Predictable Success
Unifying Design and VerificationSystemVerilog Overview
© 2006 Synopsys, Inc. (2)
Predictable Success
Agenda
• SystemVerilog Introduction• Synopsys SystemVerilog Solution• SystemVerilog Features and Successful Stories
© 2006 Synopsys, Inc. (3)
Predictable Success
Agenda
• SystemVerilog Introduction• Synopsys SystemVerilog Solution• SystemVerilog Features and Successful Stories
© 2006 Synopsys, Inc. (4)
Predictable Success
Formal
Formal
Language And Tools Fragmentation Have Led To Verification Inefficiencies
Assertions
Assertions
Coverage
CoverageSystemSystem
VIPVIP
TestbenchTestbench
Wasted Time and ProductivityWasted Time and Productivity
SimulationSimulation
HVL
Assertion/PropertyLanguage
C/C++
VHDL, Verilog
Constraints
© 2006 Synopsys, Inc. (5)
Predictable Success
SystemVerilog: Unifying Design and Verification
Simulation
Simulation
Assertions
Assertions
Coverage
CoverageSystemSystem
VIPVIP
TestbenchTestbench
FormalFormal
Fragmented Verification Single, Unified Language
© 2006 Synopsys, Inc. (6)
Predictable Success
•• BuiltBuilt--in assertionsin assertions•• Capture intent in RTL codeCapture intent in RTL code•• Pinpoint design errors quicklyPinpoint design errors quickly
AssertionsAssertionsSimulationSimulation Formal AnalysisFormal Analysis
TestbenchTestbenchCoverageCoverage
Better VBetter Verificationcation
•• Full native testbenchFull native testbench•• 22--5X faster verification5X faster verification
Verification SpeedVerification Speed
CoCo--Sim OverheadSim OverheadHDL Simulation HDL Simulation TestbenchTestbench
SystemVerilogSystemVerilog
SystemVerilog Increases Productivity•• Extends Verilog to Higher Extends Verilog to Higher
AbstractionAbstraction•• 22--5x less code5x less code•• No change in synthesis flowNo change in synthesis flow
NetlistNetlist SystemVerilog RTLSystemVerilog RTLRTLRTL
Designer PerformanceDesigner Performance
© 2006 Synopsys, Inc. (7)
Predictable Success
SystemVerilog Standardization
• Approved as IEEE Std. 1800™ SystemVerilog• Standardized under IEEE Corporate Program• Broad industry support with over 75 products• Rapid user momentum
© 2006 Synopsys, Inc. (8)
Predictable Success
IEEE Approves SystemVerilog Standard
© 2006 Synopsys, Inc. (9)
Predictable Success
Over 30 Supporting Vendors Quotes
•Synopsys•Mentor Graphics•Cadence•Magma•Real Intent•Novas•Bluespec•Denali•Ace Verification•BluePearl Software•ComputerBasedEducation•Doulos•HDL Design House•Interra Systems•Jasper•LOA Technology
•NoBug•nSys•Paradigm Works•Perftrends•PSI-Electronics & MU-Electronics•Sequence Design•Silicon Interfaces•SiMantis•Sunburst Design•Sutherland HDL•SynaptiCAD•Verific Design Automation•Verilab•VhdlCohen Publishing•XtremeEDA•Yogitech
http://www.accellera.org/pressroom/2005/IEEE_SV_PR_Quotes_110805_V2.pdf
© 2006 Synopsys, Inc. (10)
Predictable Success
IEEE SystemVerilog LRM Available
© 2006 Synopsys, Inc. (11)
Predictable Success
Over 75 Products Announced with SystemVerilog Support*
*www.systemverilog.org
© 2006 Synopsys, Inc. (12)
Predictable Success
Authors and Publishers Recognize Importance of SystemVerilog
© 2006 Synopsys, Inc. (13)
Predictable Success
SystemVerilog User Momentum Confirmed by ESNUG Surveys
SystemVerilog Use GrowingSystemVerilog Use Growing
4%
20%
15%
94%
8%
17%
44%
80%
0% 20% 40% 60% 80% 100%
SystemC
VHDL
SystemVerilog
Verilog
Within One YearCurrent
SVA Adoption IncreasingSVA Adoption Increasing
18%
17%
7%
7%
34%
8%
14%
12%
18%
21%
0% 20% 40%
0-In
OVL
OVA
SVA
PSL
20052004
Whose SystemVerilog toolsWhose SystemVerilog toolsare you using ?are you using ?
Cadence 6%
Mentor15%
Synopsys 79%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90%
With such dominance it is obvious why people use the phrase “Synopsys SystemVerilog” – John Cooley
Source: www.deepchip.com
© 2006 Synopsys, Inc. (14)
Predictable Success
Agenda
• SystemVerilog Background• Synopsys SystemVerilog Solution• SystemVerilog Features and Successful Stories
© 2006 Synopsys, Inc. (15)
Predictable Success
Synopsys SystemVerilog SolutionIndustry’s First Complete Design Methodology
SystemVerilog for Design
•Higher productivity•Faster time to market•Evolutionary –improved methodology
•Same or Better QoR as Verilog
In productiontoday
Over 150 customers
using SystemVerilog
© 2006 Synopsys, Inc. (16)
Predictable Success
Agenda
• SystemVerilog Introduction• Synopsys SystemVerilog Solution• SystemVerilog Features and Successful Stories
© 2006 Synopsys, Inc. (17)
Predictable Success
SystemVerilog for Design Support2007.06: Design Compiler, VCS, Leda, and Formality
Interface as a signal container and module port replacement Interface ports and modportsInterface bundles of ANSI module ports "\" multi-line macro continuation Macro arguments in strings Attributes extended to SystemVerilog User-defined Types (typedef) Structures“.” OperatorSupport for scopingLogic (4-value) Data TypeInteger Data Types (int, bit) Enumerations Unsized literal ('0, '1, 'x, 'z)Matching end block nameDatatype parameter SystemVerilog Assertion parsing Always_comb, always_ff, always latchReturn statement in functionsUnique/priority case, casex, casez
Arrays of structures Packed arrays of packed dataExpression Size System Function ($bits) All types as legal module portsAll types a legal task/function argument types and legal function return typesImplicit .name and .* port connections Unions (packed) Auto-operators: "+= -= ++ -- &= I= ^=" Auto-operators: “<<=>>=<<<=>>>=" Parameterized InterfacesInterface Tasks & Functions Void functions Logic default task/function argument type Input default task/function argument direction Array Querying ($length, $left, $right)Array Querying ($low, $high, $increment, $dimensions)Looping constructsCasting
© 2006 Synopsys, Inc. (18)
Predictable Success
Higher Level of Abstraction
module fifo (clk, rstp, din_src,din_dst, din_data,readp,writep,dout_src,dout_dst, dout_data,emptyp, fullp);input clk;input rstp;input [7:0] din_src;input [7:0] din_dst;input [31:0] din_data;input readp;input writep;output [7:0] dout_src;output [7:0] dout_dst;output [31:0] dout_data;output emptyp;output fullp;
. . .
Verilog SystemVerilog
typedef struct {logic [7:0] src, dst;logic [31:0] data;
} packet_t;
Define Once
module fifo ( input clk,input rstp;input packet_t din,input readp;input writep;output packet_t dout;output logic emptyp;output logic fullp
);
packet_t is a port
Use many times
© 2006 Synopsys, Inc. (19)
Predictable Success
SystemVerilog Interfaces• Encapsulate communication
Define once and reuseSignal declarationsDefine and check protocol
interface ChBus (input bit clk);bit req, gnt, rdy;bit [31:0] addr;pkt_t data;modport master(...);modport slave(...);task read(...);task write(...);assert property(...);
endinterfacemodule foo(interface ChBus);...
ChBus
clk
dataaddrreqgntrdy
Assertionread
write
• Can be designed & verified separatelyBlock-based design of communicationSynthesizableAssertions for built-in protocol checking
• Supports multiple levels of abstractionInclude logic processes if necessary
© 2006 Synopsys, Inc. (20)
Predictable Success
SystemVerilog Interfaces Exampleinterface simple_bus;
logic req,gnt;logic [7:0] addr,data;logic [1:0] mode; logic start,rdy;
endinterface: simple_bus
module memMod(interface a, input bit clk);
logic avail;always @(posedge clk)
a.gnt <= a.req & avail;endmodule
module cpuMod(interface b,input bit clk);
endmodule
module top;bit clk = 0;simple_bus sb_intf;
memMod mem(sb_intf, clk);
cpuMod cpu(.b(sb_intf),.clk(clk));
endmodule
Top
CPU Memsb_intf
clk
Bundle signals in interface
Use interfacekeyword in port list
Refer to intf signals
interface instance
Connect interface
© 2006 Synopsys, Inc. (21)
Predictable Success
Consumer Electronics Company SystemVerilog Assertions Success
•• Unnecessary read/write operations Unnecessary read/write operations found & correctedfound & corrected
•• Power consumption reduced 10%Power consumption reduced 10%
Confirm the cause of the bugwith waveform viewer
Find the bug with assertion Find the bug with assertion during the simulationduring the simulation
SimulationWith SVA
RTL description
Simulationwith VCS
Debugging with waveform viewer
Find bug from image file
Conventionalsimulation
© 2006 Synopsys, Inc. (22)
Predictable Success
ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog
SystemVerilogbuilding block
library
VMM Standard Library VMM Standard Library included with VCSincluded with VCS
Now also available in Japanese language
© 2006 Synopsys, Inc. (23)
Predictable Success
Industry’s First Verification Library with Support for SystemVerilog and VMM
VCS Verification Library• 5X higher verification
performance with VCS and Pioneer-NTB
• Supports industry’s popular bus standards
• VMM-compliant Reference Verification Methodology
© 2006 Synopsys, Inc. (24)
Predictable Success
SystemVerilog Summary
• Industry-Standard Hardware Description & Verification Language
• Broad Industry Support & User Adoption
• Synopsys Offers Strongest SystemVerilog Design & Verification Solution
• Start Benefiting from SystemVerilog’s Higher Productivity Today!
© 2006 Synopsys, Inc. (25)
Predictable Success
AMCC Speeds Verification with VCS SystemVerilog Testbench
© 2006 Synopsys, Inc. (26)
Predictable Success
Exar Triples Verification Productivity with VCS SystemVerilog Testbench
© 2006 Synopsys, Inc. (27)
Predictable Success
ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog Published
© 2006 Synopsys, Inc. (28)
Predictable Success
Synopsys Announces Source-Code License for SystemVerilog Verification Library
© 2006 Synopsys, Inc. (29)
Predictable Success
Synopsys Introduces Pioneer-NTB for SystemVerilog Testbench Automation
© 2006 Synopsys, Inc. (30)
Predictable Success
ARM-Synopsys VMM Endorsed by Leading Japanese Companies
© 2006 Synopsys, Inc. (31)
Predictable Success
Synopsys Delivers First Complete SystemVerilog Design & Verification Flow
© 2006 Synopsys, Inc. (32)
Predictable Success
Industry’s First Verification IP Library for SystemVerilog & VMM
© 2006 Synopsys, Inc. (33)
Predictable Success
S3 Adopts Synopsys’ VCS Verification Solution and the Verification Methodology Manual for SystemVerilog