© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Greg Armstrong (Integrated Device Technology, Inc.)
March 18th, 2019
TUTORIAL: Phase Locked Loops
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Outline
• Phase Locked Loops (PLL)- Principle
- Response To Injected Noise
• PLL Operation Modes- Locked, holdover and freerun
• PLL with 2 inputs
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Phase Locked Loops (PLL)
© Copyright 2018, IDT Inc. Analog Mixed-Signal Systems
PLL: Working principle
• A phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal
– Bringing the output signal back to the input signal for comparison is called a feedback loop
• By keeping the input and output phase in lock, this implies that the input and output frequencies are the same as well
• PLLs generally generate an output frequency that is a multiple, or even a fractional multiple, of the input frequency
– May requires an integer, or fractional, divider on the feedback
– May require an integer, or fractional, divider on the input as well
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Phase
Comparator
Loop
Filter
Voltage
Controlled
Oscillator
( )INu t ( )OUTu t
0,
0,
( ) sin 2 sin 2
( ) sin 2 sin 2
IN NOM IN
OUT NOM
IN
OOU
IN
OT UT TU
u t A t A
u t A t A
t
t t
x
x
t
P
PNO
M
IN
OU
T
u
K
x
x
( )C
P
ut
ut
gt
0
OUT
C
V
uK
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL: Phase Comparator
• The Phase Comparator establishes the “error” between the reference input and the clock output; using a feedback
• Most Digital PLLs (DPLLs) use a Time to Digital Converter (TDC) and Phase Frequency Detector (PFD) to measure the phase of the two clocks and produce a digital word representing the error
- TDC can be looked at as a timestamper
• The TDC timestamps the reference and feedback edges, and the PFD mathematically tracks the phase offset between the selected reference and feedback clocks
• The measured phase difference can go well beyond 1 period, or Unit Interval (UI), of the reference and feedback clocks; thus, the phase comparator must be able to measure over a large range of multiple input/feedback clock periods
- Various telecom standards define a jitter & wander tolerance requirement - the widest is defined is 18µspp
- For example, if the input clock has a nominal period of 8ns (125 MHz), then the jitter tolerance requirement equates to ± 1125 UI
5
Ref (In)
Feedback (from Controlled Oscillator)
Phase Error (to Loop Filter)
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL: Loop Filter
• The phase error is processed by the loop filter (LF)
- LF is a combination of proportional and integral (PI) control, which generates a control signal for controlling the oscillator
• The LF determines the bandwidth (BW) of the PLL
- Other functionality, such as phase slope limiting (PSL), locking range, and holdover functionality may be done as well
• Phase corrections mainly done through proportional path, along with any PSL
• Frequency offset, or drift corrections, is done through the integrator path, including damping (i.e. gain peaking control)
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Control Signal (to Controlled Oscillator)Phase Error (from Phase Comparator)
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL: Controlled Oscillator
• The controlled oscillator uses the control signal to speed up or slow down the output clock
• Most Digital PLLs replace the Voltage Controlled Oscillator (VCO) by a Digitally Control Oscillator (DCO) consisting of:
- a free-running crystal oscillator (XO)
- A digital synthesizer which pulls the frequency up or down using a Control Signal from loop filter (a digital word representing a fractional frequency offset (FFO))
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Clock (Out)
Feedback (to Phase Comparator)
Control Signal (from Loop Filter)
‘Frequency
Puller’
Free-running
Oscillator
Replaces the VCO
DCO: Digitally
Controlled Oscillator
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL: Phase-time deviation x(t)
Note: Phase-time x = random component only
Time Error TE = random and deterministic components
t1 t1 + x(t1)
nominal signal
actual signal
sin 2
sin 2
NO
NOM
M
t x t
t
x(t1)
t
8
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL: Response to Injected Noise
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PLL is a low-pass filter for input noise
PD LPF DCOPhase
Noise (In)
Phase
Noise (Out)
Oscillator
FL
Phase Noise (Out)
Phase Noise (In)
PLL is a high-pass filter for oscillator noise
PD LPF DCO
Phase Noise (Oscillator)
Phase
Noise (Out)Ref (In)
FH
Phase Noise (Out)
Phase Noise (Osc)
20
20
lo
log 2 [dB]
g 2 [dB]
IN
OSC
H j
H j f
f
20
20
lo
log 2 [dB]
g 2 [dB]
IN
OSC
H j
H j f
f
where impulse response
transfer function Laplace
OUT IN IN
OUT IN IN
IN
IN IN
x t x t h t
X s X s H s
h t
H s h t
where impulse response
transfer function Laplace
OUT OSC OSC
OUT OSC OSC
OSC
OSC OSC
x t x t h t
X s X s H s
h t
H s h t
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
0
100 200
t [s]
xIN(t) [s]
xOUT(t) [s]
1 x 10 - 6
5 x 10 - 7
- 5 x 10 - 7
- 1 x 10 - 6
PLL: Jitter & Wander filtering
• What is jitter/wander?- Noise or other disturbances
on the clock when compared to an ideal referenceo Jitter = short-term variations
o Wander = long-term variations
- ITU-T G.810 defines noise frequencies <10Hz as wander and frequencies >10Hz as jitter
• The function of a PLL is to attenuate jitter and transfer wander
- In other words, tolerate noise at the input without losing lock to the reference
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL Operation Modes
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL Modes: Locked, holdover and freerun
• Locked mode: clock has a valid input signal, PLL loop is closed, i.e. switch is in position 1.
• Freerun & holdover modes: no valid input signal is detected, controller switches to position
2, clock becomes an autonomous synchronization source.
P. C. L. F.
MEM
VCO
CONTROLLER
1INOUT
2
Holdover: memory MEM remembers last
locked mode frequency
Freerun: value in the holdover memory
is invalid or outdated
After entry into freerun or holdover
mode, frequency is subject to ageing
drift and to the influence of temperature.
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL Modes: Holdover @ constant temperature
Fractional frequency:
Time error:
0
0
( )
where initial frequency offset
frequency drift rate (constant)
y t y D t
y
D
2
0 0
0
0
( )2
where x initial phase offset
initial frequency offset
frequency drift rate (constant)
Dx t x y t t
y
D
t
y(t)
t
D∙ t
y0
x0
y0∙ t
x(t)
t2D
2
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
PLL with 2 Inputs
© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Combining two PLLs
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F2
Phase Noise (Out2)Phase Noise (In2)
F1
Phase Noise (Out1)Phase Noise (Osc1)
Phase Noise (Out2)Phase Noise (Osc2)
Phase Noise (Out1)Phase Noise (In1)
PD LPF DCOPhase
Noise (In2)Phase
Noise (Out2)
Phase Noise (Osc2)
PD LPF DCO
Phase Noise (Osc1)
PhaseNoise (Out1)
PhaseNoise (In1)
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Two PLLs: Response to Injected Noise
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PD LPF DCO
PD LPF DCOPhase
Noise (Out)
PhaseNoise (In1)
PhaseNoise (In2)
Phase Noise (Osc2)
F2F1
Band-pass filter for In2 Noise to Out
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Two PLLs: Spectral densities
(log-log scales)
│SIN1 (f)│
f [Hz]
│SIN2 (f)│
│SOSC (f)│
(log-log scales)
f [Hz]
│SOUT (f)│
OSC
IN 1
IN 2
OUT
Three spectral densities
(phase-time) …
… combined by the 2-input
PLL, …
… result in this out spectral
density:
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
Two PLLs: Applications
• GNSS & Cesium clock in enhanced Primary Reference Time Clocks (ePRTC)
• PTP & SyncE in boundary clocks (T-BC) and slave clocks (T-TSC)
• Note: PLL with 2 inputs is not the only way of combining 2 references
Combiner
GNSS
receiver
Cesium
clock
ePRTC
Output Line
Interface
Input Line
Interface
T-BC
Time
Clock
Physical
Layer
Clock
PTP Slave
Eingne
PTP Master
Engine
PTP PTP
PHY PHY
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© Copyright 2019, IDT Inc. Analog Mixed Signal Systems
T-BC: Response to Injected SyncE Noise
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A band-pass filter for SyncE Noise to PTP (Out)
PD1.1Hz
LPFDCO
SyncENoise (In)
SyncE (Out)
92mHz
LPFDCO PTP (Out)
Time Stamp Unit(TSU)
PTP StackPTP
Network
offsetFromMaster
TCXO
T-BC1
PRTC T-GM
T-BC2 T-BC9 End App.
Very little PDV
Amplitude, dB
0.05 0.1 Frequency, Hz 1 10
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