7/31/2019 Timing Yield of Sequential Networks
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Computation of joint timing yield of sequential networks considering process
variations
Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma Vrudhula
Consortium for Embedded Systems
School of Computing and Informatics
Tempe AZ
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PATMOS'07 Sarma Vrudhula - ASU 1/14
Introduction
Essential capability for cost effective, timely design of a multi-million device IC is
accurate estimation of parametric Yield prior to manufacture
Parametric Yield: fraction of ICs that satisfy constraints on
performacnce, power
Static Timing Analysis has been the primary method Cell library characterization
d(L, VT, Tox, . . .) of a cell computed using numerical analysis
software (SPICE) at various points (L, VT, Tox, . . .)
Network delay
computed using a single pass PERT-like forward traversal required times by backward traversal from output FFs to input FFs
Optimization
sizing, re-timing, re-synthesis, . . . .
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Process Variations
Manufacturing Variations
intrinsic part of any manufacturing process
traditional approach: use STA at process corners
process corners: all combinations of extreme values of parameters
implicit assumption of independence
OK if we have only a few dominant parameters (Vt, Le, W)
Nanoscale regime - loss of predictability
number of parameters that vary, magnitude of the
variations and sensitivity to variations are all increasing huge number of process corners
process corners leads to over design, negating scaling advantages
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Scope of this work
Estimation of timing yield of sequential networks
considering intra-die process variations - SSTA
Statistical delay characterization of cell library each cell has a symbolic delay expression as a function of the
process parameters - random variables
Spatial correlations modify cell delay expression when placed
delays of all gates in terms of common set of RVs
Calculation of Circuit Delay efficient propagation of delay expressions to outputs
Sequential circuits model FF and clock parameters as random variables
timing constraints of all FFs expressed in terms of common set
of RVs
express for timing yield as a funtion of all random variables
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Modeling Variations
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No algebraic or other analytical representation of d(p*)
Given p*, d(p*) can be computed using SPICE
Seek “ optimal ” representation of d in terms of p*
d(p*) belongs to a Hilbert space with a polynomial basis
Cell Delay Characterization
Delay of a cell
Restrict d to be order q: Then
roots of (q+1) order polynomials .
(q+1)m terms
probability densities
of p* in here!
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Chip level
Gate Delay
13
2
4
N gates
Cell level
mN random variables is huge
Need to express delays of cells in terms of one set of
common spatially correlated RVs
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Spatial Correlations
For
a spatial covariance function or matrix. Then
let be
independent N(0,1) RVs
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Circuit Delay
Canonical form for gate delays & signal arrival times
d( )
Main difficulty: computation of γ coefficients
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Circuit Delay (cont’d)
Using Gaussian Quadrature, computing all coefficients
requires O(r 2 3r ) evaluations. m = 3, M = 10, r = 30.
Developed a bounded error approximation to compute
max of two quadratic delay expressions: O(r 2)
evaluations.
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Final Result of Delay Propagation
1
2
3
4
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Timing Yield of Sequential Circuits
FF parameters and Clock arrival times are RVs
Setup & Hold time constraints are functions of RVs
Characterize FFs for Setup & Hold times and C-Q delay
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Timing Yield
Setup & Hold time constraints expressed as aquadratic polynomial in ξ
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Some Other work in SSTA
Discrete Distributions
Devgan-ICCAD’03 - Numerical convolutions and multiplications
Bhardwaj-ICCAD’03 - Bayesian Networks
Continuous non-Linear Delay Models:
Zhan-DAC05, Zhang-DATE06: Quadratic models of Gaussian RVs
Chang-DAC05: Numerical integration for non-Gaussian
Non-Gaussian Distributions:
Some sources of variations might not be Gaussian
Singh-DAC’06: Independent component analysis
Skewed Normal Distributions:
Chopra-ICCAD’06: Asymmetric distributions
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Cell Delay Characterization
90 nm Tech. BSIM3 BPTM Models, HSPICE
Inter-gate Gaussian variations in
in the variables
Order 2 expansion in Hermite polynomials
Order 3 quadrature: 81 samples (Gaussian) [GA10]
Number of Monte Carlo Samples - 10000
Delay, Slew analysis
Rise and Fall Delays - 20,000 samples in all
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Cell Delay Characterization (cont’d)
Gauss Quad - 81 samples,
MC - 10000 samples
Ave. Monte Carlo simulation time per Gate = 36 min.
Ave. Gaussian Quadrature time per Gate = 0.29 min.
Ave. Speed-up over Monte Carlo = 120X
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Circuit Delay Simulation Setup Delay models for library cells and EDFF using 90nm BSIM4 PTM
Parameters: (Vtn, Vtp, Le, Tox). 3σ
value of each 10%
ISCAS’89 sequential benchmark circuits
technology mapping to cell library using SIS v1.3
Place and Route of netlist done using MetaPlacer of UMPack
Radial exponential covariance used to model spatial correlations
Discrete version of KLE using n x n grid. 4n2 = 36 random variables
Quadratic Monte Carlo
Generate random variables for each gate
Transform to uncorrelated RVs ξ
Compute gate delays using pre-characterized equations
Perform STA (propagate delays)
Repeat 10,000 times
Quadratic SSTA
Generate ξ. Compute delay expression associated with output
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Circuit Delay Results
µquad µMC quad (%) lin (%) quad MC quad (%) lin (%) MC (Hr) SSTA (Min) Speedup
s38417 23815 1636 422.60 422.10 0.10 2.43 10.10 12.30 17.80 64.80 11.78 1.70 416
s38584 20705 1452 255.90 255.60 0.10 0.85 7.45 8.23 9.50 39.70 9.84 1.47 402
s35932 17793 1782 355.90 352.90 0.84 4.07 11.90 11.10 6.90 21.64 12.51 5.38 139
s15850 10369 597 704.30 704.20 0.02 0.19 22.60 22.60 0.01 48.69 5.31 1.00 319
s9234 5825 228 500.40 500.30 0.01 0.18 20.80 20.60 0.81 12.22 2.09 0.32 396
s5378 2958 179 220.57 220.54 0.01 0.15 8.73 7.90 10.50 16.30 2.16 0.38 338
s1423 731 74 983.58 983.53 0.00 0.27 28.00 28.00 0.01 60.50 0.95 0.10 567
s1238 526 18 329.16 329.12 0.01 0.13 14.60 14.60 0.00 43.70 0.46 0.10 276
s838 390 32 146.35 146.80 0.30 2.86 5.65 5.69 0.97 30.22 0.08 0.02 284
s510 211 6 128.60 128.83 0.17 1.32 5.07 5.16 1.97 26.70 0.06 0.02 202
verag 0.015 1.37 4.85 35.5 334
d)
Comparison (ps) Runtime (sec)Circuit Gates DFF's Mean (µd) Comparison (ps)
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Timing Yield Results
~400X improvement in runtime over Monte Carlo
Linear SSTA shows significant difference from MC
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Summary
Developed a methodology for the analysis of
performance in the presence of process variations.
Based on the use of Polynomial Chaos representation of
2nd order processes
Representation are optimal in expected mean square
New and efficient method to propagate quadratic delayexpressions
Several orders of magnitude speedup compared to MC
Methodology applied to
Cell and circuit delay characterization
Analysis of interconnect delay and power grid
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Q & A
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Quadratic SSTA Flow
ProcessData
DesignNetlist
CellLibrary
Process Characterization& dimensionality
reduction
Delay & Slew Models
Compute max of inputs
Compute sum of max and delay
Next Gatein Circuit?
Start
Stop
NoObtain Delay
Model for Gate
Yes
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Radial Covariance Function
Accuracy of modeling the correlation function
original correlation functionCorrelation of the approximate
process using 25 terms
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Comparison with grid-based approach
Errors in approximated correlation functions
Error compared to KLE Error compared to grid-based approachUsing same number of terms/grids
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Partitioning Sequential Circuit