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Pirouz Bazargan Sabet ValMem - March 2010

Timing Abstraction

Pirouz Bazargan Sabet

Patricia Renault

Dominique Le Dû


Functional Abstraction

Netlist Tr, C, R

Netlist of Gates, C, R

Abstraction

Timing Abstraction

Gate Delays


a

a

b

Fdown = a . b

b

Fup = b + a


Fup = Fdown

follow the current paths


a

b

c

d


conflict

tri-sta

teFup . Fdown = c.d.(ab)

Fup + Fdown = c.d

c=d

Fup = db + caFdown = db + ca

Fup = cb+ ca

functional view timing view


Delay Evaluation

xi y

Accurate delay using electrical simulation

Simulation of each configuration : 1 input

switching while others are in steady state


a

b

c

d


Fup = cb+ ca

a b c dx x x

x xx

xx x

x x x

Delay Evaluation


Include the gates until

reaching the sources

of correlation

sources of correlation

size some correlations are not useful number of configurations

Delay Evaluation


Explore the supergate to

identify the configurations

to be simulated

sources of correlation

Delay Evaluation

Functional exploration


a

b

c

d


Fup = cb+ ca

a b c dx x x

x xx

xx x

x x x

Delay Evaluation

x x


Functional correlation :

Delay Evaluation

a b

x

inputs

configstiming correlation

transition delay between a and b depends on the

delay of the gates involved in the supergate

Electrical simulations should be

done regarding the gates’ graph


Delay Evaluation

Timing dependency