MonolithIC 3D Inc. Patents Pending 1
The Monolithic 3D-IC
A Disruptor to the Semiconductor Industry
Monolithic 3D Provides an Attractive Path to…
• 3D-CMOS: Monolithic 3D Logic Technology
• 3D-FPGA: Monolithic 3D Programmable Logic
• 3D-GateArray: Monolithic 3D Gate Array
• 3D-Repair: Yield recovery for high-density chips
• 3D-DRAM: Monolithic 3D DRAM
• 3D-RRAM: Monolithic 3D RRAM
• 3D-Flash: Monolithic 3D Flash Memory
• 3D-Imagers: Monolithic 3D Image Sensor
• 3D-MicroDisplay: Monolithic 3D Display
Monolithic 3D Integration
with Ion-Cut Technology
Can be applied to
many market
segments
LOGIC
MEMORY
OPTO-ELECTRONICS
FPGAs: The 3D-TSV Solution
MonolithIC 3D Inc. Patents Pending
Reinventing FPGA using 3D-TSV
Use different dies for: Programmable Logic Programmable I/O Programmable Memory
Build Reticle Size with Multi-Dice Lines for each ~One Mask set with many die/functions size options Choice of process node and fabrication processes
Traditional FPGA Wafers vs. Continuous Array Wafers
Scribe lanes
Scribe lanes
FPGA Logic-only
chunk
Continuous Array of Logic at 22nm Wafer of IO Chiclets at 0.15
TSVsTraditional wafer of chips
TSV
FPGA chip with
IO
IO “chiclet” with TSV
prep
Scribe lane
FPGA Logic-only
chunk
Chip size 9
Chip size 4
Chip size 20
Long metal tracks cross scribe lines
Die edges need to be sealed after cut
Top wafer prepped for TSVs or micorbumps in standard pattern (“socket”) over logic chunks
Continuous Array Terrain Allows Defining Custom Logic Sizes from Same Wafers
Assembling Continuous Array Terrain into Customized Hybrid Stacks
• Chiclets assembly actually happens prior to wafer dicing
Chip with logic
size 9
Chip with TSV visible
IO 0.15
memory 22 nm
SerDes 90 nm
3D Hybrid stack with
TSVs
TSV prep
Standard TSV pattern
Chiclets
Advantages of 3D-TSV FPGA
Good Fit for the End User Application with optimal size of silicon - ~2-5 x cost reduction
Wide range of technologies and function Reduce cost by using low cost old process for I/O Increase functionality to match user alternative SC Allow integration of additional vendors with their own
dies
Huge reduction of $$$ for masks
Future SoC New Logic 15%
FPGAs: The Monolithic 3D Solution
MonolithIC 3D Inc. Patents Pending
3D IC Next Generation – Monolithic 3D
TSV: TSV-3D IC Monolithic: Nu-3D IC
Layer Thickness ~50 50-100nm
Via Diameter ~5 ~50nm
Via Pitch ~10 ~100nm
Limiting Factors Wafer handling (~5Aspect ratio (<10:1)
Lithography=>Will keep scaling
Wafer (Die) to Wafer Alignment
~1 Layer to Layer Alignment
=> Will keep scaling
Monolithic 3D vs. TSV
(1:10,000 vertical connectivity ratio)
MonolithIC 3D Inc. Patents Pending 12
Layer Transfer Technology (“Ion-Cut”) Defect-free single crystal formed @ <400oC
p- Si
Oxide
p- Si
Oxide
H
Top layer
Bottom layer
Oxide
Hydrogen implant
of top layer
Flip top layer and
bond to bottom layer
p- Si
Oxide
Cleave using 400oC
anneal or sideways
mechanical force. CMP.
Oxide
p- Si
Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today
Foundation – Pre-fabricated High Voltage Programming Transistors (‘Older’ Process)
Thin crystalline silicon layer
‘Smart Cut’
Oxide to oxide bonding
Cleavable wafer
Programming Transistors
High temp interconnect (tungsten)
IsolationTransistors
House
Foundation
Programmable interconnect
Crystalline Silicon (base wafer)
Crystalline Silicon
Antifuses
Interconnect
Primary Device (‘House’) on top of the Foundation
Vp+ Vp-
Vp+Vp+
Vp+Vp+
Vp+Vp+
Vp+Vp+
Vp+Vp+
Vp+Vp+Vp+
Vp+Vp+ Vp-
Vp-Vp-
Vp-
Vp-Vp-
Vp-Vp-
Vp-
Vp-Vp-
Vp-Vp-
12
3.
.
N
M
32
1
..
M x N fully populated antifuse crossbar
In the House
House
Foundation
M + N Programming transistors
In the Foundation
3D Antifuse Connectivity ~ ASIC Connectivity
Future Monolithic 3D FPGA
Multi-Tier Programmable Logic Tier 0 – The LUT Array + Local programmable interconnect Tier 1 – The Clock distribution Network + programmable
power distribution Tier 2 – Short Programmable Interconnect Tier 3 – Long Programmable Interconnect
Reinvented PIC Antifuse 1T Memory cell instead of the 6T
Flash DRAM …
Summary
Interconnects are now dominating all logic devices Early innovations of 3D FPGA stimulate more ideas FPGA vendors are moving into 3D (so far 2.5D) Future FPGAs will utilize 3D technology to Reinvent
the FPGA TSV to re-architect the FPGA system Monolithic to re-architect the programmable logic fabric
The Future is in the Third Dimension – 3D