Test Setup for FE-I3 single chips / modules, FE-
I4_proto1 and for full scale FE-I4
Marlon Barbero, Bonn
H. Krüger, ATUW, NIKHEF, 6.11.08
USBPix – Lightweight USB based DAQ System for FE-I3 / FE-I4
H. Krüger, ATUW, NIKHEF, 6.11.08
USB Controller FPGASRAM AC coupling
Multi-IO USB/FPGA Board Quad Module Adapter Card
FE-I3 Module with Flex Adapter
type-0 connector
single chip card con.
H. Krüger, ATUW, NIKHEF, 6.11.08
TurboDAQ
Graphical User Interface
(LabWindows/CVI, C code)
Wrapperhigh level FE functions (histogramming etc.)
USBPix.DLL
USB lib(standard)
FE-chiplow level functions
USB MultIO Board
USB Controller(standard)
FPGA(FE specific)
Quad Pixel ModuleAdapter Card
Pixel ModulePixel Module
Pixel ModulePixel Module
Single Chip
Single Chip
Single Chip
Single Chip
or
corresponding tasks
corresponding tasks
corresponding tasks
Software Hardware
USB
USB based FE-I3 Readout System - USBPixBoard
• Lightweight “Replacement” for the TurboPLL/PCC
• (Re)use TurboDAQ software ?
• Hardware based on FPGA card with USB interface
• Supports up to four single chips or four FE modules
• AC coupling for SP operation of modules
H. Krüger, ATUW, NIKHEF, 6.11.08
Firmware Structure
8051 µC
US
B
configuration state machine
strobe & LV1state machine
data receiverstate machine
reset/sync state machine
readdata buffer
& event builder
write data buffer(parser)
data memory
LDDICCK
SYNCRST
LV1
DO1
DO2
histogrammingstate machine
scan routines
full chip scan data:2880px 256 steps 8bit
data
clock XCK
USB controller
FPGA
external
STRB
external trigger
master state machine
H. Krüger, ATUW, NIKHEF, 6.11.08
USBPixBoard – Some Specs
• USB/FPGA Board (S3MultiIOBoard)– 15 Mbyte/sec FPGA PC data transfer– 2 Mbyte SRAM (sufficient for full single chip histogram)– Xilinx XC3S1000 FPGA– LVDS and TTL IOs (for ext. trigger, TDC etc.)– 8051 USB microcontroller– Drivers for Windows XP and Linux
• Module Adapter Card – four channels support single chip cards or modules– serial powering option for modules– current and (individual) voltage measurement for SP
• “Lightweight”/low-cost replacement for TPLL/TPCC– limited FPGA/memory resources: no DSP, no dedicated, programmable
delay lines
H. Krüger, ATUW, NIKHEF, 6.11.08
USBPixBoard – Status
• Target: FE-I3 single chip, (FE-I4 proto 1), FE-I4 ‘full chip’
• Hardware– prototype HW, production of ~20 boards planned
– FPGA + µC firmware and DLL programming UBonn
• Software– Based on DLL with low-level functions + GUI (two options):
a. Modified TurboDAQ software UGöttingen, Jörn Grosse-Knetter
b.New PixLib based SW development (C++, QT for Win & Linux), “open source”, access via
version control system and Wiki pages:
http://icwiki.physik.uni-bonn.de/twiki/bin/view/Systems/WebHome#UsbPix
Marlon Barbero - Bonn, Test Setup for ATLAS pixel FEs, Dec. 2nd 2008 8
FE-I4_proto1 test setup
Marlon Barbero - Bonn, Test Setup for ATLAS pixel FEs, Dec. 2nd 2008 9
FE-I4_proto1 test setup
Software
11
Hubertus Junker sLHC meeting 26.11.2008
InterfaceDisabled!
12
Hubertus Junker sLHC meeting 26.11.2008
Parametric scan
Threshold
Noise
13
Hubertus Junker sLHC meeting 26.11.2008
Addressing new
Hitmap
Inject
Filter interesting hit
anddo the math
14
Hubertus Junker sLHC meeting 26.11.2008
Status
MUX arrived last week
were installed successfully Test without FE good! FEI4_proto1 connected to Testboard
Due to bad connection so pins had to be bend up
Plans: Finish Software development start characterization. Should submit new version of test board with proper
MUX connection.