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FT/GN/68/00/23.01.16SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 1 of 6

Department of Information TechnologyLP: CS6303

Rev. No: 00

Date: 01-07-2016B.E/B.Tech/M.E/M.Tech : B.Tech Information Technology Regulation: 2013

Sub. Code / Sub. Name : CS6303 / Computer Architecture

Unit : I

Unit Syllabus:

OVERVIEW & INSTRUCTIONS:Eight ideas – Components of a computer system – Technology – Performance – Power wall – Uniprocessors to multiprocessors; Instructions – operations and operands – representing instructions – Logical operations –control operations – Addressing and addressing modes.

Objective:

To differentiate various functional units, Uniprocessor to multiprocessor, instructions, control and logicaloperations, addressing modes.

SessionNo *

Topics to be covered Ref Teaching Aids

1 Introduction to computer architecture, Eight ideas T1-Ch12;Pg.3-4 BB/LCD

2Components of a computer system, Technology T1-Ch.1;Pg.4-25, BB/LCD

3 Performance, Power wall, SPEC benchmark T1-Ch.1;Pg.26-40, BB/LCD

4Uniprocessors to multiprocessors T1-Ch.1;Pg.41-42,

BB/LCD

5Instructions: Language of the machine, Operations of computer hardware, Operands of computer hardware

T1-Ch.2;Pg.76-86BB/LCD

6Representing instructions in the computer

T1-Ch.2;Pg.94-101 BB/LCD

7 Logical operationsT1-Ch.2;Pg.102-104

BB/LCD

8Instructions for making decisions, Control operations, supporting procedures in computer hardware


9 Addressing and addressing modes - MIPS Addressing Mode Summary, Decoding Machine Language

T1-Ch.2;Pg.112-116, BB/LCD

Content beyond syllabus covered (if any): SPEC benchmark, supporting procedures in computer hardware.

* Session duration: 50 minutes



Sub. Code / Sub. Name: CS6303 / Computer Architecture

Unit : II

Unit Syllabus:

ARITHMETIC OPERATIONS ALU - Addition and subtraction – Multiplication – Division – Floating Point operations – Subword parallelism.

Objective:

To gain knowledge about the various arithmetic operations that performed by ALU.

SessionNo *

Topics to be covered RefTeaching

Aids

10 Designing of ALU, signed and unsigned numbers, Addition and subtraction,

T1-Ch.3;Pg.224-229,

BB/LCD

11 Multiplication - Sequential Version of the Multiplication Algorithm and Hardware, Example for a multiply algorithm, Signed multiplication T1-Ch.3;Pg.230-237,

,

BB/LCD

12 Faster multiplication, Multiply in MIPS, summary, Division – A division algorithm and hardware T1-Ch.3;Pg.237-241, BB/LCD

13 Example for a divide algorithm, signed division, Faster division, Divide in MIPS

T1-Ch.3;Pg.237-241, BB/LCD

14 Floating Point - Floating point representation, Floating point addition, Binary floating point addition

T1-Ch.3;Pg.242-2249,

BB/LCD

15 Floating point multiplication, Binary floating point multiplication, Floating point instructions in MIPS, Accurate arithmetic

T1-Ch.3;Pg.249-265T1-Ch.9;Pg.337-342, T1-Ch.3;Pg.298-300 BB/LCD

16 Subword parallelismSubword Parallelism With Max-2, Ruby B. Lee, HP. BB/LCD

Content beyond syllabus covered (if any): Using a Hardware Description Language, Verilog.

* Session duration: 50 mins




Unit : III

Unit Syllabus:

PROCESSOR AND CONTROL UNIT Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining – Pipelined datapath and control – Handling Data hazards & Control hazards – Exceptions.

Objective:

To expose the students to the concept of pipelining.

SessionNo *


Aids

17 Basic MIPS implementation – An overview of the implementation, Logic design conventions.

T1-Ch.4;Pg.303-306, BB/LCD

18 Building a datapath, creating a single data path, Example for building a data path


19 Control implementation scheme – The ALU control, Designing the control unit, operation of the data path

T1-Ch.4;Pg.259-26

BB/LCD

20 Finalizing Control, example for Implementing Jumps, Why a Single-Cycle Implementation Is Not Used Today


21 Pipelining-An overview of pipelining, designing instruction sets for pipelining, pipeline hazards, structural hazards, data hazards

T1-Ch.4;Pg.331-347, BB/LCD

22 A pipelined datapath, graphically representing pipelines T1- Ch.4;Pg.347-349 BB/LCD

23 Pipelined control, seperation of control lines according to pipeline stage


24 Data hazards: Forwarding versus Stalling, Dependence detection T1 -Ch.4;Pg.355-363 BB/LCD

25 Data hazards and stalls, Control hazards, Assume branch not taken, Reducing the delay of branches, Pipelined branch example

T1-Ch.4;Pg.363-370, BB/LCD

26 Dynamic branch prediction, Example for Loops and prediction, Branch hazards


27 Exceptions - How Exceptions Are Handled in the MIPS Architecture, Exceptions in a Pipelined Implementation, Exception in a Pipelined Computer example


Content beyond syllabus covered (if any): Nil





Unit : IV

Unit Syllabus:

PARALLELISM Instruction-level-parallelism – Parallel processing challenges – Flynn's classification – Hardware multithreading – Multicore processors

Objective:

To expose the students to the concept of parallel processing architectures.

SessionNo *


Aids

28 Parallelism and Advanced Instruction-Level Parallelism, The Concept of Speculation, Static Multiple Issue, An Example: Static Multiple Issue with the MIPS ISA

T1-Ch.7;Pg.632-634- BB/LCD

29 Example for Simple Multiple-Issue Code Scheduling, Example for Loop Unrolling for Multiple-Issue Pipelines, Dynamic Multiple-Issue Processors


30 Dynamic Pipeline Scheduling, limited amounts of ILP also limit the extent to which such stalls can be hidden. Power Efficiency and Advanced Pipelining

T1-Ch.7;Pg.645-648

BB/LCD

31 Challenges of parallel processing T1-Ch.7;Pg.650-652BB/LCD

32 Flynn's classification T1-Ch.7;Pg.654-664 BB/LCD

33 Hardware multithreading T1-Ch.7;Pg.664-667BB/LCD

34 Multicore processors and their performance, Performance and energy efficiency of the Intel core i7 Multicore


35 Putting multicore and SMT together, Benchmarking Four Multi cores Using the Roofline Model


36 Revision


* Session duration: 50 mins;




Unit : V

Unit Syllabus:

MEMORY AND I/O SYSTEMS Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache performance -Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts, I/O processors.

Objective:

To familiarize the students with hierarchical memory system including cache memories and virtual memory.

To expose the students with different ways of communicating with I/O devices and standard I/O interfaces.

SessionNo *


Aids

37 Memory hierarchy design – Introduction, Basics of Memory Hierarchies: An quick review

T1-Ch.5;Pg.457-475, BB/LCD

38 Memory technology and Optimizations, SRAM Technology, DRAM technology, Improving memory performance inside a DRAM chip T1-Ch.5;Pg.475-482 BB/LCD

39 The Basics of Caches, Accessing a Cache, Handling Cache Misses, Handling Writes, Designing the Memory System to Support Caches


40 Measuring and Improving Cache Performance, Calculating Cache Performance and Average Memory Access Time, Locating a Block in the Cache, Reducing the Miss Penalty Using Multilevel Caches


41 Virtual memory, Placing a Page and Finding It Again, Page Faults, Integrating Virtual Memory, TLBs, and Caches, Implementing Protection with Virtual Memory, Handling TLB Misses and Page Faults

R2-Ch.5;Pg.492-500 BB/LCD

42 Input/output system R2-Ch.5;Pg.337-359BB/LCD

43 programmed I/O R2 -Ch.4;Pg.259-272, BB/LCD

44 DMA and interruptsR2-Ch.4;Pg.234-237 BB/LCD

45 I/O processors R2-Ch.4;Pg.204-208-BB/LCD






Text Books:1. David A. Patterson and John L. Hennessey, “Computer organization and design‟, Morgan Kauffman,

Elsevier, Fifth edition, 2014.

Reference books:

2. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer Organisation“, VI edition, McGraw-Hill Inc, 2012.

3. William Stallings “Computer Organization and Architecture”, Seventh Edition, Pearson Education, 2006.

4. Vincent P. Heuring, Harry F. Jordan, “Computer System Architecture”, Second Edition, Pearson Education, 2005.

5. Govindarajalu, “Computer Architecture and Organization, Design Principles and Applications", first edition, Tata McGraw Hill, New Delhi, 2005.

6. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata McGraw Hill, 1998. 7. http://nptel.ac.in/.

http://nptel.ac.in/