• Chair: Rolf Aschenbrenner, Fraunhofer IZM• Co-Chair: Klaus Pressel, Infineon
Rolf Aschenbrenner is deputy director at Fraunhofer IZM and head of department System Integration and Interconnection Technologies. He is IEEE Fellow and has had long-term activities for IEEE.
Dr. Klaus Pressel joined Infineon in 2001, where he now focuses on innovations in assembly and packaging technology. Klaus represents Infineon in various technical committees of international conferences.
SiP and Module
“SiP, or System-in-Package, refers to a package (such as SO, QFP, BGA, CSP,LGA) that has multiple die (Si, GaAs, SiGe, and or SOI) plus optional passives integrated together. The package is typically surface mounted to the main board.” (Prismark, 2017)
“SiP is a combination of multiple active electronic components of different functionality, assembled into a single unit, that provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components and other packages and devices.” (ITRS, 2007)
“SiP module is a package that contains an electronic system or sub-system and is miniaturized through IC assembly technologies” (ASE, 2014)
SiP Definitions
Infineon´s detailing
Prismark´s Drawing
Fraunhofer IZM photonics integration
Examples of elementsfor the „Packaging Toolbox“
SiP Packaging Toolbox: Interconnect
Evolution of standard interconnect
• Wirebond and stacked wirebonds incl. copper wire
• Flip Chips and stacked flip chips (w/ TSV)
• Package on Package (PoP)
Challenges
• More IO/area, size of microbumps
• Thin chips for thinner stacks
• Warp and I/O arrangement for MtM SiP
New: Embedding Technology – Interconnect by Electroplating
• Embedding of thin active chips into the dielectric layers
• Embedding of passive components together with chips
• Embedding of SMD components for low volume and SME´s
Challenges:
• Remaining dielectric thickness decreasing
• Lines/spaces and via Ø @ HDI substrates, by shrinking the chip pitch
• Multi material challenge (Si, dielectric, EMC, underfill, die attach …)
Concept Material Interconnection
Side by Side PCB SolderAdhesiveWire bond
FlexSilicon
SolderAdhesiveWire bond
Stacked / Folded PCB SolderAdhesiveWire bond
Flex SolderAdhesive
Silicon SolderWire bond
Embedding PCB SolderElectroplated
Flex SolderAdhesiveElectroplated
Thin film (Wafer Level)
Electroplated
Fan Out Wafer/Panel Level
Mold compound SolderAdhesiveElectroplated
Module PCBFlex
SolderAdhesiveElectroplated
SiP Packaging Toolbox: Packaging Concept
Wafer and Panel Level Packaging
Reconstituted Wafers
TSV´s for Silicon Interposer
µ-Bumps
Wafer Thinning andHandling
Low k Polymers for RDL
Merge of Front-end and Back-end
New
Pro
cess
es
SiP Packaging Toolbox –> “new functional blocks“
Aside from the electrical domain, also multiple additional functionalities will emerge for the SiP packaging toolbox.
Example: Antenna Integration for FO
eWLBInfineon
IntegratedFO TSMC
Panel FOFhG-IZM
Source ASE
SiP Packaging Toolbox: Chiplet Integration
• More Than Moore and More Moore Integration in one SiPusing Chiplet concept
• Core technologies derived from previously mentioned tools
• Active and passive interposer concept
• Electrical and optical interconnects „in SiP“
Issues to be adressed:• KGD Issues• EDA Issues• Cost/Performance/Reliability considerations
Images from “Chiplet-based partitioning using Smart Interposer forHigh Performance Computing” by Patric Vivet, CEA Leti3D Summit, Dresden, Jan 2019
SiP Packaging Toolbox: Package Type (Module)
Apple Watch S3
Photos source: Prismark/Binghamton University
1. Applications Processor2. Memory3. Field of Inductors4. RF Modules5. Cellular Transceiver6. GPS Module7. Cellular Baseband8. Cellular Power Manager
When the SiP becomes the „main“ or the „complete“ part of the system -> SiPModules
Challenge:• Turning the value chain topside down• OSATs become EMS with increased
capabilities in Assembly (incl. non-standard componenassembly)
• May even go as far as OSAT becoming OEM?
Multifunctional InteractiveSmart Card
Photos source: Fraunhofer IZM
Future SiP Market
SIP MARKET - GLOBAL FORECAST TO 2023 by Markets
Examples of future requirements derivedfrom different application areas
Applications - Power
Switching Cell for Industrial Application Challenges:
• “Switching Cell in Package”• 2 component layers integrated: Chips and SMD• Peripherals on the module• Increasing Power Densities in Package: 200W/cm3• Lower Parasitics Requirements• Multi-Material Challenge: Si w/ III-V• Thermal Transient Management• EMC challenges• Co-design with actives and passives
Spring contact DC+
Spring contact DC-
Spring contact OutDriver contacts
DCB
Driver boosterPrimary DC link capacitor
Photos source: Fraunhofer IZM
SiP (electronic only) for autonomous driving
SiP (multi domain functionality) for efficient autonomous driving
Specifications of Modular Micro Camera Packaging of image sensors using embedding
Modular system with the option of integrating more sensors
Example: Dual Core ARM9 with350 MHzintegrated image processing-DSP (APEX),3M-Pixel CMOS sensor OmniVision, 16 MByte DDR SDRAM,32 MByte NAND Flash, Mentor RTOS system softwareUSB 2.0 device interface
Applications Motion detection (protection against theft)
Pattern detection (traffic signs)
Edge detection (character recognition)
Real-time image processing
Applications - AI
© Fraunhofer IZM
Souce: NVIDIA
Source:Fraunhofer IZM
• New package platform (FO, embedding)• Complex SystemsCost
• Technology Diversity (Sensors, antenna, IC´s, passives• Pitch, soldered and non-solderd components
Assembly
• Reliability and application specific requirements• Temperature / cooling• Performance• Pitch, dimensions, thickness
CustomerRequirements
• Application specific (incl. mixed signal, media, etc.)• Electrical, mechanical and thermal aspects• Self testing, incl. BIST
Test
• New materials (Hf materials)• Material interactions• Failure modes• Thermal mismatch
Materials
• SiP Requiring a system <-> package co-design• Different libraries in one project• Multiple domains with different scaling properties• Thermal, mechanical and electrical analysis
Co-Design
Standardization FootprintDimensionsThickness…
Challenges for Implementing SiP
Examples of challenges derivedfrom the different sections
Challenge Material: Material Selection – Embedded Die Technology
Last 10 years: all package materials changedNext 10 years: package material change will continue
Components with differences in: Size (100x100 µm² - 12x12 mm²) Thickness (40 µm – 3 mm) Material & surface finish Stiffness, fragility
Process Challenges: High Density Integration – Large Area High Accuracy – High Speed Heterogeneous Component Handling
• Adapted tools and bonding methods
s: micro-mechanics
SiP IPhone A11++
Cross section A10 Package
s: System Plus Consulting
https://de.ifixit.com/Teardown/iPhone+X+Teardown/98975?lang=enOdd shape, as connectors
fragile MEMs
variety of components
alreadyencapsulated ICs
passives
fragile ferrites
Stacked Memory Chips
Assembly Tools
Challenge Assembly: Mixed Placement for SiP
Courtesy J. Hunt, ASE
CommonPackaging Platform
expected tofacilitate
standardisationrequirements
=>FOWLP/FOPLP
Challenge Standardization: Common Package Type
Multiple fabrication technologies and fab origins„best of class“, „best of price“
Source:Fraunhofer IZM
Thank You to all the SiP TWG members for the contribution
Rolf AschenbrennerKlaus Pressel, InfineonErik Jung, Fraunhofer IZMHannes Stahr, AT+SHarrison Chang, ASEKey Chung, SPILHugo Pristauz, BESI