Reliable Data Storage using Reed Solomon Code
Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl
Spring 2004
Part A Final Presentation
Problem:Cosmic radiation in space causes bit-flips, and therefore valuable information could be lost.
Solution:All data stored will first be encoded via a Reed Solomon Encoder. A Reed Solomon Decoder will be used when data retrieval is required.
Reed Solomon Encoder
Reed Solomon Decoder
Storage Device
Hi res Hi freq.
input data
(possibly)corrupted
data
(hopefully)corrected
data
Basic Project Function
How will we implement?
RocketIO Link
“Storage”Board
Memory
“Master”Board
RS Encoder
RS Decoder
CPU resources will be used at a minimum
Satellite Computer & Logic
Satellite Data
Storage
First Semester Goals• Studying the system-on-chip design process.• Studying the EDK environment.• Studying the blocks that build our system:
– PowerPC– Reed Solomon Encoder/Decoder.– PLB IPIF and bus transaction protocol.– RocketIO
• Implementing the Reed Solomon cores as slaves on the bus (CPU still very involved in the flow).
• Sending a packet through RocketIO Reference Design
PLB
PowerPC
RSDecoder
RS Encoder
PLB2OPBBridge
OPB
UART
Hyperterminalon
DIGLABPC
IPIF
FIFO
IPIFIPIF
First Semester Goal Arch.
A Few Numbers…
• PLB Frequency is 100 MHz
• The Reed Solomon data width is 8-bit.
Thus, if we could theoretically perform an 8-bit write each clock cycle, our basic architecture would reach a throughput of 0.8 Gbps.
System Blocks
IPIF
The IPIF is (as its initials suggest) an interface between the bus and the IP.
It takes care of the transaction protocols on the bus and simplifies access to the IP. It also enables special features such as S/W Resetting, User Logic address ranges, interrupts, Bursting, DMA support and more.
IPIF – continued
Bus Transactions
Bursting enables us to transfer data with a higher throughput!
Reed Solomon cores• When creating the cores using Xilinx
CoreGen, the following parameters are needed: – k: number of symbols per data block (to be
encoded)– n: total number of output symbols (original data +
check symbols)– s: number of bits per symbol
The Reed Solomon code can detect n-k symbol errors and correct (n-k)/2.
We have chosen k=239, n=255, s=8, which are similar to G. 709 standard.
RS cores
RS Cores – Detailed
FIFO
We have used several different FIFOs in our design, all taken from Xilinx CoreGen.
We have made three FIFO types for our purposes, the “plb_in_fifo”, “plb_out_fifo” and the “plb_fifo”.
For this we have chosen a 1024x8bit FIFO.
PLB OPB
UART
Encoding data flow
• Writing to encoder is done via IPIF. When there is no write request the encoder is in bypass mode.
• Data from the encoder is directly connected to a FIFO.• The FIFO is read via IPIF to the PowerPC and sent
through UART to PC.
PowerPC
RSDecoder
RS Encoder Hyperterminal
onDIGLAB
PC
IPIF
FIFO
IPIFIPIF
PLB2OPBBridge
Decoding data flow• The data is put through IPIF to a FIFO at the decoder
inputs. • Using a block called FIFO-Helper, data is sent every
clock cycle to the decoder.• The decoder also has a FIFO at its outputs where data
is taken from via IPIF for PowerPC and sent through UART to PC.
PLB
PowerPC
RSDecoder
RS Encoder
PLB2OPBBridge OPB
UART
Hyperterminalon
DIGLABPC
IPIF
FIFO
IPIFIPIF
RocketIO
• RocketIO can transmit and receive serial data at rates ranging from 620 Mbps to 3.125 Gbps.
• At these rates, in order to assure sampling at correct times, each byte is coded into a 10 bit sequence with enough edges.
• The 10 bit scheme allows for special “K-Characters”, which are used for various tasks, including packet start and end signaling (SOP, EOP) and byte-synchronization (Comma).
DCR
RocketIO Ref. Design
PowerPC
PLB
RSDecoder
RS Encoder
PLB2OPBBridge OPB
UART
Hyperterminalon
DIGLABPC
IPIF
FIFO
IPIFIPIF
PacketProcessing
Engine
DataBRAM
RocketIOTransceiver
Mindspeed Physical Media Attachment
Xilinx Coding Sublayer
RocketIO Transceiver Diagram
loopback
loopback8B/10BEncode
FIFOTXDATA 16 bit SerializerTransmit
Buffer
TXN
TXP
8B/10BDecode
Elastic Buffer
RXDATA 16 bitDeserializerComma Detect
ReceiveBuffer
RXN
RXP
We will use one of the following:• 125 MHz x 16 bit x 10b/8b = 2.5 Gbps• 156.25 MHz x 16 bit x 10b/8b = 3.125 Gbps
RocketIO Ref. Design
The reference design has several disadvantages.
• Packets must be prepared (in other words, encoded) and stored in memory first, and only then sent.
• There is too much CPU resource waste.
PowerPCRS
EncoderPowerPC
DataBRAM
PacketProcessing
Engine
RocketIOTransceiver
Original Second Semester Goals
• Building a CPU offload unit that will be a master on the PLB, perhaps using the DMA capability of the IPIF.
• Using another development board to simulate a storage device.
• Performing fast and reliable data transfers between the two boards using the RocketIO ports.
Original Second Semester GoalSystem Diagram
PLB
Rocket I/O
SDRAMMemory
ControllerPowerPC
RSDecoder
RS Encoder
Second Development
Board(simulating
storage device)
CPU offload unit
PLB2OPBBridge
OPB
UART, etc.
OPB
Our New “Master” Board Architecture
PLBPowerPC PLB2OPBBridge
UART
Hyperterminalon
DIGLABPC
RS Encoding Unit
IPIF
Outgoing PacketDelivery Unit
OutgoingMemory
RocketIO Transceiver
RS Decoding Unit
IPIF
Incoming PacketReceiving Unit
IncomingMemory
Advantages Of This Architecture
• The CPU responsibility is only to give simple read/write orders. The rest of the flow is done in hardware.
• There is no need for the “CPU offload unit”.• The unit we will create can be treated as a black
box, and be added multiple times for multiple storage devices in a modular fashion.
• A very similar box would be put in the “storage” board.
“Storage” Board Diagram
OPBPLBPowerPC PLB2OPBBridge
UART
Hyperterminalon
DIGLABPC
IPIF
Outgoing PacketDelivery Unit
“Storage” Memory
RocketIO Transceiver
IPIF
Incoming PacketReceiving Unit
Large SDRAM
Second Semester Schedule
• Building the outgoing delivery unit and the incoming receiving unit – 6 weeks.
• Interfacing the units to PLB – 1 week.• Testing the architecture on “Master” board with
RocketIO loopback – 2 weeks.• Creating similar units for “Storage” board – 2
weeks.• Testing architecture on “Storage” board with
RocketIO loopback – 1 week.• Integration of the two boards and final
debugging – 2 weeks.
Demonstration
• Through the UART interface, we will demonstrate the following:– Encoding of 239 bytes into a 255-byte Block.– Destroying several symbols according to a
randomization seed from the user.– Decoding and correction of the original block.
Thank you