PROGRAMMABLE
INTERVAL TIMER 8254
Dr. Sikder Sunbeam Islam
EEE, IIUC
ABOUT 8254
The 8254 programmable interval timer/counter is
functionally similar to the software designed
counters and timers. It generate accurate time
delay. 8254 is the high speed version of the 8253.
Features:
3-identical 16-bit counters.
Six modes of operation.
Single +5v power supply.
24-pin DIP(Dual in-line package).
Can count either in BCD or Binary.
Fig.1 2
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APPLICATIONS
Real time clock
Event-counter
Digital one-shot
Programmable rate generator
Square wave generator
Complex waveform generator
Complex motor controller
Used to refresh DRAM memory.
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INTERNAL BLOCK DIAGRAM OF 8254
Fig.2: Internal blocks of 8254
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COUNTER SELECTION
CLK : The clock input is the timing source for each of the internal
counters.
OUT: A counter output.
GATE : The gate input controls the operation of the counter for a
mode.
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INTERNAL BLOCK DIAGRAM OF A
COUNTER
Fig.3: Internal blocks of counter
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INTERNAL BLOCK DIAGRAM OF A COUNTER (CONTINUES.)
The Counters are fully independent. Each Counter may operate in a different Mode.
The Control Word Register is shown in the figure; it is not part of the Counter itself, but its contents determine how the Counter operates.
The status register, shown in Fig.3, when latched, contains the current contents of the Control Word Register and status of the output.
The actual counter is labeled CE (for „„Counting Element‟‟). It is a 16-bit presettable synchronous down counter.
OL(M) and OL(L) are two 8-bit latches. OL stands for „„Output Latch‟‟; the subscripts M and L stand for „„Most significant byte‟‟ and „„Least significant byte‟. These latches normally „„follow‟‟ CE.
There are two 8-bit registers called CR(M) and CR(L), CR for „„Count Register‟‟. Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. 7
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CONTROL WORD FORMAT
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8254 OPERATION
8254 Write operation
The programming procedure for the 8254 is very flexible. Only two conversion need to be remember.
For each Counter, write the Control Word in the control register before the initial count is written.
Load the low-order byte of a count in the counter register (CR).
Load the higher-order byte of a count in the counter register (CR).
The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte).
With a clock and an appropriate gate signal to one of the counters, the above steps should start the counter and provide appropriate output according to the control word. 9
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8254 READ OPERATIONS
There are three possible methods for reading the
counters:
A simple read operation (read counter after
stopping)
The Counter Latch Command (reading on the
fly), and
The Read-Back Command (read multiple counter
at a time).
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A SIMPLE READ OPERATION
This operation read the counter after stopping.
Counting is stopped by controlling the gate input or the
cloak input of the selected counter.
Then two I/O read operation are performed by the MPU:
1. The first I/O operation reads the low order byte.
2. The second I/O operation reads high order byte.
Counter Latch Command
This allows reading the contents of the Counters “on the fly''
without affecting counting in progress.
The selected Counter's output latch (OL) latches the count at
the time the Counter Latch Command is received.
This count is held in the latch until it is read by the CPU (or
until the Counter is reprogrammed). The count is then
unlatched automatically and the OL returns to “following''
the counting element (CE). 11
[Latches can be memory devices, and can store one bit of data for as long as the device is powered.]
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COUNTER LATCH COMMAND (CONTINUED)
Fig: Counter Latching Command Format
Example:
;Latching Counter-1
MOV AL, 01000000B ; count
latched for counter 1.
OUT CNT_REG, AL;
;Reading Counter-1
MOV DX, COUNTR1
IN AL, DX
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If the counter is latched, and then latched again before the count is read,
the second Counter Latch Command is ignored.
[“;” is used to notify statements
in program]
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READ-BACK COMMAND
This command is used to read several counters at a time. It
eliminates the need of writing separate counter-latch commands
for different counters.
It allows the user to check the count value, programmed Mode,
and current states of the OUT pin and Null Count flag of the
selected counter/ counters.
The command can be written into the Control Word Register and
has the format shown in Figure.
Figure: Read-back command format
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READ-BACK COMMAND (CONTINUED)
By setting the COUNT bit D5 =0, multiple counter output
latches (OL) can be latched (counted).
Each counter's latched count is held in the OL until it is read
(or reprogrammed). The counter is automatically unlatched
when it is read.
By setting STATUS bit D4 = 0; status information of selected
counter(s) can be latched. The counter status format is shown
in Figure below.
Bits D5 through D0 shows the
counter's programmed Mode.
OUTPUT bit D7 contains the
current state of the OUT pin.
This allows the user to
monitor the counter's output
via software. Figure: Counter status format 14
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Example:
;Read-back Command for Count 0
MOV AL, 11000010B ; count latched for Count 0
OUT CNTRL_REG, AL;
;Reading the latched status for count 0
MOV DX, COUNTR0
IN AL, DX ; Reading Status
MOV AH, AL
;Reading the latched count for Counter 0
IN AL, DX ; Reading LSB of Counter 0
MOV BL, AL
IN AL, DX ; Reading MSB of Counter 0
MOV BH, AL
READ-BACK COMMAND (CONTINUED)
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If both count and status of a counter are latched, the first read operation of
that counter will return latched status. The next one or two reads return
latched count.
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MODES OF OPERATION
Mode 0: Interrupt on terminal count.
Mode 1: Hardware Retriggerable One-Shot.
Mode 2: Rate Generator.
Mode 3: Square Wave Mode.
Mode 4: Software Triggered Mode.
Mode 5: Hardware Triggered Mode.
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MODE 0: INTERRUPT ON TERMINAL COUNT OR
EVENT COUNTER
Figure: Suppose count 7 is loaded. 17
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MODE 0: INTERRUPT ON TERMINAL COUNT
OR EVENT COUNTER(CONTINUES).
Once the count is loaded in the register, the
counter is decremented. When the count reaches
to zero, the OUT goes High. Count starts from N.
The OUT remains High until the new count or
command is loaded.
The Gate (G) input must be a Logic 1 to allow the
counter to count.
If G becomes Logic 0 in the middle of the count,
the counter will remain stop until G again
becomes a Logic 1.
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MODE 1: HARDWARE RETRIGGER ABLE ONE-SHOT:
MONOSTABLE MULTIVIBRATOR.
OUT is initially High.
When Gate is triggered, OUT goes to Low.
On completion of count, OUT goes to High again.
If the Gate input occurs within the duration of
counting, the counter is again reloaded with
count and start counting from the beginning.
Figure: Suppose count 5 is loaded.
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MODE 2: RATE GENERATOR:
When count N is loaded, the OUT remains High(1) for
N-1 clock period and Low (0) for 1 clock period.
The count N is reloaded automatically and the pulse is
generated continuously.
Count N=1, invalid.
When the Gate is logic zero, there will be no counting.
When the Gate is logic 1, then normal counting is
started.
Figure: Suppose count 5 is loaded.
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MODE-3 :SQUARE WAVE GENERATOR
Generate continuous Square wave at the out put.
Gate should be maintained at logic 1 always.
When count N loaded, if N is EVEN then OUT
will be High for N/2 clock cycles and Low for N/2
clock cycles.
If N is ODD, output remains HIGH for (N+1) /2
and low for (N-1) /2.
Figure: Suppose count 6 is loaded.
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MODE 4: SOFTWARE TRIGGERED STROBE
After mode is set, the output goes high.
If count of N is loaded, then OUT will be high for N clock cycles and low for one clock cycle at the end.
The cycle does not begin until the counter is loaded again.
Gate input must be maintained High during operation.
Figure: Suppose count 8 is loaded.
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MODE 5: HARDWARE TRIGGERED STROBE
(RETRIGGERABLE)
Operation is similar to Mode-4, except that it is started
by a trigger pulse on the G pin instead of by software.
When the GATE pulse is triggered from low to high the
count begins. At the end of the count OUT goes Low for
one clock period.
Figure: Suppose count 5 is loaded.
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PROBLEM 1
a. Identify the port address of the control register and counter 2 in
Figure-1.
b. Write a subroutine to initialize counter 2 in mode 0 with a count of
50,000.The subroutine should also include reading counts on the fly;
when count reaches zero, it should return to the main program.
c. Write a main program to display seconds by calling the subroutine as
many times as necessary.
Figure-1
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Problem 1 (Continued)
Solution (a):
According to the Figure-1,
A15 A14 A13 A12……………….A3 A2 A1 A0 Address Counter/Register
1 0 0 ……………… 0 0 0 8000H Counter0
1 0 0 ……………… 0 0 1 8001H Counter1
1 0 0 ……………… 0 1 0 8002H Counter2
1 0 0 ……………… 0 1 1 8003H Control Register
Address of Counter 2 = 8002H
Address of Control Register = 8003H
Solution (b):
We have to initialize counter 2 in Mode0.
Count=(50,000)10 = C350H
Control Word to initialize counter 2 in mode0 and to load 16-bit count:
1 0 1 1 0 0 0 0
Counter 2 Load 16 bit Count Mode0 Binary count
So, Control Word = 10 11 000 0=B0 H
1 0 0 0 0 0 0 0
Counter 2 Load 16 bit Count Don't Care
So, Control Word = 10 00 000 0=80H (Counter Latch Command)
To read count 2 on the fly counter latch command is:
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Solution (b).
Subroutine:
COUNTER PROC NEAR
CNT2 EQU 8002H
CNTR EQU 8003H
MOV AL, B0H
OUT CNTR, AL
MOV AL, 50H
OUT CNTR2, AL
MOV AL, C3H
OUT CNTR2, AL
READ: MOV AL, 80H
OUT CNTR, AL
IN AL, CNT2
MOV DL, AL
IN AL, CNT2
OR AL, DL
JNZ READ
RET
COUNTER ENDP
Problem 1 (Continued)
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Solution (c)
Clock frequency, fc = 2 MHz
Time period of each clock cycle,
𝑡𝑐 =1/(2 ×106)= 5 ×10−7 𝑠𝑒𝑐 Every time subroutine is called then, 50,000 × 5 ×10−7 = 25 ݉𝑠 is counted.
To count 1 sec subroutine needed to be called, 25݉𝑠= 40 𝑡𝑖݉𝑒𝑠 = 28𝐻 𝑡𝑖݉e𝑠
Main Program:
Assuming segment registers are already initialized. MOV BL, 00H
SECOND: MOV CL, 28H
WAIT: CALL COUNTER
DEC CL
JNZ WAIT
MOV AL, BL
ADD AL, 01
DAA
OUT 25H, AL ; assuming 8 bit port 25H
MOV BL, AL
JMP SECOND
HLT
Problem 1 (Continued)
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Problem 2:
Write instructions to generate a pulse in every 50 us later from counter 0.
Consider the figure of problem1.
Solution :
To generate a pulse in every 50 us later, we should initialize counter0 in
mode 2. Gate0 should be high.
Count: Clock frequency, fc = 2 MHz
Needed count, 𝑁 =𝑢݈𝑠𝑒 𝑡𝑖݉𝑒(𝑡𝑝)
𝑐݈𝑐݇ 𝑒ݎ𝑖݀(𝑡𝑐) =
50 ×10−6
5 ×10−7 = 100 = 64𝐻
Control Word:
Instructions:
CNT0 EQU 8000H
CNTR EQU 8003H
MOV AL, 14H
OUT CNTR, AL
MOV AL, 64H
OUT CNT0, AL 28
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Problem 3:
Write instructions to generate a 1 KHz square wave from Counter1. Assume
the gate of Counter1 is tied to +5V through a 10K resistor. Explain the
significance of connecting the gate to +5V. (use Figure of problem 1)
Control Word:
Solution:
To generate a square wave from Counter1, it should be initialize in Mode 3.
As, Clock time period=5 ×10−7s and time period of Square Wave=(1/1K)=10−3s
Needed count = 𝑁 =𝑢݈𝑠𝑒 𝑡𝑖݉𝑒(𝑡𝑝)
𝑐݈𝑐݇ 𝑒ݎ𝑖݀(𝑡𝑐)=
10−3
5 ×10−7=2000 = 07𝐷0𝐻
Instructions:
CNT1 EQU 8001H
CNTR EQU 8003H
MOV AL, 76H
OUT CNTR, AL
MOV AL, D0H
OUT CNT1, AL
MOV AL, 07H
OUT CNT1, AL
Gate should be maintained at logic 1 (+5V) always
as GATE =1 enables counting and GATE =0
disables counting. 29
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Problem 4:
Write a subroutine to generate an interrupt every 1sec. Consider the figure of
problem1.
Solution
To obtain a pulse every 1 sec, the count should be 2×106, which is too large
for
one 16-bit counter. We can divide this counter as follows:
Counter 1 [Clock pulse=2 MHz]--- Mode 2 ----- Count 50,000 (C350H)
Counter 2 [Clock pulse=Out1 (output of counter 1)]---- Mode 2 ---- Count 40 (28H)
So, finally we get 50,000 × 40 = 2×106 count and from OUT2 we get the
desired output.
0 1 1 1 0 1 0 0 74H
Binery count CW
Binery count CW
1 0 0 1 0 1 0 0 94H
Counter 2 LSB Only Mode2
Counter 1 Load 16 bit Count Mode2
Control word:
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Subroutine:
INTRP PROC NEAR
CNT1 EQU 8001 H
CNT2 EQU 8002H
CNTR EQU 8003H
MOV AL, 74H
OUT CNTR, AL
MOV AL, 94H
OUT CNTR, AL
MOV AL, 50H
OUT CNT1, AL
MOV AL, C3H
OUT CNT1, AL
MOV AL, 28H
OUT CNT2, AL
RET
INTRP ENDP
Problem 4:
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REFERENCE
Microprocessor and Interfacing Programming
and Hardware; Douglas V Hall, 2nd Edition.
Microprocessors and Microcomputer-Based
System Design; Mohammed Rafiquzzaman,
revised edition.
Microprocessor & Interfacing Lecture Materials;
Mohammed Abdul Kader, EEE, IIUC.
Mohammed Amer Arafah, King Saud University;
https://fac.ksu.edu.sa/sites/default/files/part8_825
4.pdf
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