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Subject-MDS
Topic-PACKAGE
Presented By
Kshama Nikhade
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Package
It Provides a Convenient mechanismto Store and Share declarations that are
common across many design units
It is used to hold VHDL code i.e of
general use.
Package can be Included in manyother Source Files, which can then use
Definitions provided In Package
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PACKAGE
PACKAGE
DECLARATION
PACKAGE BODY
(OPTIONAL)
Stores Set Of Common
Declarations that can be
Shared by many Design Units
Library and use clause are
used to access the items
declared in package
Declaration
Package Body is always
associated with apackage
declaration
Stores definitions of
Functions & Procedures
Contains Behaviour of
Subprograms or functions
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Package Declaration
package package_name is
[package declarations]
[type declarations]
[component declarations]
end [package] [package_name]
component declaration
Variable declaration
subprogram
Declarations
type declarations
subtype declaration
constant declaration signal declaration
attribute Declaration
use clause
Syntax
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Package Declaration Example
package MY_PACKAGE is
type SUMMER is (MAY, JUNE, JULY, AUG, SEP);
component D_FF
port ( D, Clk : in bit;Q, Qbar : out bit );
end component ;
Constant P_Delay :Time := 125ns;
Function int2Bit_VEC (int_Value:integer)
return bit_vector ;
end MY_PACKAGE ;
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Importing Declarations into Design
Units
1 . Import All Declarations
library DESIGN_LIB;
use DESIGN_LIB.MY_PACKAGE.allentity ff is
{
}
end ff;
architecture df of ff is
{
}
end df;
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2.Selectively Import Declaration
A. USING USE CLAUSE
library DESIGN_LIB;
use DESIGN_LIB.MY_PACKAGE.D_FF
use DESIGN_LIB.MY_PACKAGE.P_Delay
architecture df of ff is
{
}
end df;
B. Using Selected Names
library DESIGN_LIB;
Package ANOTHER_PACKAGE is
function SEASON(MONTH:DESIGN_LIB.
MY_PACKAGE.SUMMER)
return integer;
end ANOTHER_PACKAGE;
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PACKAGE BODY
Syntax :
package body package_name is
[package body item declarations]
[subprogram bodies]
[complete constant declarations]
[type and subtype declaration][use clause]
end [package body] [package_name]
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Example Of Package Body
Package body MY_PACKAGE is
function int2Bit_VEC (int_Value:integer)
return bit_vector isBegin
--behaviour of function described here
end int2Bit_Vector ;end MY_PACKAGE
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4:1
MUX
4:1
MUX
4:1
MUX
4:1
MUX
4:1
MUX
S1 S0W0
W1
W2W3
m(0)
m(1)
m(3)
m(2)
f
W4
W7
W6
W5
W9
W8
W15
W10
W11
W12
W14W13
S3 S2
Design of 16: 1 mux using 4:1mux
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Package Declaration of 4:1mux
Library ieee;Use ieee.std_logic_1164.all;
Package mux4to1
Component mux4to1
Port(w0,w1,w2,w3 : in std_logic;
s : in std_logic_vector(1 downto 0);
f : out std_logic);
End component;
End mux4to1;
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Design of 16: 1 mux using 4:1mux
Library ieee;
Use ieee.std_logic_1164.all;
Library work;
Use work.Mux4to1.all
Entity Mux16to1 is
Port(w : in std_logic_vector(0 to 15)s : in std_logic_vector(3 downto 0);
f : out std_logic);
End Mux16to1;
VHDL CODE FOR 16:1 MUX
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Architecture struct of Mux16to1 is
Signal m: std_logic_vector(0 to 3);
Begin
Mux1: Mux4to1 portmap
(w(0),w(1),w(2),w(3),s(1 downto 0),m(0));
Mux2: Mux4to1 portmap
(w(4),w(5),w(6),w(7),s(1 downto 0),m(1));
Mux3: Mux4to1 portmap
(w(8),w(9),w(10),w(11),s(1 downto 0),m(2));
Mux4: Mux4to1 portmap(w(12),w(13),w(14),w(15),s(1 downto 0),m(3));
Mux5: Mux4to1 portmap
(m(0),m(1),m(2),m(3),s(3 downto 2),f));
End struct ;
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University Questions1. Discuss the usage of package body and package
declaration with their syntax.(S-11 for 6M)
2. Explain the Concept of package and package body
(W-04 for 4M)
3. What is Package Body and Package Header .Illustrate
With Example. (S-06 for 5M)
4. How are packages used to encapsulate information
that is to be shared among multiple design units?
(W-06 For 4M)
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