© 2014 GOEPEL electronics IEEE Std 1149.1 updates
IEEE Std 1149.1-2013
1
This is an IEEE 1149.1 working group member’s attempt in presenting changes and new features defined in IEEE 1149.1-2013.
Slides not reviewed or approved by the working group.
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
2
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Changes to existing concepts
Previously depreciated BC_6 no longer supported
Boundary-scan register can have excludable segments
All (except TAP) pins may have additional observe-only cells
Additional BSDL constructs and new options for existing constructs
Defined interface for design-specific TDR (recommended)
3
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
4
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New Concepts
Test-Mode Persistence (TMP) Controller (optional)
Electronic Chip Identification (ECIDCODE) (optional)
Initialization (optional)
IC Reset (optional)
(excludable) Register segments (optional)
Power domain control (optional)
Register fields, mnemonics, and assembly (optional)
Procedural Description Language (PDL) (optional)
5
IEEE P1149.1/D2012.e21, June 4, 2012
36 Copyright © 2012 IEEE. All rights reserved.
This is an unapproved IEEE Standards Draft, subject to change.
6.2 Test-Mode Persistence (TMP) Controller 1630
The optional test-mode persistence (TMP) controller provides a means to place and hold the device in test mode. 1631 For the purpose of this standard, test mode means that the device pins are controlled from the boundary-scan 1632 register, and the system logic should be held in a safe and cool state while performing tests. This may be used to 1633 prevent a device from attempting to return to functional operation, with unknown and possibly destructive 1634 effects, when a non test mode instruction such as BYPASS or PRELOAD is inserted between test mode 1635 instructions such as EXTEST or RUNBIST. During board or system test, it provides control over which chips are 1636 in test mode, and which are not, and may keep a chip, board, or system safe until the circuit under test is either 1637 powered down or a proper reset sequence can be performed to safely bring the chip, board, or system out of test 1638 and ready for other operations. 1639
The resources required to implement the optional TMP controller include a simple state machine (see Figure 1640 6-9), the two instructions CLAMP_HOLD and CLAMP_RELEASE (See Clause 8.20), and a single bit bypass-1641 escape register (See Clause 16). 1642
6.2.1 TMP Controller state diagram 1643
6.2.1.1. Specifications 1644
Rules 1645
a) The state diagram for the Test-Mode Persistence (TMP) controller shall be as shown in Figure 6-9. 1646
1647 Figure 6-9—Persistence Controller State Diagram 1648
b) The TMP controller shall change state only in response to the following events: 1649
1. A rising edge of TCK when either the CLAMP_HOLD or CLAMP_RELEASE instructions are active 1650 (see Clause 8.20); or 1651
2. A transition to logic 0 at the TRST* input (if provided, see Figure 6-8); or 1652
3. On-chip reset at power-up (i.e. POR, if provided, see Figure 6-8); or 1653
4. A rising edge of TCK when the single-bit TMP control register is asserted (it contains a ‘1’), and the 1654 BYPASS instruction is in the Instruction Register and the TAP controller is in the Update-IR TAP 1655 controller state. 1656
NOTES: 1657
1. Either the IDCODE instruction or the BYPASS instruction is forced into the Instruction register by entering the Test-Logic-1658 Reset TAP controller state according to rules 7.2.1e and 7.2.1f in this Standard. This is not a condition for resetting the TMP 1659 controller state since the TAP state does not pass through Update-IR. 1660
Persistence-Off Persistence-On
CLAMP_HOLD Instruction
CLAMP_RELEASE Instruction
“BYPASS-Escape”TAP-POR*
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Test-Mode Persistence (TMP) Controller
IEEE 1149.1-2013 Clauses 6.2, 8.20, and 16
New, optional, synchronous finite state machine
Assert test mode regardless of active instruction
Instructions CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS
Two-bit TMP Status register
6
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Electronic Chip Identification (ECID)
Optional
Individual chip’s ECID value is unique
“Serial number” for the component
Permits tracking the history of the component through its lifetime
ECIDCODE instruction, ECID register
Extraction defined in PDL
7
IEEE 1149.1-2013 Clauses 8.15 and 13
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Initialization
Focusing on devices with programmable I/O
Optional method to initialize component before test
INIT_SETUP and INIT_SETUP_CLAMP, and/or INIT_RUN instructions
Initialization process to be defined in PDL
Initialized system state is retained as long as the device stays in test mode (or “persistence” is on)
8
IEEE 1149.1-2013 Clauses 8.17, 8.18, 8.19, 14, and 15
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
IC Reset
Provide test control of system reset and related inputs through TAP
Does not control reset signals to the test logic
IC_RESET instruction and Reset Selection register
9
IEEE 1149.1-2013 Clauses 8.21 and 17
IEEE P1149.1/D2012.e27, September 10, 2012
167 Copyright © 2012 IEEE. All rights reserved.
This is an unapproved IEEE Standards Draft, subject to change.
17. The reset selection register 5813
This register and its associated IC_RESET instruction (see sub-clause 8.21) allow control of system reset functions 5814 through the TAP, including blocking undesired resets to the system logic during testing. 5815
17.1 Design and operation of the reset selection Register 5816
5817 Figure 17-1— Reset selection register overview 5818
The reset selection register may be described, as shown above in Figure 17-1, in terms of the capture/shift register 5819 (the optional capture capability is not shown here), the update register, and reset select logic. A more detailed 5820 example is shown in Figure 17-2. The reset selection register is also divided into fields and bits within the fields as 5821 described in the rules. The labeling in Figure 17-1 illustrates the terminology of the rules. Figure 6-8 shows the 5822 generation of the TAP-POR* signal and Figure 6-5 the generation of the Reset* register. 5823
17.1.1 Specifications 5824
Rules 5825
a) The reset selection register shall consist of at least a single cell to control its own reset plus one or more pairs 5826 (two-bits) of cells and associated reset select logic, one such pair for each reset signal to the system logic to 5827 be controlled, 5828
C U
C U
C U
C U
C U
Domain 1
Domain N
reset-enable 1
reset-control 1
reset-enable N
reset-control N
reset-hold
TDI
TDO
TAP-POR*
Reset*(from TAP)
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register segmentsRegisters may be segmented (other than Bypass, ID, and TMP status register) Register segment length must fixed (1 bit or longer)
Segments can be included / excluded
Segments must not overlap and must not be contained within another segment*
Excludable segments are initially excluded
Segment-select cell controls inclusion of segment
Segments may be in different power domains
Mutually exclusive segments in “broadcast” config
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IEEE 1149.1-2013 Clauses 9.2, 9.4, B.8.19, B.8.20, and B.8.21
* = this restriction is true for registers defined in the standard
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Power domain control
IEEE P1149.1/D2012.e21, June 4, 2012
98 Copyright © 2012 IEEE. All rights reserved.
This is an unapproved IEEE Standards Draft, subject to change.
If the test data register segment requires some action to be taken to make the segment scannable, then a domain-6026 control cell must be provided. It is shown immediately prior to the segment-selector cell in the TDR in Figure 6027 9-15, but could be placed in any non-excludable portion of this or another TDR. 6028
6029 Figure 9-15—Scan control of enabling excludable register segments. 6030
If the segment-selector cell captures a ‘0’ logic value, indicating that the segment is not ready for scanning, then 6031 the domain-control cell must be enabled by scanning a ‘1’ into its parallel output, and the segment-selector 6032 capture value re-checked to verify that the segment is ready. For instance, if a segment is in a power domain 6033 that can be powered-down, and the power domain is controlled on chip, then a domain-control cell (named a 6034 DomCtrl cell in Annex A) must be provided to turn on the power to the domain containing the segment, when 6035 required. If multiple TDRs have segments in the same power domain, then there could be multiple domain-6036 control cells in different TDRs that can turn the domain power on. The “ready to scan” signal from the domain-6037 controller could be captured in multiple segment-selector cells to verify that the power is on and that the various 6038 segments are ready to be included for scan. 6039
The parallel output of the segment-selector cell is delayed one TCK cycle from the latched parallel output. This 6040 is to prevent the potential race between update actions and switching the segment between included and 6041 excluded by allowing time for the update actions to complete before the segment changes state. 6042
Figure 9-16 shows an example segment-selector cell meeting all of the rules of this clause. 6043
6044 Figure 9-16—Example segment-selector cell with ungated clocks 6045
NOTE—The reset signal in the figure is shown as the CH_Reset* signal, which implies the presence of the TMP controller. 6046 The rules permit any of the test reset signals (TAP_POR*, TRST*, Reset* (Test-Logic-Reset TAP controller state), or 6047 CH_Reset*) to be used here, but one of them must be used. 6048
Excludable SegmentC
U 0
1
PI
PO
SI SO
“Ready to scan”
From TDITo TDO
Segment-selector
CellCapture_<TDR>
Shift_<TDR>
Update_<TDR>
C
UPO
SI SO
Domain-control
Cell
0
10
1
0
1
Q
QSET
CLR
DQ
QSET
CLR
D
PO
From last bit
TCK
CH_Reset*
PITo next bit
Segment-selector Cell
tdr_cap
tdr_updShiftTdrBit
CaptureTdrBit
UpdateTdrBit
SI SO
Shift_<TDR>
Capture_<TDR>
Update_<TDR>Q
QSET
CLR
Ddelay
To switch
“Ready to scan”
to domain controller (1 = enable domain for test)
(from domain controller; 1 = ready)
SegMux
Power domains may be powered down
Segments in un-powered domains must be excluded
Domain-control cell for on-chip control through TAP
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register fields, mnemonics, and assembly
Registers can be segmented, requiring “assembly” defined in BSDL
Registers / segments can be described with fields
Patterns / values to be loaded into fields may be defined with mnemonics
12
IEEE 1149.1-2013 Clauses B.8.18, B.8.19, B.8.20, and B.8.21
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New Instructions
CLAMP_HOLD
CLAMP_RELEASE
TMP_STATUS
ECIDCODE
INIT_SETUP
INIT_SETUP_CLAMP
INIT_RUN
IC_RESET (all optional)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
CLAMP_HOLD
Test-mode instruction
Required if TMP controller is provided
Selects TMP Status register
Sets TMP controller to Persistence-On
Enforces CLAMP-behavior
Chip designer selects opcode (anything but all-0)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
CLAMP_RELEASE
Test-mode instruction
Required if TMP controller is provided
Selects TMP Status register
Sets TMP controller to Persistence-Off
Enforces CLAMP-behavior
Chip designer selects opcode (anything but all-0)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
TMP_STATUS
Normal-mode instruction
Required if TMP controller is provided
Selects TMP Status register
Reports status of TMP controller and value of Bypass-Escape bit
Chip designer selects opcode
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
ECIDCODE
Normal-mode instruction
Used to retrieve vendor-defined public electronic chip identification code (ECID register)
all ‘1’ or all ‘0’ in ECID register indicates failure to retrieve ECID value
Chip designer selects opcode
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
INIT_SETUP
To supply parameters required for component initialization, through Init Data register
Such information is component and board (instance) dependent
Not a test-mode instruction
If provided, must be run before any test-mode instructions
Chip designer selects opcode
19
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
INIT_SETUP_CLAMP
Required whenever the INIT_SETUP is provided
Enforces CLAMP-behavior (test mode instruction)
Would be run in place of INIT_SETUP
Selects Init Data register
Chip designer selects opcode
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
INIT_RUN
Test-mode instruction
Selects Init Status register
Executes sequential initialization process
Completion of initialization determined based on:
time delay (defined as clock cycles or actual time), or
polling status
Chip designer selects opcode
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
IC_RESET
Normal-mode instruction
Selects Reset Selection register
Control of “system reset” functions through the TAP
No affect on test logic
Does not change TMP controller state
Chip designer selects opcode (should avoid all-0)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
23
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New Data Registers
TMP Status Register
Electronic Chip ID (ECID) Register
Init Data Register
Init Status Register
Reset Selection Register (all optional)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
TMP Status Register
Required if TMP Controller is implemented
Selected by CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS
Two-bit register
Bit 0: Bypass-Escape bit (1 for transition to Persistence-Off)
Bit 1: TMP-status bit (reports status of TMP Controller)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
TMP Status Register IEEE P1149.1/D2012.e21, June 4, 2012
157 Copyright © 2012 IEEE. All rights reserved.
This is an unapproved IEEE Standards Draft, subject to change.
Figure 16-1 shows a possible implementation of the TMP control register that meets the requirements of this 5710 clause. The connection of the”TMP_state” input signal and the “Bypass_Escape” output signal are to Figure 5711 6-10. Figure 6-8 shows the generation of the TAP_POR* signal from the TRST* or on-component power-up 5712 generation circuit. 5713
5714 Figure 16-1—Example TMP control register (non-gated clocks)5715
Q
QSET
CLR
D TMPCtrl_tdo
Shift_TMPCtrl
TDI
TCK
0
1
Bypass_escape
TAP-POR*
Q
QSET
CLR
D
TMP_Status bit0
10
1Capture_TMPCtrl
Bypass_escape bit
TMP_state
Deleted: shows the use of the “Bypass_Escape” 5716 output signal5717
Deleted: 5718
Q
QSET
CLR
D ByEsc_tdo
Shift_ByEsc
TDI
TCK
0
1
Bypass_Escape
TAP-POR*
Formatted: Font: Bold
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Electronic Chip ID (ECID) Register
Selected by ECIDCODE instruction
User-(designer-)defined length
Value is unique to each chip of a specific type
All-1 and all-0 indicate error during retrieval
Details of retrieval process not defined in standard (extraction sequence described in PDL)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Init Data Register
Provides parameters for initializing programmable I/O and other circuits requiring initialization
Selected by INIT_SETUP
Length depends on chip design
Value depends on component instance and board design
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Init Status Register
Observes status of the initialization process
Selected by INIT_RUN
Two or more bits long:
Bit 0: busy (1) or done (0)
Bit 1: successful/pass (1) or unsuccessful/fail (0)
‣ (additional bits may capture further status / failure details)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Reset Selection Register
Selects one or more possible functional reset operations to be performed
Selected by IC_RESET
Length: 1+(N*2) bits, with N≥1
LSB = reset-hold bit (0 allows reset control w/ Reset-Select)
N 2-bit pairs, one for each system logic reset signal to be controlled:
MSB (closer to TDI): reset-control bit (0 asserts reset signal when enabled)
LSB (closer to TDO): reset-enable bit (0 enables reset-control bit for use)
Documented with REGISTER_FIELDS, etc.
30
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
31
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New BSDL Constructs
New port types for additional information
Power Port Association
Register Fields
Register Mnemonics
Register Assembly
Register Association
Boundary Scan Register segments
System Clock description
32
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New port types
3.3V DC-DC converter
2.5V DC-DC converter
IC1
IC2BIDIR
BIDIRBIDIRBIDIR
VREF_IN
VREF_OUT
INPUT
INPUT
POWER_0
POWER_POS
LINKAGE_IN
LINKAGE_INLINKAGE_INLINKAGE_IN
ABCD
in
out
buffer
inout
LINKAGE
LINKAGE_INOUT, LINKAGE_BUFFER, LINKAGE_OUT, LINKAGE_IN, LINKAGE_MECHANICAL, POWER_0, POWER_POS, POWER_NEG, VREF_IN, VREF_OUT
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Pin descriptions in pin map
constant SM:PIN_MAP_STRING:= "CLK:9, Q:(open,open,open,open,16,17,18,19), " & "D:(open,open,open,open,2,1,26,25), " & "GND1:15, VCC1:8, GND2:open, VCC2:open, OC_NEG:7, " & "TDO:20, TMS:21, TCK:23, TDI:24";
Optional new pin descriptions for use in pin map
OPEN, TIE0, or TIE1 for non-connected package pins
TIE0 / TIE1 only allowed for pin types IN, LINKAGE_IN, POWER_0, POWER_POS, or VREF_IN
34
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
ASSEMBLED_BOUNDARY_LENGTH
Attribute ASSEMBLED_BOUNDARY_LENGTH of myIC : entity is (40,46);
Boundary-scan register may now be segmented
REGISTER_ASSEMBLY would be used to define the construction of the full boundary-scan register
ASSEMBLED_BOUNDARY_LENGTH specifies
reset length (all excludable segments excluded), and
maximum length (all excludable segments included)
35
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
BOUNDARY_SEGMENT
IEEE P1149.1/D2012.e21, June 4, 2012
234 Copyright © 2012 IEEE. All rights reserved.
This is an unapproved IEEE Standards Draft, subject to change.
16260 Figure B.7—A cell on an input which pulls to a logic 1 16261
Cell 0 in the example BSDL boundary-scan register description below could describe an input cell similar to Figure 16262 B.7. Cells 1, 2, and 3 all are associated with a single bi-directional port called MyBidi. Cell 1 in the example 16263 inherits its undriven behavior (PULL0, in this case) from the OUTPUT3 cell, cell 2, driving the same port . 16264 16265 --num cell port/* function safe [input/ccell disval rslt] 16266 " 0 (BC_1, MyInput, input, X, PULL1), "& 16267 " 1 (BC_1, MyBidi, input, X, PULL0), "& 16268 " 2 (BC_1, MyBidi, output3, 0, 3, 0, PULL0), "& 16269 " 3 (BC_1, *, control, 0), "& 16270 16271
The <input spec> provides valuable information to the ATPG process and the board test engineer. Figure B.8 16272 illustrates some of the test coverage improvements achieved by the use of <input spec> when the IC is on a PCB. 16273 The function of each pin is shown with the <input spec>, where appropriate, in parenthesis. 16274
The upper left input is tied to 2.5V power through an external pull-up resistor. Without an <input spec> of OPEN0, 16275 the presence of an open on this pin cannot be determined. When the input pin is defined by the IC vendor as 16276 OPEN0, an ATPG tool can predict a different capture value when the pin is open than when it is properly 16277 connected. 16278
16279
16280 Figure B.8— Illustration of use of <input spec> for an IC 16281
The other five inputs on the left side are connected to a passive connector by nets A through E. Without an <input 16282 spec> on these pins, the test engineer is forced to populate or drive the connector in order to prevent un-driven 16283
01
G11DC1
1DC1
01
G1
Mode
UpdateBSRClockBSR
ShiftDR To next cell
From prior cell
System Input
Pin
To System Logic
Receiver
IC1
INPUT (open0)
INPUT (open0)
POWER_POS
ABCDEC
ONNECTOR
IHGF
CONNECTOR
INPUT (open1)INPUT (open1)INPUT (open1)INPUT (open1)INPUT (open1)
CONTROL
(pull0) BIDIR
(pull0) BIDIR(pull0) BIDIR
OUTPUT2
Obstacle
2.5V DC
Defines always-on and/or excludable segments of the boundary-scan register
REGISTER_ASSEMBLY is used to combine segments into the full boundary-scan register
Also new for the boundary-scan register description: new input-spec elements:
OPEN0, OPEN1, OPENX, EXTERN0, EXTERN1
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
SYSCLOCK_REQUIREMENTS
attribute SYSCLOCK_REQUIREMENTS of myIC is “(myCLK, 10, 20, RUNBIST)“;
Describe the use of system clocks for various instructions (for use in PDL)
Defines the required minimum and maximum frequency
RUNBIST, INTEST, INIT_SETUP, INIT_SETUP_CLAMP, INIT_RUN, ECIDCODE, IC_RESET, or design specific
Pin type: in, inout, LINKAGE_IN, or LINKAGE_INOUT
37
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register Mnemonics
Provide meaningful text names / descriptions for values to be loaded into a TDR / part of a TDR
Allowed in BSDL and/or package files
38
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_MNEMONICS
attribute REGISTER_MNEMONICS of INIT_Example : entity is "SerDes_Protocol ( "& " off (0b000) <Powered down>, "& " SATA (0b010) <Serial Advanced Technology Attachment>, "& " SRIO (0b011) <Serial RapidIO>, "& " XAUI (0b101) <10 Gbps Attachment Unit Interface>, "& " Resvd1 (0b100) <Reserved for future use>, "& " Resvd2 (0b11X) <Undefined behavior - Do Not Use> )";
Mnemonic group
Mnemonic list
Mnemonic identifier (name)
Mnemonic value (pattern)
Information tag
39
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register Fields
Defining possibly hierarchical construction of a TDR
Allowed in BSDL and/or package files
Identifying fields within a TDR and characteristics such as:
the type of TDR cell used in each field,
how the fields are reset and to what value, and
what values should be written / expected from the fields
Register Fields may be addressed by PDL
40
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_FIELDS
attribute REGISTER_FIELDS of MEMD_example : package is "MBist [6] ( "& "(Algorithm [3] IS (5 DOWNTO 3 )), "& "(Command [1] IS (2) ), "& "(Status [2] IS (1 DOWNTO 0) ) "& " )";
Defines and names fields within a register / segment
Total length of register / segment is stated explicitly
Support for hierarchy through PREFIX keyword
Register field definition includes:
Field name, field length, bit list, and possibly field options (value, type, or reset)
41
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_FIELDS
Register field options:
Value: CAPTURES, DEFAULT, SAFE, or RESETVAL
Type: NOPI, NOPO, NOUPD, MON, PULSE0, PULSE1, SHARED
Reset: PORRESET, TRSTRESET, TAPRESET, or CHRESET
42
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register Assembly
Defines a register / segment by concatenating register segments and fields in the order listed
Listed segments may be defined with REGISTER_FIELDS or a REGISTER_ASSEMBLY
May contain in-line field definitions
Package hierarchy can be added to reference registers / segments in specific package files
DOMCTRL, SEGSEL, SEGSTART, and SEGMUX support excludable segments
43
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_ASSEMBLY
attribute REGISTER_ASSEMBLY of INIT_Example : entity IS "init_data (" &
-- TDI "(init_tail IS init_seg), "& "(SerDesChannel_00 IS Channel), "& "(SerDesChannel_01 IS Channel), "& "(SerDesChannel_02 IS Channel), "& "(SerDesClk_0 IS ChClock) )";
Name of assembled register / segment
Instance name
Register / segment name
44
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_CONSTRAINTS
attribute REGISTER_CONSTRAINTS of init_example : entity is "init_data (" & "( (PDA=={Override})&&( PDB == { Override } ) ) "& " ERROR <Domain A & B cannot both be ON at the same time> "&
")";
For documenting structural constraints on values to be written to a TDR
45
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register and Power Port Association
Providing information that may point to causes of incorrect behavior
To support test, diagnostics, debug
46
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
REGISTER_ASSOCIATION
Attribute REGISTER_PORT_ASSOCIATION of init_example : entity is "VSEL_bits (4) : (PwrUp_IO_VSEL(4)), "& "VSEL_bits (3) : (PwrUp_IO_VSEL(3)), "& "VSEL_bits (2) : (PwrUp_IO_VSEL(2)), "& "VSEL_bits (1) : (PwrUp_IO_VSEL(1)), "& "VSEL_bits (0) : (PwrUp_IO_VSEL(0)), "& "SerDesChannel(0) : (IO_TXP(0),IO_TXN(0),IO_RXP(0),IO_RXN(0)), "& "SerDesChannel(1) : (IO_TXP(1),IO_TXN(1),IO_RXP(1),IO_RXN(1)), "&
... "SerDesChannel(16) : (IO_TXP(16),IO_TXN(16),IO_RXP(16),IO_RXN(16)),"& "SerDesChannel(17) : (IO_TXP(17),IO_TXN(17),IO_RXP(17),IO_RXN(17))";
Allows pairing register bits / fields with specific info
Register field / instance
Port, info, sysclk, or user
47
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
POWER_PORT_ASSOCIATION
attribute POWER_PORT_ASSOCIATION of myIC : entity is "DDR_REF1 : ( DDR_DATA(7), “& " DDR_DATA(6), “& " DDR_DATA(5), “& " DDR_DATA(4), “& " DDR_DATA(3), “& " DDR_DATA(2), “& " DDR_DATA(1), “& " DDR_DATA(0) ), “& "IO_REF1 : ( SERDES(0), SERDES(1) ), "& "IO_REF2 : ( SERDES(2), SERDES(3) )";
Associates reference voltages with dependent I/Os
48
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Register segments, initialization example
49
from IEEE Std 1149.1-2013 Annex D.1
© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Outline
Changes to existing concepts
New concepts
New instructions
New data registers
New BSDL constructs
New: Procedural Description Language (PDL)
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New: Procedural Description Language
Based on TCL
Aligned with PDL in IEEE P1687
Purpose 1149.1 PDL is to load and unload registers or register fields independent of package level
TDR-centric language
Dependent on BSDL and package file(s)
Normative Annex C
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
New: Procedural Description Language
PDL Level 0:
intended to support “load-and-go” ATE
procedures that operate on test data registers (writing to and comparing expected values from registers)
does not return the data captured in the registers
provides very limited flow control
PDL Level 1:
intended to support diagnostic, debug, and test procedures where interactive operation is needed
defines all PDL commands as extensions to Tcl
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© 2014 GOEPEL electronics IEEE Std 1149.1 updates
Thank youHeiko Ehrenberg
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