Cavendish Laboratory, Department of Physics, University of Cambridge Maurice Goodrick <[email protected]>, Richard Shaw
<[email protected]>, Dave Robinson <[email protected]>
Department of Physics and Astronomy, University College London Martin Postranecky <[email protected]>, Matthew Warren
Poster Number 126
Topical Workshop on Electronics for
Particle Physics ( TWEPP-2011 )
Vienna, Austria 26 to 30 Sept. 2011
Digital Atlas Vme Electronics - DAVE - Module
DAVE Module
• ATLAS-SCT have developed a new ATLAS trigger card, 'Digital
Atlas Vme Electronics' ( "DAVE" ) • The unit was designed to provide a versatile array of interface and logic resources, including a large FPGA and NIM signalling
• Interfaces to both VME bus and USB hosts
• Originally planned as replacement for ATLAS-SCT stand-alone trigger & veto logic NIM crate
• Many more generic features added to the design • Re-used ATLAS CTP firmware to exactly duplicate ATLAS running condition
• Random trigger, simple and complex deadtime, ECR, BCR, etc. are being generated to give exactly the same conditions in
standalone running as experienced in combined runs
• DAVE card thus evolved into a powerful and flexible logic module
• Potentially useful to all ATLAS subsystems as well as for other non-ATLAS users ( FPGA with NIM I/O, programmable delays )
• Firmware is developed in a modular fashion allowing code contributions from interested users
• Requirements for CTP-like triggers have been implemented
• Further development will aim to provide ECR generation, source/sink RAM, trigger history and trigger type generation
IN<7-0> TTL/NIM Sel.
CLK-IN<1-0> ECL/NIM Sel.
CLK-OUT<1-0> ECL/NIM Sel.
OUT<7-0> TTL/NIM Sel.
Red LED FPGA Prog.
Xilinx PROM
Prog. FPGA Switch
GSI 18x4Mb SRAM
Ext. 5V/3A Conn.
Spartan3E FPGA
Clock MUX/PLL
VME Base Address A<31-28> A<27-24>
7x Supply Monitor
Red LED 3x Supply OK
80.15733MHz XTAL Osc.
VME J2
Clk+4 Delay Lines
VME J1
Blue LED 4x Supply OK
Set Serial No.
SER<7-4>
SER<3-0>
SIL JTAG for FPGA
USB Reset Switch
Set Mod. Record
MR<7-4>
MR<3-0>
Debug & DownloadDIL for USB MCU
40-pin DIL HEADER
3x LEDs
NIM
ECL
12x LEDs
3
3
3
3
3
SHIFT
REG.
2
CLKIN0
IN0
IN2
IN6
IN4
CLKIN1
CLKOUT0
OUT0
OUT2
OUT6
OUT4
CLKOUT1
SW
SW
SW
22
88
22
88
NIM
ECL
NIM
TTL
NIM
TTL
HEX SELECT
16-pin AUX. CONNECTOR
USB
J-TAG
X-TAL
80.15733MHz
MPX
PLL
:2
40/80MHz select
CLK Master DELAY
4x Slave DELAYS 4
44
CLKIN select
FPGA &
PROM
2
8
4
8
16
6
2
16 ( incl. 2x diff. pairs 2V5 LVDS )
SW
SERIAL NO.
MOD. RECORD
SW
SW
24
40-pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 6x POWER 2x
GND pins32
EXT. +5V IN
FUSES
+3V3 +2V5 +1V8 +1V2 -5V -2V
6x DC-DC
VME
J1
VME
J2
+5V
Bu
ffer
s
VME BASE ADDRESS A<31-24>
16
22
Data 4Mbx18 SRAMAddress
MP-UCL, 18 August 2011
20x
LE
MO
-00 Bu
ffer
s
All POWER Monitor
8
72x LEDs
7
8
8
SHIFT
REG.
Xilinx Spartan3e XC3S1600E-5FGG400C
7
6x FUSES
4 USBMCU
ATLAS SCT
Debug & Download DIL for USB MCU
Ext. +5V / 3A Power Conn.
CLK-IN<1-0> 2x LEMOs 00
Global Reset Switch ( FPGA, MCU )
4-pin USBAUX. DIL 16x I/Os
FPGA JTAG
Prog. MODE Hex Switch.
3x STATUS LEDs ( Programmable )
3x4 LEDs ( Programm. )
Programm. Reset Switch
CLK-OUT<1-0> 2x LEMOs 00
DATA-IN<7-0> 8x LEMOs 00
DATA-OUT<7-0> 8x LEMOs 00
40-pin DIL HEADER
VME J1 VME J2
FOR MORE INFORMATION SEE :
https://twiki.cern.ch/twiki/bin/viewauth/Atlas/DAVEUserGuide
UNIVERSITY OF CAMBRIDGE
CTP-like Trigger ModuleInputEnableSync
OutputEnable
Map
ECR Gen
Orbit Gen
Fine Delays
Mask/ GateDead-time
SRAM
Random Trig
VME/USB Interface
On-Board
FPGA
LEMO I/O LVDS I/O Clocks
RegisterBlock
Recommended
