CSE 567 - Autumn 1998 - Combinational Logic - 1
Multi-Level Optimization
1. Reduce number of literals fewer literals means less transistors (less space) fewer inputs implies faster gates (less switches in series) fan-ins (# of gate inputs) are limited in some technologies
2. Reduce number of gates number of gates (or gate packages) influences manufacturing
costs
3. Reduce number of levels of gates fewer levels of gates implies reduced signal propagation delays minimum delay configuration typically requires more gates
(wider less deep circuits)
Explore tradeoffs between increased circuit delay and reduced gate count automated tools to optimize logic and explore possibilities
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A B DC
X = AC'D + BC'D + ACD' + BCD'
(12 literals and 4 wires, max fan-in = 4)
X = (A+B)C'D + (A+B)CD'
(8 literals and 6 wires, max fan-in = 2)
X = (A+B)(C xor D)
(4 literals and 2 wires, max fan-in = 2)
Optimization Approaches
Exploit common subexpressions (less gates)
Minimize number of literals rather than terms
Trade more levels of logic for reduced fan-in (may also be faster)
No systematic minimization procedure exists as in the two-level case
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manipulate network via a collection of transformations
there exists no algorithm that guarantees an "optimal" multi-level network will be obtained
inputsoutputs
each node is an arbitrarily complex gate
Network Operations
Operations on factored forms elimination decomposition extraction simplification substitution
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divisorquotient
remainder
interesting divisors are called kernels and cubes
Factoring Boolean Expressions
Division with Boolean functionsF = DQ + R D = divisor
Q = quotientR = remainder
Example:X = ac + ad + bc + bd + eY = a + b
X/Y = c + d X = Y (c + d) + e
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G does not divide F under algebraic rules
G does divide F under Boolean rules
(very large number of these)
the key here is the
absorption theorem of
Boolean algebra
Algebraic vs. Boolean Division
Algebraic division – use rules of algebra (see previous example)
Boolean division – use rules of Boolean algebra
F = ad + bcd + eG = a + b
F/G = (a + c) d
F = GQ + R = [G (a + c) d] + e(a + b) (a + c) d + e(aa + ac + ab + bc) d + e(a + bc) d + ead + bcd + e
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Kernels and Cubes
Kernel: cube-free factor of an expression (no cube can factor it evenly)
kernels: a + b, a + cdnon-kernels: a, abc, a(c + d)
Co-kernel: quotient resulting from dividing the expression by the kernel
e.g., F = a c + b c + b’ d’ kernels:a + bco-kernels: c
G = (a + b + c) (d + e) f + g kernels:a + b + c; d + eco-kernels: de, df; af, bf,
cf
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Why Kernels?
Multi-cube algebraic divisors (only other divisors are cubes)
Can be partitioned into a hierarchy (efficient extraction algorithms) level-0 kernel: cannot be divided evenly by a kernel level-n kernel: can be divided evenly only by level-(n-1) kernels
and itself
F = (a (b + c) + d) (eg’ + g (f + e’)) + (b + c) (h + i)
level-0 (among others): b + clevel-1 (among others): a (b + c) + dlevel-2: F
F = j (a (b + c) + d) (eg’ + g (f + e’)) + (b + c) (h + i)
F is level-3 because it contains a level-2 kernel: (a (b + c) + d) (eg' + g (f + e'))
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Tabular Method for Finding Kernels
Use a cube-literal matrix
Rectangles represent a cube
The co-rectangle represents a kernel
e.g. g = abe + acd + bcd
cube = cd
kernel = a+b
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Common-Cube Extraction
Find the cubes common two several expressions
Useful for extracting the cubes (factoring)
e.g. F = abc + abd +egG = abfgH = bd + ef
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Finding Kernel Intersectons
First find the kernels and co-kernels (cubes)
e.g. F = af + bf + ag + cg + ade + bde + cdeG = af + bf + ace + bceH = ade + cde
(Number these cubes in order of appearance)
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Finding Kernel Intersections
The cokernel-cube matrix
A column for each cube
A row for each cube in each function
Numbers indicate which cubes in the corresponding kernel
Rectangles in this matrix correspond to common kernels
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a
b
c
d
e
w
x
y
z
p = ce + de
v = a’d + bd + c’d + ae’
s = r + b’
t = ac + ad + bc + bd + e
u = q’c + qc’ + qcq = a + b
r = p + a’
Example to Illustrate Transformations
Unoptimized logic network
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j = a’ + b + c’ v = jd + ae’
s = ke + a’ + b’
t = kq + e
u = q + c
k = c + d
a
b
c
d
e
w
x
y
zq = a + b
Example to Illustrate Transformations (cont’d)
Optimized network
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a
b
c
d
e
w
x
y
z
p = ce + de
v = a’d + bd + c’d + ae’
s = p + a’ + b’
t = ac + ad + bc + bd + e
u = q’c + qc’ + qcq = a + b
Elimination
Removing a node (too simple a function, better to absorb into other gates)
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a
b
c
d
e
w
x
y
z
p = ce + de
v = jd + ae’
s = r + b’
t = ac + ad + bc + bd + e
u = q’c + qc’ + qcq = a + b
r = p + a’
j = a’ + b + c’
Decomposition
Break a complex node into simpler ones (too complex for a single gate, create opportunities for sharing sub-expressions)
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a
b
c
d
e
w
x
y
z
p = ke
v = a’d + bd + c’d + ae’
s = r + b’
t = ka + kb + e
u = q’c + qc’ + qcq = a + b
r = p + a’
k = c + d
Extraction
Finding common sub-expressions and pulling them out into their own node(most important and complex function in multi-level optimization)
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a
b
c
d
e
w
x
y
z
p = ce + de
v = a’d + bd + c’d + ae’
s = r + b’
t = ac + ad + bc + bd + e
u = q + cq = a + b
r = p + a’
Simplification
Two-level minimization applied to a node (exploit structural don't cares)
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a
b
c
d
e
w
x
y
z
p = ke
v = a’d + bd + c’d + ae’
s = r + b’
t = kq + e
u = q’c + qc’ + qcq = a + b
r = p + a’
k = c + d
Substitution
Reuse existing nodes to make others simpler (closely linked to extraction and decomposition)
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ab x a =1, b = 1, x =1 can never occur
Multi-Level Logic Don’t Cares
Don't cares come from two sources in multi-level circuits
From specification (external explicit don't cares) in terms of circuit inputs and outputs
From structure of circuit graph (internal implicit don't cares) a combination of input and internal values cannot occur or an internal node output is irrelevant for some input
combinations depending on how it is used by its fanout
Both are critical in arriving at minimal circuits
Must be maintained throughout all graph operations
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A is a late arriving inputthat is moved closer to the output by restructuring the logic(i.e., changing DAG structure)
AA
Restructuring Multi-Level Logic for Speed
Decrease fanout of nodes more destinations for a signal implies slower transmission elimination
Decrease fanin of nodes gate speed proportional to square of number of inputs (1st
order) decomposition, simplification
Move late input closer to outputs make path to output shorter, pre-compute other logic Shannon decomposition (f = a fa + a’ fa’)
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Summary of Multi-Level Optimization
Minimization procedures heuristic application of the operations we just listed no guarantee of finding an optimal realization does quite well in a practical amount of time (with algebraic
division)
Everything up to this point has been technology independent just considering literal count or depth of circuit not the types of elements available to actually implement the
circuit
Technology mapping process of converting circuit graph into one where each node
is directly implementable with an available gate or function block
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NAND2area: 4delay: 2
NAND4area: 8delay: 8
AOI21area: 6delay: 5
XOR2area: 16delay: 6
Technology Mapping
Process of transforming logic network so that all nodes can be directly implemented with an available component directed toward area or speed optimization
Requires library of available gates permutations of inputs (e.g., a•b + c – a and b can be
switched) area and delay for each library gate
Example:
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Canonical Representation for Library Cells
Represent function in terms of 2-input NAND gates
Not a unique representation library must represent all non-isomorphic possibilities
Example: F = (ABCD)' has two representations
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node in graph cell in library
Technology Mapping by Tree Matching
Dynamic programming algorithm taken from code generation – Aho and Johnson's TWIG
DAG is viewed as a forest of trees (two options) 1. partition into trees (break graph at fanout nodes) 2. duplicate logic in common sub-trees
Consider adding inverter pairs along any arc of original DAG