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MODULE 5
ARITHMETIC OPERATIONS,
ADVANCED ASSEMBLY
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Content
Module 5 is about the material presented in
module 1 on Data Representation but within
the context of the machine language.
• Signed and Unsigned Numbers
• Building an ALU
• Multiplication and Division revisited
• Floating point
• Hardware supporting FP Arithmetic
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References
• Class Notes
• P&H (4th Edition)
Chapter 3: ―Arithmetic for Computers‖
Appendix C: ―The basic of Logic Design‖ (on book CD
made available on WebCt)
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NUMBERS IN COMPUTERS
So far as it relates to logic circuit design and assembly, we
dealt mostly with natural numbers (0, 1, 2, ...)
We will review the techniques seen in Module 1 to deal with:
• negative numbers,
• the capacity of a number representation,
• fractions and real numbers.
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NUMBERS IN COMPUTERS cont.
n being the number of digits
MIPS words are 32 bits long, but we continue the discussion with16 bits half words.
To clarify the notation, the leftmost bit (bn-1) has the largest
number and is called the most significant bit (MSB).Bit 0 (b0) is the least significant bit (LSB).
There are several techniques to represent negative numbers.
The method almost universally used the two’s complement representation.
1
02
n
i
i
ib x
821212021211110113210
tentwo
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
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TWO’s COMPLEMENT REPRESENTATION
Because an even number
of numbers (216) can be
represented with a fixed
number of bits (16),
we have a skewed
representation.
Range: -215 to 215-1
0000 0000 0000 0000 = 0ten
0000 0000 0000 0001 = 1ten
0000 0000 0000 0010 = 2ten
0000 0000 0000 0011 = 3ten
...
0111 1111 1111 1110 = +32766ten
0111 1111 1111 1111 = +32767ten
1000 0000 0000 0000 = - 32768ten
1000 0000 0000 0001 = - 32767ten
...
1111 1111 1111 1101 = - 3ten
1111 1111 1111 1110 = - 2ten
1111 1111 1111 1111 = - 1ten
Zero is uniquely represented by:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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TWO’s COMPLEMENT REPRESENTATION cont.
Properties of the two‘s complement representation:
• x + (-x) = 2n
• two‘s complement range goes from -2n-1 to 2n-1-1 (-215 to 215-1)
• Hence 2n truncates to zero (216)
• single zero• all negative numbers have the MSB equal to 1 (sign bit)
for example:11102 -1(2)3 + 1(2)2 + 1(2)1 + 0(2)0=-8+4+2 = -210
111102 -1(2)4 + 1(2)3 + 1(2)2 + 1(2)1 + 0(2)0
= -16 + 8 + 4 + 2 =-210
0
0
13
13
14
14
15
15)2(...)2()2()2( bbbbx
0000 0000 0000 0011 = 3ten
1111 1111 1111 1101 = - 3ten
1 0000 0000 0000 0000 = 0ten
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USEFUL SHORTCUTS
To negate a given number. Invert every bit and add 1.
Convert to numbers of different size (sign extension):
The bit sign is copied to capacity if the new word is longer.
The number is truncated if the new word is shorter.
0000 0000 0000 0010 = 2ten invert
1111 1111 1111 1101 add 1
1111 1111 1111 1110 = -2ten invert
0000 0000 0000 0001 add 1
0000 0000 0000 0010 = 2ten
0000 0000 0000 0010 = 2ten 16 bits
0000 0000 0000 0000 0000 0000 0000 0010 32 bits
1111 1111 1111 1110 = -2ten 16 bits
1111 1111 1111 1111 1111 1111 1111 1110 = -2ten 32 bits
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SHORTCUTS cont.
• Shifting left (or right) performs multiplication (or division) by
powers of two
e.g. shift left by 2 bit x 4 (22); shift right by 4 16 (24)
• The shift operation preserves the sign if zeros are entered on
the right and the sign bit propagated on the left:
0000 0000 0000 0000 0000 0000 0000 0011 = 3ten
Shift left x20000 0000 0000 0000 0000 0000 0000 0110 = 6ten
1111 1111 1111 1111 1111 1111 1111 1111 = -1ten x 2
1111 1111 1111 1111 1111 1111 1111 1110 = -2tenx 2
1111 1111 1111 1111 1111 1111 1111 1100 = -4ten
21111 1111 1111 1111 1111 1111 1111 1110 = -2ten
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SIGNED AND UNSIGNED
• Signed numbers are not always needed.
• For example, memory addresses run from 0 to thelargest. In the C language, integers can be declared to beunsigned .
• The result of a comparison will depend on whether the
compared numbers are assumed to be signed or
unsigned.• Need new comparison instruction to account for that.
We had:
slt $1, $2, $3
slti $1, $2, 100We add two new instructions:
sltu $1, $2, $3
sltiu $1, $2, 100
For comparing signed numbers
For comparing unsigned numbers
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SIGNED AND UNSIGNED - EXAMPLE
Example:
Supposed
$S0 = 1111 1111 1111 1111 1111 1111 1111 1111
$S1 = 0000 0000 0000 0000 0000 0000 0000 0001
$S0‘s value means -1 if signed number, or 4,294,967,295 if
unsigned.
slt $t0, $S0, $S1 # -1 < 1 t0 = 1
sltu $t0, $S0, $S1 # 232-1 > 1 t0 = 0
Comparing these two numbers to 1 will yield different results,
whether they are considered to be signed or unsigned.
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SIGNED AND UNSIGNED cont.
However, the hardware that performs additions and
subtractions does not depend on whether the numbers are
signed or unsigned, because the subtraction is achieved
by negating a number and then adding. More on that
later.
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ADDITION AND SUBTRACTION IN HARDWARE
Subtraction works the same with the manual method or via thetwo‘s complement and add.
One problem is that the sum of two numbers (signed or
unsigned) may exceed the capacity of the registers.
0000 0000 0000 0111 = 7ten
+ 0000 0000 0000 0110 = 6ten
0000 0000 0000 1101 = 13ten
0000 0000 0000 0111 = 7ten
+ 1111 1111 1111 1010 = -6ten
0000 0000 0000 0001 = 1ten
0111 1111 1111 1111 = +32767ten
+ 0000 0000 0000 0010 = + 2ten
1000 0000 0000 0001 = - 32767ten
0000 0000 0000 0111 = 7ten
- 0000 0000 0000 0110 = 6ten
0000 0000 0000 0001 = 1ten
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ADDITION AND SUBTRACTION cont.
The results obtained in the last addition of the previous slide
is obviously wrong. We would need one more bit.
The same thing could occur with two negative numbers.
However, it cannot occur with numbers of opposite signs.
One method to detect occurrence of overflow is to check the
validity of the sign of the results. Overflow conditions:
Operation A BCorrect
Result
Result indicating
an OverflowA + B >= 0 >= 0 >= 0 < 0
A + B < 0 < 0 < 0 >= 0
A – B >= 0 < 0 >= 0 < 0
A – B < 0 >=0 < 0 >= 0
d l i h i O i d d bl
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ACCOUNTING FOR OVERFLOWS
• When an overflow is detected, it may create an exception (orinterrupt), that is, an abnormal condition.
• The way the computer handles exceptions is similar toprocedures, with the difference that it is unplanned by the user.
• The computer jumps to a fixed address outside the control of the user.
Later we will cover the hardware needed to handle exceptions.
For now, the new instructions introduced have the property of
ignoring exceptions.
addu $1, $2, $3
addiu $1, $2, 100
subu $1, $2, $3
M d l 5 A ith ti O ti Ad d A bl
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ACCOUNTING FOR OVERFLOWS cont.
What is the connection between unsigned numbers andoverflow?
Unsigned numbers can create overflows like the others butthe computer designers (that‘s you) chose to ignore them.
So actually addu, addiu, and subu do exactly the sameoperation than add, addi, and sub, but do not cause
exceptions.
Note that unsigned integer usually are used for memoryaddressing where overflow is ignored.
M d l 5 A ith ti O ti Ad d A bl
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LOGICAL OPERATIONS
• There is a class of operations to manipulate the bits inside
a word without attributing a special meaning to them.
• There are called logicals.
First, shift : bits are moved a number of places left to right.
0000 0000 0000 0000 0000 0000 0000 1010shifted left eight (8) places yields
0000 0000 0000 0000 0000 1010 0000 0000
Two new instructions for logical left shift and logical right
shift:
sll $10, $16, 8 # $10 = ($16 << 8)
srl $10, $16, 8 # $10 = ($16 >> 8)
M d l 5 A ith ti O ti Ad d A bl
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LOGICAL OPERATIONS cont.
This explains the necessity for the shamt (shift amount) filed
in the R format instructions.
There exists other kinds of shifts. The most important is the
shift right arithmetic which preserves the sign bit (sra)
and rotate left and right (rol, ror).
Example for instruction sra:
1111 0000 0000 0000 0000 1010 0000 0000
1111 1111 1111 0000 0000 0000 0000 1010 (shift by 8)
op rs rt rd shamt funct
0 0 16 10 8 0
M d l 5 A ith ti O ti Ad d A bl
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LOGICAL OPERATIONS cont.
• Other useful logical operations have to do with the logicaloperators, AND, OR, (NOR, XOR, NOT).
• Each bit of the result is the result of a logical operationbetween each bit of the operands.
Example:
This is often used to apply a mask , which forces all bits to
zero except those set to 1 in the mask.
Similar operation for OR (to combine portions of a word)
0000 1010 0000 1000 0000 1010 0000 0000
AND 0000 0000 0000 0000 1111 1111 1111 11110000 0000 0000 0000 0000 1010 0000 0000
0000 1010 0000 1000 0000 1010 0000 0000
OR 0000 0000 0000 0000 1111 1111 1111 1111
0000 1010 0000 1000 1111 1111 1111 1111
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LOGICAL OPERATIONS cont.
We have instructions as well as the ―immediate‖ version:
and $1, $2, $3 # $1 = $2 & $3
or $1, $2, $3 # $1 = $2 | $3
andi $1, $2, 100 # $1 = $2 & 100
ori $1, $2, 100 # $1 = $2 | 100
Note:
In andi and ori, the 16 bit constant is padded with leading
0‘s (zero-extended).
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Arithmetic Logic Unit (ALU)
The ALU is a digital circuit used to perform arithmetic
operations (addition, subtraction, multiplication, division)
and logical operation (AND, NOT, OR, XOR, SHIFT...)
The ALU gets the info about which operation to do from the
instruction itself (opcode field op)
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CONSTRUCTION OF ALU
• The Arithmetic and Logic Unit (ALU) is a combinational logicblock constructed from four (4) hardware building blocks:
• AND and OR gates, inverters, and multiplexers
• The ALU carries out the operations specified by instructions.
• It takes two 32 bit operands and produces a 32-bit result
according to the values of control lines.
1. A 1-bit ALU performs a logical AND or a logical OR on twobits (a & b).
2:1 mux2:1 mux selects either:(0) a AND b(1) a OR b
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ADDITION IN THE ALU
2. ADDITION: for each bit, the result is found by adding two
bits and the carry from the preceding bit.
There are two results: the sum and the carry, so there are
three inputs and two outputs.
This block is referred to as the full adder.
+
Carry In
Carry Out
SUM
a
b
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SPECIFICATION FOR A 1-BIT ADDER
Inputs OutputsComments
a b Carry In Carry Out Sum
0 0 0 0 0 0 + 0 + 0 = 00two
0 0 1 0 1 0 + 0 + 1 = 01two
0 1 0 0 1 0 + 1 + 0 = 01two
0 1 1 1 0 0 + 1 + 1 = 10two
1 0 0 0 1 1 + 0 + 0 = 01two
1 0 1 1 0 1 + 0 + 1 = 10two
1 1 0 1 0 1 + 1 + 0 = 10two
1 1 1 1 1 1 + 1 + 1 = 11two
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ADDITION IN THE ALU cont.
The simplified logic functions for the two outputs are:
= (a xor b) xor CarryIn
CarryInbaCarryInbaCarryInbaCarryInbaSum
baCarryInaCarryInbCarryOut
CarryOut
Sum
+
Carry In
Carry Out
SUM
a
b
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ADDITION IN THE ALU cont.
Connecting all the blocks together leads to a 32-bit ripple adder because the carry (CarryOut) from the LSB may propagate all
the way through.
1 bit ALU
32 bit ALU
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What operation is selected if OPERATION = 00102 (i.e.what is the function associated to output Results?
1.a + b
2.a & b
3.a | b4.a + b + CarryIn
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What are the operations performed by the ALU ?
a) The ALU performs logical and arithmetic operations.
b) The ALU accesses the memory directly to store andload 32 bit words in one of the 32 registers.
c) The ALU can only add two 32 bit operands toproduce a 32-bit result using a 32-bit full-adder
d) The ALU accepts two 32 bit operands and producesa 32-bit result according to the values of controllines.
e) Answers a) and d)
f) Answers b) and c)
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Arithmetic Logic Unit (ALU)
The ALU is a digital circuit used to perform arithmetic
operations (addition, subtraction, multiplication, division)
and logical operation (AND, NOT, OR, XOR, SHIFT...)
The ALU gets the info about which operation to do from the
instruction itself (opcode field op)
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ADDITION IN THE ALU cont.
Connecting all the blocks together leads to a 32-bit ripple carry adder . Its name come from the fact that the carry (CarryOut)
from the LSB propagates (ripples) all the way through.
1 bit ALU 32 bit ALU
LSB
MSB
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SUBTRACTION IN THE ALU
• Change the sign of operand b by inverting its bit and thenadd 1 (two‘s complement a – b = a + (-b) ).
• Need to add an extra inverter and a 2:1 multiplexer.
• The unused CarryIn input of the least significant bit (LSB)is used to supply the 1.
a + (-b)
ADD/SUB
MUX
LSB
0 AND1 OR
2 ADD/SUBSUB
babababa )()1(1LSB:
0 ADD
1 SUB
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OTHER LOGICAL OPERATIONS NEEDED
A MIPS ALU also needs a NOR function.
How to make a NOR by reusing the hardware?
0
1
0
1
a
b
a NOR b = a + b = a ∙ b
From DeMorgan‘s theorem
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Assuming that the 1-bit ALU shown below is for theLSB, what binary value should Binvert and CarryIn be
for operation a – b?
1.Binvert = 0; CarryIn = 0
2.Binvert = 0; CarryIn = 1
3.Binvert = 1; CarryIn = 04.Binvert = 1; CarryIn = 1
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OUR ALU SO FAR…
The ALU up to now can do four operations which are foundin almost every computer:
Add, Subtract, AND ,OR
Most MIPS instructions can be performed, but the design isstill incomplete.
Comparison instructions such as set on less than (slt).
Set to 1 if rs < rt, and 0 otherwise.A slt instruction will set all but LSB to 0 and LSB set
according to the comparison.
Expand the three-input mux
Add input for slt resultThe input Less is connected to 0
for upper 31 bits
The input Less of LSB depends
comparison (i.e. rs < rt?)
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COMPARISON
Need a special 1-bit ALU for the most significant bit (MSB) sinceoutput of the adder is 1 if a – b < 0 (a < b) and 0 otherwise.
This is the same as checking if the result is negative or positive!
The Overflow detection checks:
sign a, sign b, sign result
Set
1: a < b
0: a >= b
1: a < b
0: a >= b
Used output
of adder
1. a – b2. Test if MSB = 1
(negative)3. If yes,
a < bLSB = 14. If no,
a ≥ b LSB = 0
sltu $S1, $S2, $S3
The ALU will do $S2 - $S3
and check the MSB (sign bit)
Results:
0000 … 1 (all other bits = 0)
Results:0000 … 0
MSB ALU has now 3 outputs: Results, Set, Overflow
MSB ALU
Result = less
all 0 exceptLSB
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COMPARISON cont.
On the left is the multiple 1-bit ALUcells connected together with the
special ALU (ALU31) for the MSB.The ―less‖ inputs all connected to zero
except for LSB which is connectedto ―set‖ output of MSB:
If a – b < 0,
a < b result is 000 … 1
otherwise 000 … 0
Special ALU detects a < bor result of a – b < 0
If yes
LSB
1 (other bits
0)
LSB
MSB
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The FINAL 32-bit ALU
Note that both CarryIn and Binvert are set to 1 for asubtraction or set to 0 for addition or logical operations.
use a single control line for both: Bnegate.
Last point how to support conditional branch instructionssuch as branch if equal beq .
beq a, b, label
a – b = 0?
Add hardware to test if
the result is 0 by using OR
on all results
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CPU MAIN FUNCTIONS
Program Counter (PC) supply instruction address.
Register specified by instruction.
ALU can do the following: compute an arithmetic result or
compare. It can also compute a memory address (more later).
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THE 32-BIT ALU DEVELOPED SO FAR
ALU31(MSB)
ALU30 ALU29 ALU28 ALU27 ... ALU5 ALU4 ALU3 ALU2 ALU1 ALU0(LSB)
a 0 1 0 0 1 ... 0 1 0 0 1 1
b 0 0 1 0 1 ... 1 0 1 0 0 0
Symbol commonly usedto represent an ALU
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THE ALU CONTROL LINES
ALU Operation Four control lines:
1. Ainvert (select a or a‘)2. Bnegate (select b or b‘ as well as carryIn of LSB)
3. 2-bit Operation Lines for the 4:1 mux (and,or, add, less).
Summary of the control lines:
CONTROL LINES FUNCTION
0000 And
0001 Or
0010 Add0110 Subtract
0111 Set-less-than
1100 NOR
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Recall this slide from Module 2 FULL ADDER
Word Width Full Adders (a ‗word‘ is made of n bits)
An n-bit full-adder can be fabricated by cascading togethern full-adder modules as shown above.
What are the PROPAGATION DELAYS corresponding to Σ and Co in each one-bit full adder?
• 3 gate delays for Σ (negating inputs adds 1 delay)
• 2 gate delays for Co (there are no inverted inputs)
CarryInbaCarryInbaCarryInbaCarryInbaSum
baCarryInaCarryInbCarryOut
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Recall this slide from Module 2 FULL ADDER
Then, what is the propagation delay for the n-bit adder?
• (n-1) x 2 gate delays to propagate carry to the last full
adder in the chain (up to output Cn-2)
+
• 3 gate delays to produce the final sum (output ∑n-1)
• Total propagation delay = 2n + 1 gate delays!
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Need for Faster Addition
There is a problem with the 32-bit
ripple carry adder in the ALU.
It takes 2(32)+1 gate delays to
complete the results because the
carry must propagate through all
1-bit full adder!
To speed things up determine
the carry sooner for high-order
bits by adding some hardware.
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FASTER ADDITION: FAST CARRY
One may anticipate the carry to speed up the addition, but at thecost of more gates.
In theory we can calculate the values of any bit carry using onlytwo gate levels.
For example, CarryIn for bit 2 of the adder is exactly the CarryOutof bit 1 (from slide 26, Module 5):
and CarryIn1 is defined as:
Using abbreviations for simplified expressions of ci for CarryIn_i :
0000001
1111112
bacacbc
bacacbc
111_11_11_2_ baCarryInaCarryInbCarryOutCarryIn
000_00_01_ baCarryInaCarryInbCarryIn
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FASTER ADDITION: FAST CARRY cont.
If we replace c1 in equation for c2, we obtain:
Logic function c2 can be implemented with seven AND gates
and one 7-input OR gate.
By adding some hardware (i.e. gates) to implement the
logic function above, carryIn2 (c2) becomes known morequickly (2 gate delays instead of 4).
For a wide adder, unfortunately, the size of the logic block
would be enormous making this approach not so practical.
110010010010010010012 bacbbcabbabcbacaabaac
0000001
1111112
bacacbc
bacacbc
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CARRY-LOOKAHEAD ADDER
Carry-lookahead is a more economical technique because itsimplifies the hardware.
From the previous two slides, we know that the carry in forthe next bit (ci+1) can be defined in terms of the infofrom ALU i.
Rewriting the equation for C2 from the previous slide:
cibiaibiaici
biaiciaicibici
1
1
11001001001
0010010012
bacbbcabbab
cbacaabaac
)0000011112 cbabababac
c1
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CARRY-LOOKAHEAD cont.
Note the repeated appearance of (ai∙bi) and (ai+bi). These importantfactors are referred to as generate and propagate, respectively:
Using them, we can rewrite the expression for carryout as:
ci+1 = gi + pi∙ci
So if gi is 1 then the adder generates a CarryOut (ci+1)
independent of CarryIn (ci ) ci+1 = 1 + pi∙ci = 1
If gi is 0, but pi is 1 CarryIn is being propagated to Carryout.
ci+1 = 0 + 1∙ci = ci
*So CarryIni+1 will be 1 if either gi is 1 or pi is 1 and Carryini is 1.
iii
iii
ba p
bag
Generates a carry regardless of CarryIn
Propagates a CarryIn to a CarryOut
)0000011112 cbabababac
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CARRY-LOOKAHEAD cont.
We can rewrite the carry expression in terms of gi and pi for thefirst 4 bits:
Essentially, a CarryIn i obtained if some earlier adder generated acarry (gi ) and all intermediary adders propagated a carry (pi ).
We see that for n bits, we have n+1 terms and the longest term hasn+1 factors, where in the previous case there was a geometricalgrowth.
For a large adder, this is still not practical.
0012301231232334
00120121222223
001011000111112
0001
cppppgpppgppgpgc
cpppgppgpgcpgc
cppgpgcpgpgcpgc
cpgc
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Carry-Lookahead Analogy
Plumbing analogy for carry
lookahead for 1 bit, 2 bits,
and 4 bits using water pipes
and valves.
Nice idea, but still not practical
for 32-bit adder.
P&H, page C-42
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CARRY-LOOKAHEAD PER N-BIT BLOCKS
One other idea is to build n-bit adder blocks and to ripple thecarry from block to block.
These blocks are often 4-bit (n=4) adders which have only oneCarryIn and one CarryOut by performing carry look ahead for 4-bit adders.
For a 16-bit adder, the propagate signals can be calculated for
each 4-bit adder block:
P0 = p3 ∙ p2 ∙ p1 ∙ p0
P1 = p7 ∙ p6 ∙ p5 ∙ p4
P2 = p11 ∙ p10 ∙ p9 ∙ p8 P3 = p15 ∙ p14 ∙ p13 ∙ p12
Pi is the ‗super‘ propagate signal for a 4-bit block.
Pi =1 if each of the bits in the group will propagate a carry.
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CARRY-LOOKAHEAD PER N-BIT BLOCKS cont.
The ―super‖ generate signal Gi will be true if all the bits willgenerate a carry from the most significant bit of the group
only:
G0 = g3 + (p3 ∙ g2) + (p3 ∙ p2 ∙ g1) + (p3 ∙ p2 ∙ p1 ∙ g0)
G1 = g7 + (p7 ∙ g6) + (p7 ∙ p6 ∙ g5) + (p7 ∙ p6 ∙ p5 ∙ g4)
G2 = g11 + (p11 ∙ g10) + (p11 ∙ p10 ∙ g9) + (p11 ∙ p10 ∙ p9 ∙ g8)
G3 = g15 + (p15∙g14) + (p15∙p14∙g13) + (p15∙p14∙p13∙g12)
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CARRY-LOOKAHEAD PER N-BIT BLOCKS cont.
Then for a 16-bit adder, the carry out equations have similar formas before (slide 52):
C1 = G0 + (P0 ∙ c0)
C2 = G1 + (P1 ∙ G0) + (P1 ∙ P0 ∙ c0)
C3 = G2 + (P2 ∙ G1) + (P2 ∙ P1 ∙ G0) + (P2 ∙ P1 ∙ P0 ∙ c0)
C4 = G3+(P3∙G2)+ (P3∙P2∙G1)+ (P3∙P2∙P1∙G0)+ (P3∙P2∙P1∙P0∙c0)
Extra logic, but saves time
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How many gate delays is required to determine C4? Note that Pi is determined in one gate delay (slide 54).Gi is determined in two gate delays using gi and pi (slide 55).
Finally, gi and pi are each one gate delay using ai and bi (slide 51).
C4 = G3+(P3∙G2)+ (P3∙P2∙G1)+ (P3∙P2∙P1∙G0)+ (P3∙P2∙P1∙P0∙c0)
From slide 54: P0 = p3 ∙ p2 ∙ p1 ∙ p0
P1 = p7 ∙ p6 ∙ p5 ∙ p4
P2 = p11 ∙ p10 ∙ p9 ∙ p8
P3 = p15 ∙ p14 ∙ p13 ∙ p12
From slide 55:
G0 = g3 + (p3 ∙ g2) + (p3 ∙ p2 ∙ g1) + (p3 ∙ p2 ∙ p1 ∙ g0)
G1 = g7 + (p7 ∙ g6) + (p7 ∙ p6 ∙ g5) + (p7 ∙ p6 ∙ p5 ∙ g4)
G2 = g11 + (p11 ∙ g10) + (p11 ∙ p10 ∙ g9) + (p11 ∙ p10 ∙ p9 ∙ g8)
G3 = g15 + (p15∙g14) + (p15∙p14∙g13) + (p15∙p14∙p13∙g12)
From slide 51: iii
iii
bap
bag
1) 4
2) 5
3) 64) 32
5) 33
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CARRY-LOOKAHEAD PER N-BIT BLOCKS cont.
To determine C4, there is two gate delays using Gi andPi
Pi is determined in one gate delay
Gi is determined in two gate delays using gi and pi
gi and pi are each one gate delay using ai and bi
Thus, C4 is know is 1+2+2 = 5 gate delays
Without carry-lookahead, the delay would be 32 gate
delays!
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NOW, LET’S LOOK AT MULTIPLICATION USING ALU
First, let‘s review the multiplication of decimal numbers.Multiplying 1000ten by 1001ten:
1000 Multiplicand
1001 Multiplier
1000
00000000
10001001000 Product
(m bits X n bits = m+n bit product)
Basically, we place a copy of the multiplicand if the
multiplier‘s digit is 1 or place 0 otherwise.
4 bits
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MULTIPLICATION cont.
Turn it into hardware by shifting right the multiplier to test
the successive bits and shifting left the multiplicand.
32 bit shifted 32 times to the left
register
shift no matter what(may need to add)
register
add?
decides when to shift and
when to write into product register
register
Initialized to 0 LSB
1000Multiplicand1001Multiplier1000
00000000
10001001000
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• Step 1 – test Multipler0, which is
the LSB of the multiplier
• Step 2 – moves the intermediate
operands to the left
• Step 3 - Next bit of the
multiplier becomes LSB
MULTIPLICATION FLOWCHART
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Multiplication Example
1000 x 1001 =
1 0 0 1
multipliermultiplicand
product
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0
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Multiplication Example
1000 x 1001 =
1 0 0 1
multipliermultiplicand
product
0 0 0 0 0 0 0 0
Test? Yes0 0 0 0 1 0 0 0
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Multiplication Example
1000 x 1001 =
1 0 0 1
multipliermultiplicand
product : add multiplicand
0 0 0 0 1 0 0 0
Test? Yes0 0 0 0 1 0 0 0
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Multiplication Example
1000 x 1001 =
0 1 0 0
multiplier shift rightmultiplicand shift left
product
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
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Multiplication Example
1000 x 1001 =
0 1 0 0
multipliermultiplicand
product
0 0 0 0 1 0 0 0
Test? no0 0 0 1 0 0 0 0
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Multiplication Example
1000 x 1001 =
0 0 1 0
product
0 0 0 0 1 0 0 0
0 0 1 0 0 0 0 0
multiplier shift rightmultiplicand shift left
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Multiplication Example
1000 x 1001 =
0 0 1 0
multipliermultiplicand
product
0 0 0 0 1 0 0 0
Test? no0 0 1 0 0 0 0 0
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Multiplication Example
1000 x 1001 =
0 0 0 1
product
0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 0
multiplier shift rightmultiplicand shift left
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Multiplication Example
1000 x 1001 =
0 0 0 1
multipliermultiplicand
product
0 0 0 0 1 0 0 0
Test? yes!0 1 0 0 0 0 0 0
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Multiplication Example
1000 x 1001 =
0 0 0 1
multiplier
0 1 0 0 0 0 0 0
multiplicand
product : add
0 1 0 0 1 0 0 0
Test? yes!
Shifted 4 times corresponding to the 4 bits of the multiplier.Done!
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION t
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MULTIPLICATION cont.
Why is this approach to multiplication inefficient?
If each step is 1 clock cycle, it implies 100 clock cycles for two (2)
32-bit numbers!!
How could we speed things up?
Do things in parallel!
The multiplier and the multiplicand are shifted while the
multiplicand is added to the product if the multiplier bit is 1.
Because parts of the hardware have unused portions, it is further
optimized by halving the width of the adder (32 bits) and the
registers (32-bit).
Revised hardware for multiplication is shown in the next slide.
Module 5 – Arithmetic Operations, Advanced Assembly
F ll i th lti li ti fl t d i th l t
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Following the multiplication flow presented in the lastclass, what happens next?
1010 x 1011 =
1 0 1 1
4-bit multiplier register8-bit multiplicand register
8-bit product register
0 0 0 0 0 0 0 0
Test? Yes0 0 0 0 1 0 1 0
1) multiplicand and multiplerregisters are shifted by 1 bit
2) nothing happens
3) multipler is added to theproduct register
4) multiplicand is added to theproduct register
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION cont
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MULTIPLICATION cont.
Why is this approach to multiplication inefficient?
If each step is 1 clock cycle, it implies 100 clock cycles for
two (2) 32-bit numbers!!
How could we speed things up?
Instead, do things in parallel!
Note that both the multiplier and the multiplicand are shifted while
the multiplicand is added to the product if the multiplier bit is 1.
Because parts of the hardware have unused portions, further
optimization is possible by halving the width of the adder (32
bits) and the registers (32-bit).
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION IMPROVEMENT
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MULTIPLICATION – IMPROVEMENT
Instead of shifting the multiplicand left where it ends up using 64bits, the product is shifted right.
Further saving is achieved by combining the multiplier and theproduct into one 64 bit register.
• The multiplicand, ALU and Multiplier register are all 32 bits wide.
• Product register is 64 bits with the multiplier in the right half.
multiplier
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION ALGORITHM
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MULTIPLICATION - ALGORITHM
0. Init.
Place Multiplicand in Multiplicand register.Place Multiplier in lower half of Product register.
Clear upper half of Product register.
1. Test and Update.
If the LSB of Product register is 1, add Multiplicand register to
upper half of Product register and place results back in the
upper half of Product register.
2. Shift.Product register shifted right one 1 bit
3. Count.
if 32nd repetition then done else goto step 1.
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION EXAMPLE
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10002 x 10012 =
0 0 0 0 1 0 0 1
Product Multiplier
8-bit product register with 4-bit
multiplier place in lower half
MULTIPLICATION - EXAMPLE
Multiplicand x Multiplier
Initialized
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MULTIPLICATION EXAMPLE
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0 1 0 0 0 1 0 0
Test? Yes0 0 0 0 1 0 0 1
Product Multiplier
1 0 0 0 1 0 0 1
Add
0 1 0 0 0 1 0 0
Shift
Test? No
Shift
0 0 1 0 0 0 1 0
MULTIPLICATION - EXAMPLE
10002 x 10012 =
Module 5 – Arithmetic Operations, Advanced Assembly
MULTIPLICATION EXAMPLE
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10002 x 10012 =
Test? No0 0 1 0 0 0 1 0
0 0 0 1 0 0 0 1
Shift
Test? Yes!
1 0 0 1 0 0 0 1
Add
0 1 0 0 1 0 0 0 N=4. DONE!
0 0 0 1 0 0 0 1
MULTIPLICATION - EXAMPLE
Shift
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED MULTIPLICATION
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SIGNED MULTIPLICATION
• One way to multiply two signed numbers:
o Find sign of each operand (multiplicand and multiplier)
o Make each operand a positive number
o Multiply the two positive numbers
o Change sign of product accordingly
Works and easy to follow and understand
• More elegant approach to multiplying signed numbers:
Booth‘s algorithm
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED MULTIPLICATION cont
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SIGNED MULTIPLICATION cont.
First, let‘s see how there are multiple ways to computer a product.
Example: 2ten by 6ten (0010two by 0110two):
2 x 6 =12
0 0 1 0 multiplicand
x 0 1 1 0 multiplier
+ 0 0 0 0 shift (0 in multiplier)
+ 0 0 1 0 add (1 in multiplier)
+ 0 0 1 0 add (1 in multiplier)
+ 0 0 0 0 shift (0 in multiplier)
0 0 0 0 1 1 0 0
P&H IMD 3.11
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED MULTIPLICATION cont
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SIGNED MULTIPLICATION cont.
Knowing that the ALU can add or subtract, the same answer
could be obtained through different ways.
For example:
610 = -210 + 810, so could do 2 x (-2 + 8) = 12
01102 = -00102 + 10002 (11102 + 10002 =01102)
In Booth‘s algorithm, a string of n 1‘s in the multiplier is
replaced by a 1 followed by n 0‘s.
112 (310) 1002 (410) But this adds 1...
This is compensated by pre-subtracting the multiplicand
at the beginning of the sequence of 1‘s
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED MULTIPLICATION – Booth’s Algorithm
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SIGNED MULTIPLICATION – Booth s Algorithm
We replace a string of 1s in the multiplier with an initial
subtract when we see a 1.
Then later we add when we see the bit after the last 1.
Here is our example again: 2 x 6
0 0 1 0 Multiplicandx 0 1 1 0 Multiplier
+ 0 0 0 0 shift (0 in multiplier)- 0 0 1 0 sub (first 1 in multiplier)+ 0 0 0 0 shift (middle of string of 1s)
+ 0 0 1 0 add (prior step had last 1)
0 0 0 0 1 1 0 0
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM
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BOOTH S ALGORITHM
• Andrew Donald Booth (1918-2009) invented this approach to
speed up the algorithm (in machines of his era, shifting wasfaster than addition).
• For some patterns, his algorithm is indeed faster AND handles
signed numbers as well.
• Key insight: Classifying groups of bits into:
- Beginning
- Middle
- End
of a run of 1s:
• Can leave strings of 0s alone.
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont
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Instead of looking at one bit in the multiplier, we are looking at2 bits:
BOOTH S ALGORITHM cont.
P&H IMD 3.11
Product | Multiplier
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
• Booth changes the first step of the multiplication
algorithm (looking at 1 bit of multiplier and deciding
whether to add multiplicand) to looking at 2 bits of
the multiplier.
• New first step has 4 cases, depending on values of 2
bits.
• Look at current bit and bit to the right.
• Still need to shift the product to the right.
• New algorithm in the following slide:
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
1. Depending on the current and previous bits, do one of the
following:
00: Middle of string of 0s, no arithmetic
01: End of string of 1s, add multiplicand to left half of product
10: Beginning of string of 1s, subtract multiplicand fromleft half of product
11: Middle of string of 1s, no arithmetic
2. As in the previous algorithm, shift the Product register right 1bit.
Pros: Can skip over strings of 1s.
Cons: Bad for 101010...
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
Things to keep in mind when using this algorithm:
• Need to add a bit to the right of the rightmost bit of the
product register.
• Recall that shifting the product right must preserve the
sign of the intermediate result (since we are dealing with
signed numbers)
• Need to perform arithmetic shift right .
The new algorithm is shown in the following slide.
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont
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Perform 210 x 610 = 1210
BOOTH S ALGORITHM cont.
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
Now perform 210 x -310 = -610
00102 x 11012 = 00102 x –(00112) = -(01102) = 10102
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
Why does this apply to signed numbers? Let‘s call a the multiplierand b the multiplicand. ai and bi are the bits of these numbers.
(do nothing, add b, or subtract b)
The Product obtained with Booth‘s algorithm can be written as:
but so,
The same reasoning could be carried out swapping a and b.
The Booth algorithm does nothing but implements the encoding of two‘s complement numbers!
1,1,0)( 1 oraa ii
31
3130
2
21
1
10
0
012)(...2)(2)(2)(
baabaabaabaa
31
31
31
30
2
2
2
1
1
1
1
0
0
022...22222 aaaaaaab
i
i
i
i
i
i aaa 2221
abaaaab 31
31
2
2
1
10 2...22
ai ai-1 action0 0 do nothing0 1 add b1 0 sub b1 1 do nothing
2’s compl. of a
Module 5 – Arithmetic Operations, Advanced Assembly
BOOTH’S ALGORITHM cont.
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BOOTH S ALGORITHM cont.
• Intuition for why Booth‘s algorithm works:
M x (00111110) = M x (25+24+23+22+21) = M x 62
• Number of operations can be reduced to 2 by rewriting:
M x (01000000-10) = M x (26 - 21) = M x 62
When 1‘s in multiplier are grouped into long blocks, Booth‘s
algorithm performs fewer additions (and subtractions)
than regular algorithm.
Module 5 – Arithmetic Operations, Advanced Assembly
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In multiplication using Booth’s algorithm, what
arithmetic operation is performed next by the ALU if
bits a0 and a-1 in the product register are 1 and 0,respectively?
1. Logical AND
2. Addition
3. bit a-1 doesn‘t exist 4. Subtraction
5. Shift
Module 5 – Arithmetic Operations, Advanced Assembly
MORE EXAMPLES USING BOOTH’S ALGORITHM
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multiplicand multiplier
5 x -3 = -15 -5 x -6 = 30
Module 5 – Arithmetic Operations, Advanced Assembly
What is the Booth Algorithm?
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What is the Booth Algorithm?
a) An algorithm used in addition that handles signed
numbersb) An algorithm used in multiplication operation that
handles signed numbers
c) An algorithm that allows a multiplication to be
performed in fewer iterationd) An algorithm that allows multiplication to always
take less time to complete
e) answer b) and d)
Module 5 – Arithmetic Operations, Advanced Assembly
Moving on to DIVISION
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g
Dividend ÷ Divisor = Quotient + Remainder
Dividend = Quotient x Divisor + Remainder
1001 QuotientDivisor 1000 | 1001010 Dividend
- 1000____
10
101
1010
- 1000
10 Remainder
1001010 | 1000- 1000 1001
1010
-1000
10 (assume positive number for now)
Module 5 – Arithmetic Operations, Advanced Assembly
Division Algorithm
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Module 5 – Arithmetic Operations, Advanced Assembly
Division Algorithm
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Remainder = Dividend
For i = n-1 to 0
if Remainder – D ≥ 0
{
qi = 1
Remainder = Remainder – D
}
else
{qi = 0
}
D = D 2
Example:
011011012
000101012
12 divisorn D
Set remainder = 01101101
109 21
Module 5 – Arithmetic Operations, Advanced Assembly
Division Algorithm
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Divisor = 00010101,
D = 22 x divisor 2 shifts to the left!
1 shift 00101010
2 shifts 01010100
D = 01010100
12 divisorn D
Left shifting
Example:
01101101
00010101
Module 5 – Arithmetic Operations, Advanced Assembly
Division Algorithm
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i = 2
Remainder – D= 00011001 > 0
Remainder = Dividend
For i = n-1 to 0
if Remainder – D ≥ 0
{
qi = 1
Remainder = Remainder – D
}
else
{qi = 0
}
D = D 2
Example:
01101101
00010101
12 divisorn D
Remainder = 01101101
D= 01010100
q2= 1
Remainder = 00011001
D = 00101010 shift right
... keep going ...
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION cont.
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Hardware (divide-by-zero not represented):
Divisor moving down at each iteration
SUB/ADD
MSBinit: Remainder = dividend
slt test MSB (rem < divisor)
if 1 do nothingelse subtract
First initialized to 0
Divisor placein left half
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION ALGORITHM cont.
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• Step 1: Subtract divisorfrom remainder to see if
divisor < remainder• remainder = rem - div
• Comparison done used a ―set less than‖ instruction
• Step 2:
2a if result is +vediv<rem• put 1 in quotient.
2b if result is –vediv>rem
• put 0 in quotient
• restore to original value byadding divisor back.
• Step 3: Shift divisor
• Repeat 33 times• n + 1 steps needed
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION ALGORITHM
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Module 5 – Arithmetic Operations, Advanced Assembly
Division Example – Divide 0111 by 0010
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Division Example – Divide 01112 by 00102
Iteration Step Quotient Divisor Remainder
0 Initial Values 0000 0010 0000 0000 0111
1 Rem = Rem – Div
Rem<0, +Div, sll Q, Q=0
Shift Div right
0000
0000
0000
0010 0000
0010 0000
0001 0000
1110 0111
0000 01110000 0111
2 Rem = Rem – Div
Rem<0, +Div, sll Q, Q=0
Shift Div right
0000
0000
0000
0001 0000
0001 0000
0000 1000
1111 0111
0000 01110000 0111
Dividend ÷ Divisor = Quotient + Remainder
01112 ÷ 00102 = 00112 rem 00012
710 ÷ 210 = 310 rem 110
Module 5 – Arithmetic Operations, Advanced Assembly
Division Example – Divide 0111 by 0010
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Division Example – Divide 01112 by 00102
Iteration Step Quotient Divisor Remainder
3 Rem = Rem – Div
Rem<0, +Div, sll Q, Q=0
Shift Div right
0000
0000
0000
0000 1000
0000 10000000 0100
1111 11110000 01110000 0111
4 Rem = Rem – Div
Rem>0, sll Q, Q=1
Shift Div right
0000
0001
0001
0000 0100
0000 0100
0000 0010
0000 0011
0000 00110000 0011
5 Rem = Rem – Div
Rem>0, sll Q, Q=1
Shift Div right
0001
0011
0011
0000 0010
0000 0010
0000 0001
0000 0001
0000 00010000 0001
Dividend ÷ Divisor = Quotient + Remainder01112 ÷ 00102 = 00112 rem 00012
710 ÷ 210 = 310 rem 110
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION –EXAMPLEd d d
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Dividend ÷ Divisor = Quotient + Remainder01112 ÷ 00102 = 00112 rem 00012
710 ÷ 210 = 310 rem 110
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION - IMPROVEMENT
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105ECSE-221B At the end get
dividend
no shift
As for the multiplication, only a 32 bit ALU is needed toperform the successive subtractions.
Can speed things up by shifting the operands and thequotient simultaneously with the subtraction.
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION - IMPROVEMENT
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We can also eliminate the quotient register by putting theresult in the unused portions of the remainder register.
+ / - quotient
shift left Remainder/Quotient
and write a 0 or a 1shift right Remainder once at the end
Module 5 – Arithmetic Operations, Advanced Assembly
IMPROVED ALGORITHM
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quotient =1
quotient =0
Dividend÷Divisor=Quotient+Remainder
Module 5 – Arithmetic Operations, Advanced Assembly
IMPROVED ALGORITHM cont.
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We note that in the initial algorithm, we couldn‘t ever get a 1
in the quotient in the first iteration, otherwise would haven+1 quotient shifts lost of the 1.
In the improved algorithm, we start with a shifted remainder
and get 32 iterations.Have 1 extra shift of remainder at the end to shift back.
This is because of the architecture
two 4-bit numbers start with: 8 bits
- 4 bits ______________________
< 0!
rem register
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION EXAMPLE WITH NEW ALGORITHM
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DIVISION EXAMPLE WITH NEW ALGORITHM
Iter Step Divisor Remainder
0 Initial Values
Rem << 1
0010
0010
0000 0111
0000 1110
1 Rem = Rem – Div (left half)
Rem<0, Rem = Rem+Div, Rem <<1, Rem0=0
0010
0010
1110 1110
0001 1100
2 Rem = Rem – Div (left half)
Rem<0, Rem = Rem+Div, Rem <<1, Rem0=0
0010
0010
1111 1100
0011 1000
Dividend ÷ Divisor = Quotient + Remainder0111
2÷ 0010
2= 0011
2rem 0001
2710 ÷ 210 = 310 rem 110
Module 5 – Arithmetic Operations, Advanced Assembly
DIVISION EXAMPLE WITH NEW ALGORITHM
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DIVISION EXAMPLE WITH NEW ALGORITHM
Iter Step Divisor Remainder
3 Rem = Rem – Div (left half)Rem > 0, Rem <<1, Rem0=1
0010
0010
0001 1000
0011 0001
4 Rem = Rem – Div (left half)Rem > 0, Rem <<1, Rem0=1
--------------------------------------------------------
Rem >> 1 (left half)
00100010
0010
0001 00010010 0011
0001 0011
Dividend ÷ Divisor = Quotient + Remainder01112 ÷ 00102 = 00112 rem 00012
710 ÷ 210 = 310 rem 110
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED DIVISION
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So far we were dealing with unsigned numbers.
There is no simple Booth algorithm equivalent.
First record the sign of the divisor and the dividend.
Then, divide the absolute values, and negate the sign of quotientif the signs are different.
Rule: remainder has the same sign as the sign of the dividend.
Can check results from
Remainder = (Dividend – Quotient x Divisor)
Example:
+7 / +2 = +3 rem +1
1=(7 - 3×2)
-7 / +2 = -3 rem -1? rem = -7 - (-3×2)= -7 - (-6)= -1
or = -4 rem +1? good since -7-(-4×2)=-7-(-8)= +1,but not following rule
Module 5 – Arithmetic Operations, Advanced Assembly
SIGNED DIVISION cont.
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A signed division algorithm negates the quotient if:
the signs of the operands are opposite.
The sign of the nonzero remainder matches the dividend
Dividend = Quotient X Divisor + Remainder Example+ + + + +7/+2= +3 Rem +1
+ - - + +7/-2 = -3 Rem +1
- - + - -7/+2 = -3 Rem -1
- + - - -7/-2 = +3 Rem -1
Module 5 – Arithmetic Operations, Advanced Assembly
What is the sign of the quotient in -145 divided by -6?
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a) negative
b)positive
c) quotient is +ve if the remainder is -ve
d) quotient is +ve if the remainder is +ve
Module 5 – Arithmetic Operations, Advanced Assembly
INSTRUCTIONS
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The same hardware (i.e. a 32 bit ALU, 64-bit register) can be used toperform multiplication and division (add or sub, shift left or right).Only the control differs.
The MIPS machine calls Hi and Lo the respective halves of the 64-bitregister used to store the 64 bit product or the quotient/remainder.Additionally, to handle signed and unsigned integers, MIPS has two
flavours of the instructions.
mult $2, $3 # Hi,Lo = $2 x $3 (64 bits)
multu $2, $3 # same but unsigned (no overflow)div $2, $3 # Lo = $2/$3 (quotient),
# Hi = $2 mod $3 (remainder)
divu $2, $3 # same but unsigned (no overflow)
MIPS uses specific registers from which result can be called:
mfhi $1 # $1 = Hi (user to test formflo $1 # $1 = Lo overflow)
mflo: move from Lo (get copy of Lo)mfhi: move from Hi (get copy of Hi)
Module 5 – Arithmetic Operations, Advanced Assembly
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Module 5 – Arithmetic Operations, Advanced Assembly
Which number below is a normalized number?
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1.1010.1100×2-1
2.1.0101100×22
3.0.1010110×2-2
4.0.0101011×2-3
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT
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Real numbers include rationals and irrationals.
For an irrational, the number of digits is not finite.
3.14159265 ... (pi)For a rational, the number of digits needed to represent it may be
arbitrarily large.
0.000000001 = 1.0 x 10-9 (one nanosecond)
3.15575 x 109 (number of seconds in a century)
In either case we must settle for a fractional approximation.
A normalized number in ordinary scientific notation has just onenon zero digit to the left of the dot.
For example in scientific notation, there is one digit left of thepoint.
2.997925 x 108 m/s is the speed of light.
The same applies to binary. + - 1.ssssssss x 2eeee
Sign Fraction Exponent
Module 5 – Arithmetic Operations, Advanced Assembly
Floating point
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Floating point is the computer arithmetic supporting real numbers
The name ―floating point‖ comes from the fact that the binary
point is not fixed.
0.101 × 2-2 is the same number as 1.01 × 2-3
The difference is that 1.01 × 2-3 is normalized which facilitate
the hardware
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT cont.
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The bits allocated for the exponent part (E) and for thefraction/mantissa part (F) trade range against precision .
The MIPS format for floating-point number is:
The floating-point numbers are of the form:
X = (-1)S x (1 + Fraction) x 2E
Remember the hidden bit: IEEE 754 makes the leading 1-bit of normalized binary numbers implicit.
For clarity, the term significand is used in the book to representthe 24-bit number. The fraction refers to the 23-bit number.
1 bit 8 bits 23 bits
S Exponent Fraction
s eee eeee e sss ssss ssss ssss ssss ssss
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT cont.
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For single precision - range is about from 2.0×10-38 to 2.0×1038.
This is by no means infinite, so overflow (exponent is too large)and underflow (negative exponent is too large, i.e. the number
is too small to be represented) can occur.
To offer greater range and precision computer hardware support
double precision numbers (11 bit exponent and 52 bit fraction
making used of two 32-bit words).
Some computers use different encodings, but this one has become
the IEEE 754 Standard which is used by many computers.
In C, a single precision is a float and a double precision number is
a double.
Module 5 – Arithmetic Operations, Advanced Assembly
PROPERTIES
h h f h
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This representation can share some of its operations with integeroperations.
The sign bit is in the same place so sign test works the same way.
Sorting floating point numbers should be the same operation assorting fixed point numbers. It would work fine if the exponent
could not be negative. But if we used two‘s complementrepresentation, the scheme breaks down.
So, the idea is to use a biased notation (Module 1) to make themost negative exponent look like the smallest.
With an 8 bit exponent, the bias is to be 127 (1023 for 11 bits indouble precision).
Module 5 – Arithmetic Operations, Advanced Assembly
EXPONENT - BIASED NOTATION
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Small numbers as small as:
+/- 1.0000 0000 0000 0000 0000 000two x 2-126
Large numbers as large as:
+/- 1.1111 1111 1111 1111 1111 111two x 2+127
The range of exponent that
can be represented
In general: X = (-1)S ×(1+ Fraction) ×2(Exponent–bias)
0000 0000 -127 Reserved
0000 0001 -126
...
0111 1110 -1
0111 1111 0
1000 0000 +1
...
1111 1111 128 Reserved
Module 5 – Arithmetic Operations, Advanced Assembly
h f l
From Module 1 - Real Number Representation
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There are four special cases:
Programmers can verify those special cases and decide whatto do next.
Fraction= 0 Fraction is nonzero
Exponent = 0 ± 0De-normalized
number
Exponent = 255± ∞
(depending on sign
bit)
NaN(Not A Number)
Not a number (NaN) is an
un-representable value like 0/0or sqrt(-1) as a floating-point.
Module 5 – Arithmetic Operations, Advanced Assembly
FEATURES OF IEEE 754
R t ti f ( lt f di id b i t d f
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• Representation of +∞ or -∞ (result of divide by zero instead of an exception).
• Representation of the result of other illicit operations (such as0/0 or ∞-∞), printed as NaN (Not a Number).
• Denormalized forms. The exponent field is zero but thesignificand gains zeros after the dot (There is a gradualunderflow between the smallest normalized number and 0).
• Not all hardware implement those features, but at least theyspecify whether they are implemented or not.
Single precision Double precision Object represented
Exponent Fraction Exponent Fraction
0 0 0 0 0
0 nonzero 0 nonzero +/- Denormalized number
1 to 254 anything 1 to 2046 anything +/- Floating point number
255 0 2047 0 +/- Infinity
255 nonzero 2047 nonzero NaN
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING-POINT ADDITION
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Let‘s add numbers in scientific notation to illustrate how to
do additions for floating-points:9.999ten x 101 + 1.610ten x 10-1
Let‘s assume that we can only store 4 decimal digits of thesignificand and 2 decimal digits of the exponents.
There are four steps:
1. Adjust exponent to align the decimal point.
Shift the smallest number to the right until its exponent
matches the largest.
1.610 x 10-1 0.01610 x 101
0.016 x 101 (only 4 digits stored)
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING-POINT ADDITION cont.
2 Add significands 9 999
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2. Add significands. 9.999
+ 0.016
10.015 (x 101
)3. Normalize the sum. The result must have the form:
+- 1.ssssssss × 2eeee
Shift the significand and adjust the exponent appropriately.
1.0015 x 102
The biased exponent should be between 0 and 255.
If it is not, there is an underflow or overflow (programmer to
check).
4. Round. (more later)
1.002 x 102
If not Normalized, goto step 3. (for example if 9.9 10.0)
Module 5 – Arithmetic Operations, Advanced AssemblyBinary Floating-Point Addition
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The algorithm for binary follows our
previous example using decimals
Step 1. Adjust exponent
Step 2. Add the two significands
Step 3. Normalize
and check for overflow or underflow
Step 4. Round the significand and
normalize again if needed
Figure 3.15 (P&H p.252)
Module 5 – Arithmetic Operations, Advanced Assembly
HARDWARE TO SUPPORT FP ADDITION
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Whichexponent is larger?
add significands
Exponent
Difference controlthree multiplexors:MUX 1 – chooses bigger exponentMUX 2 – selects smaller significand
MUX 3 – selects bigger significand
MUX 1 MUX 2 MUX 3
Significand
Module 5 – Arithmetic Operations, Advanced Assembly
At what stage in the floating-point (FP) addition dowe need normalize the number?
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1. Before adding the two significands2. After the rounding process only
3. After adding the two significands and after
the rounding process4. Only at the end once we‘ve completed the
FP addition
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT MULTIPLICATION
T f ll th t ill lti l 1 110 1010 9 200 10 5
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To follow the steps, we will multiply 1.110ten x 1010 x 9.200ten x10-5
1. Add exponents.
New exponent = 10 + (-5) = 5
Since they are biased, we would add the bias twice, so the result‘s biased
exponent is: E1 + E2 – bias
Check: 10 + 127 137 and -5 + 127 122,
(10 + 127) + (-5 + 127) – 127 = 5 + 127
2. Multiply significands. (unsigned)
1.110
x 9.200
00000000
2220
9990
10.212000 keep 3 digits to the right of dec. pt: 10.212 x 105
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT MULTIPLICATION
3 N li P d t
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3. Normalize Product.
Here normalization will be achieved by shifting right and
incrementing the exponent.
Check for the exponent that may cause an overflow if
capacity is exceeded. Note that an underflow can occur if
both operands have large negative exponents.
1.0212 x 106 (Check if exponent is too big)
4. Round.
If not Normalized, goto step 3.
Rounded to four digits 1.021 x 106
5. Sign.
Determine the sign of the product from the signs of the
operands.
Module 5 – Arithmetic Operations, Advanced AssemblyBinary Floating-Point Multiplication
S dd b d
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Step 1. Add biased exponents
Step 2. Multiply the significandsStep 3. Normalize and check for
overflow or underflow
Step 4. Round
Step 5. Set the signs
As it can be seen, there is a lot in
common between the hardware for
addition and multiplication
(rounding and normalizing).
Module 5 – Arithmetic Operations, Advanced Assembly
In the floating-point multiplication, how do we knowthat there is an underflow?
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1. The unbiased exponent is greater than 1272. The unbiased exponent is smaller than -126
3. The significand bits are all zeros
4. The unbiased exponent is smaller than -127
5. The significand bits are all ones
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING-POINT INSTRUCTIONS
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MIPS supports (like many machines) special registers for
storing floating point numbers, named $f0, $f1, ..., $f31.MIPS supports single and double precision operations and
corresponding loads and stores.
For double precision, 32 bit registers are used in pairs.To simplify, only even numbered registers can be used for
single precision operations.
The operands are always stored in even numbered registerswhich are used in pairs.
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT INSTRUCTIONS cont.
Fl ti i t dditi i l d d bl i i
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Floating-point addition single and double precision:
add.s $f2, $f4, $f6 # $f2 = $f4 + $f6
add.d $f2, $f4, $f6 # $f2 = $f4 + $f6
double $f2 is really a pair of single precision registers $f2 & $f3
Floating-point subtraction single and double precision:
sub.s $f2, $f4, $f6 # $f2 = $f4 - $f6
sub.d $f2, $f4, $f6 # $f2 = $f4 - $f6
Floating-point multiplication single and double precision:
mul.s $f2, $f4, $f6 # $f2 = $f4 * $f6
mul.d $f2, $f4, $f6 # $f2 = $f4 * $f6
Floating-point division single and double precision:
div.s $f2, $f4, $f6 # $f2 = $f4 / $f6
div.d $f2, $f4, $f6 # $f2 = $f4 / $f6
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT INSTRUCTIONS cont.
Loads and stores of single and double precision numbers are all
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Loads and stores of single and double precision numbers are all
pseudo-instructions involving transfers between registers specific to
floating-points. So there are separate load and store instructions.
MIPS code for loading 2 single precision numbers from memory, add
them, then store sum:
lwc1 $f4, 100($s2) # $f4 = Memory[$s2+100]
# load 32 bit fp number# into $f4
lwc1 $f6, 200($s2) # $f6 = Memory[$s2+200]
# load 32 bit fp number
# into $f6
add.s $f2, $f4, $f6 # $f2 = $f4 + $f6swc1 $f2, 500($s2) # Memory[$s2 + 500] = $f2
# store 32 bit fp number
# from Rf2
Module 5 – Arithmetic Operations, Advanced Assembly
FLOATING POINT INSTRUCTIONS cont.
Oth i t ti ifi t fl ti i t
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Other instructions specific to floating-points:
Floating-point comparison – less than (lt)
c.lt.s $f2, $f4 # if ($f2 < $f4) cond = 1 else# cond = 0
c.lt.d $f2, $f4 # if ($f2 < $f4) cond = 1 else
# cond = 0
also have equal (c.eq.s, c.eq.d), not equal (c.neq.s, c.neq.d),greater than (c.gt,s, c.gt,d).
Floating-point branch true:
bc1t 25 # if (cond == 1) goto PC+4+100
Floating-point branch false: bclf 25 # if (cond == 0) goto PC+4+100
Module 5 – Arithmetic Operations, Advanced Assembly
ACCURATE ARITHMETIC
Th b f l b b t 0 d 1 i i fi it b t
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The number of real numbers between, say 0 and 1, is infinite, but
the number of floating point numbers is finite.
There are less than 253 number representation (double).
Floating-point numbers are normally approximations for a number
they cannot really be represented
Rounding (finding the closest approximation) can be done in
several ways.
• Always round up
• Always round down
• Truncate
• Round to the nearest even (when exactly halfway)
Module 5 – Arithmetic Operations, Advanced Assembly
ACCURATE ARITHMETIC cont.
Every intermediate result in floating point addition and
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Every intermediate result in floating point addition andmultiplication has to be truncated.
To accurately round a number, the IEEE 754 standard keeps 2extra bits (guard and round ) during the intermediatecalculations.
Here is an example in decimal: 2.56×100 + 2.34×102
The numbers have 3 significant decimal digits but we keep two moreduring calculations.
2.3400 ×102
+ 0.0256 ×102
2.3656 ×102
Now we round the two added digits, 00—49 down and 50—99 up.
Result: 2.37x102
Module 5 – Arithmetic Operations, Advanced Assembly
ACCURATE ARITHMETIC cont.
Without the extra digits, the result is: 2.36x102
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Without the extra digits, the result is: 2.36x10
2.34 x102
+ 0.02 x102
2.36 x102
The answer if off by 1 bit in the last digit.
Note that one extra digit would have been sufficient, butmultiplication requires two:
Binary product may have one leading 0 bit. As the number getsnormalized, the product is shifted left by one bit.
Accuracy in floating point is measured in terms of the number of bits in error in the LSBs of the significand.
Number of units in the last place, or ulp.
The IEEE standard guarantees better than one-half ulp.
Module 5 – Arithmetic Operations, Advanced AssemblySUMMARY OF MODULE 5
R i f b t ti i t
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• Review of number presentation in computer
• Construction of Arithmetic and Logic Unit (ALU)
• Addition using the ALU
• Subtraction using the ALU
• Hardware implementations for multiplication• Improved hardware
• Booth algorithm for signed numbers
• Hardware implementations for division
• Improved hardware