Modeling and Simulation of Strained Silicon MOSFETs for Nanoscale Applications
A dissertation submitted in partial fulfillment of
the requirement for the degree of Bachelor of Technology
by
Vivek Venkataraman (2002193) Susheel Nawal (2002185)
Under the Supervision of Prof. M. Jagadesh Kumar
to the Department of Electrical Engineering Indian Institute of Technology Delhi
May 2006
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What we have learnt from this endeavour....
“Stress IS proportional to strain !!!”
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CERTIFICATE
This is to certify that the thesis entitled “Modeling and Simulation of Strained Silicon
MOSFETs for Nanoscale Applications” being submitted by Vivek Venkataraman and
Susheel Nawal to the Indian Institute of Technology, Delhi, in the Electrical Engineering
Department is a bona fide work carried out by them under my supervision and guidance. The
research reports and the results presented in this thesis have not been submitted in parts or in
full to any other University or Institute.
Date : 1 May 2006 Dr. M. Jagadesh Kumar
Professor Department of Electrical Engineering
Indian Institute of Technology New Delhi - 110016
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Publications from this thesis
M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal,"Comprehensive Approach
to Modeling Threshold Voltage of Nanoscale Strained Silicon SOI MOSFETs," Journal of
Computational Electronics, Vol.6, No.4, pp.439-444, December 2007.
Vivek Venkataraman, Susheel Nawal and M. Jagadesh Kumar, "Compact Analytical
Threshold Voltage Model of Nanoscale Fully-depleted Strained-silicon on Silicon-
germanium-on-insulator (SGOI) MOSFETs," IEEE Trans. on Electron Devices, Vol.54,
pp.554-562, March 2007.
M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal, "Impact of Strain or Ge
content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs," IEEE
Trans. on Device and Materials Reliability, Vol.7, pp.181-187, March 2007.
M. Jagadesh Kumar, Vivek Venkataraman and Susheel Nawal, "A Simple Analytical
Threshold Voltage Model of Nanoscale Fully Depleted Single-Layer Strained-Silicon-on-
Insulator (SSOI) MOSFETs," IEEE Trans. on Electron Devices, Vol.53, pp.2500-2506,
October 2006.
Susheel Nawal, Vivek Venkataraman and M. Jagadesh Kumar, "Compact Modeling of
Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs," Technical Proceedings of
the 2006 NSTI Nanotechnology Conference and Trade Show, Volume 3, pp. 854-857,
May 7-11,2006, Boston, Massachusetts, U.S.A.
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ACKNOWLEDGEMENT
We wish to express our sincere gratitude to our supervisor Dr. M. Jagadesh Kumar
for his invaluable guidance and advice during every stage of this project. We are greatly
indebted to him for his constant encouragement and support, without which it would not have
been possible for us to pursue this research.
Special thanks are due to Prof. G. S. Visweswaran for his insightful comments and
valuable suggestions during our project presentations. We also thank Prof. B.
Bhaumik for her comments and questions related to our work, which have helped us
immensely to improve our understanding.
We are grateful to Mr. Chandrashekhar for allowing us to use the laboratory facilities
at all points of time.
We would also like to express our sincere thanks to Mr. Ali A. Orouji and
Mr. B. Subrahmaniam for helpful discussions.
Vivek Venkataraman Susheel Nawal
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Abstract
For nanoscale CMOS applications, strained-silicon devices have been receiving
considerable attention owing to their potential for achieving higher performance and
compatibility with conventional silicon processing. However, no compact models are
available in the literature modeling their threshold voltage or current characteristics, taking
into account short channel effects. The aim of our project is to study various strained silicon
devices and develop analytical models for the same.
In this work, novel analytical models for the threshold voltage of nanoscale bulk
strained-Si/SiGe MOSFETs, Fully Depleted Strained Silicon on Insulator (FD-SSOI)
MOSFETs, and Fully Depleted strained-Si on Silicon-Germanium-on-Insulator (SGOI)
MOSFETs are developed by solving the 2-D Poisson equation. Our models include the
effects of the strain (in terms of equivalent Ge mole fraction), short-channel length,
source/drain junction depths, substrate (body) doping, strained silicon thin film thickness,
gate work function and other device parameters. Our models correctly predict a decrease in
threshold voltage with decreasing channel length and increasing strain in the silicon thin film
i.e. with increasing Ge concentration. An analytical model for the output current
characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs is also developed. We
demonstrate significant current enhancement due to strain, even in short channel devices,
attributed to the velocity overshoot effect. The accuracy of the results obtained using our
analytical models, is verified using two-dimensional device simulations.
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TABLE OF CONTENTS
Figure Captions...................................................................................................8
Chapter I............................................................................................................11
Introduction.......................................................................................................11
Chapter II ..........................................................................................................14
Effect of Strain ..................................................................................................14 2.1 Introduction...........................................................................................................................................14 2.2 Effect on Silicon Band Structure...........................................................................................................14 2.3 Effect on MOSFET parameters.............................................................................................................15
Chapter III.........................................................................................................17
Strained-Si / SiGe MOSFET............................................................................17 3.1 Introduction...........................................................................................................................................17 3.2 Threshold Voltage Model .....................................................................................................................18 3.3 Calculation of Equivalent Depletion Region Depth (xd) .......................................................................23 3.4 Results and Discussion..........................................................................................................................25 3.5 Concluding Remarks.............................................................................................................................29
Chapter IV.........................................................................................................30
Fully Depleted Strained Silicon On Insulator MOSFET..............................30 4.1 Introduction...........................................................................................................................................30 4.2 Threshold Voltage Model .....................................................................................................................30 4.3 Results and Discussion..........................................................................................................................34 4.4 Concluding Remarks.............................................................................................................................36
Chapter V ..........................................................................................................38
Fully Depleted Strained Silicon On SiGe-on-Insulator MOSFET...............38 5.1 Introduction...........................................................................................................................................38 5.2 Threshold Voltage Model .....................................................................................................................38 5.3 Results and Discussion..........................................................................................................................44 5.4 Concluding Remarks.............................................................................................................................50
Chapter VI.........................................................................................................51
Analytical Drain Current Model for Strained-Si/SiGe MOSFETs .............51 6.1 Introduction...........................................................................................................................................51 6.2 Model for output characteristics of Strained-Si/SiGe nMOSFET.........................................................51 6.3 Results and Discussion..........................................................................................................................56 6.4 Concluding Remarks.............................................................................................................................61
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Chapter VII .......................................................................................................62
Conclusions........................................................................................................62 Future Work:...............................................................................................................................................63
References..........................................................................................................64 Figure Captions
Figure 1 Effect of strain on Si and SiGe band structure (Ref. [15]).
Figure 2 Cross-sectional view of the strained-Si/SiGe MOSFET showing the depletion
regions.
Figure 3 Box approximation of the depletion region for solving 2-D Poisson equation.
Figure 4 Depletion region of the strained-Si/SiGe MOSFET for 2 dlL x≥
Figure 5 Depletion region of the strained-Si/SiGe MOSFET for 2 dlL x≤
Figure 6 Threshold voltage versus strain x (Ge content in SiGe substrate) for channel lengths
(L) of 50 nm and 30 nm. The parameters used are: VDS = 50 mV, Vsub = 0 V,
NA = 1 x 1018 cm-3, ts-Si = 15 nm, rj = 50 nm, tf = 2 nm, Mφ = 4.35 eV.
Figure 7 Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV,
Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 15 nm, rj = 50 nm, tf = 2 nm, Mφ = 4.35 eV.
Figure 8 Threshold voltage versus strain x (Ge content) for body dopings NA = 1 x 1018 cm-3
and NA = 1 x 1017 cm-3, and corresponding gate work functions Mφ = 4.35 eV (n+
poly) and Mφ = 4.71 eV (Mid-gap metal) respectively. The parameters used are: VDS
= 50 mV, Vsub = 0 V, L = 50 nm, ts-Si = 15 nm, rj = 50 nm, tf = 2 nm.
Figure 9 Threshold voltage versus strain x (Ge content in SiGe substrate) for S/D junction
depths rj = 50 nm and rj = 80 nm. The parameters used are: VDS = 50 mV, Vsub = 0 V,
L = 50 nm, NA = 1 x 1018 cm-3 , ts-Si = 15 nm, tf = 2 nm, Mφ = 4.35 eV.
Figure 10 Threshold voltage versus strained-Si film thickness ts-Si. The parameters used are:
VDS = 50 mV, Vsub = 0 V, NA = 1 x 1018 cm-3, L = 50 nm, rj = 50 nm, tf = 2 nm,
Mφ = 4.35 eV.
Figure 11 Cross-sectional view of the FD-SSOI MOSFET.
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Figure 12 Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV,
Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 25 nm, tf = 2 nm, tb = 100 nm, Mφ = 4.35 eV.
Figure 13 Threshold voltage versus strain x (equivalent Ge content) for strained-Si film
thicknesses ts-Si = 15 nm and ts-Si = 10 nm. The parameters used are: VDS = 50 mV,
Vsub = 0 V, L = 50 nm, NA = 1 x 1018 cm-3, tf = 2 nm, tb = 100 nm, Mφ = 4.35 eV.
Figure 14 Threshold voltage versus strained-Si film thickness ts-Si. The parameters used are:
VDS = 50 mV, Vsub = 0 V, NA = 1 x 1018 cm-3, L = 50 nm, tf = 2 nm, tb = 100 nm,
Mφ = 4.35 eV.
Figure 15 Cross-sectional view of the FD-strained-Si on SGOI MOSFET.
Figure 16 Comparison between the actual surface potential (solving the fourth order differential
equation) and approximate solution (neglecting the fourth order term). The
parameters used are: x = 0.1, VGS = 0.15 V, VDS = 50 mV, Vsub = 0 V, L = 50 nm,
NA = 1 x 1018 cm-3, tf = 2 nm, tb = 100 nm, Mφ = 4.35 eV, ts-Si = 5 nm, tSiGe = 10 nm.
Figure 17 Threshold voltage versus strain x (Ge content in the SiGe film) for different
strained-Si and SiGe film thicknesses. The parameters used are: VDS = 50 mV,
Vsub = 0 V, L = 50 nm, NA = 1 x 1018 cm-3, tf = 2 nm, tb = 100 nm, Mφ = 4.35 eV.
Figure 18 Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV,
Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm,
Mφ = 4.35 eV (Maximum Transconductance Method)
Figure 19 Threshold voltage versus channel length L. The parameters used are: VDS = 50 mV,
Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb = 100 nm,
Mφ = 4.35 eV ( Ninv = NA Method)
Figure 20 Threshold voltage versus strain x (Ge content in the SiGe film) for gate work
functions Mφ = 4.35 eV (n+ poly) and Mφ = 4.71 eV (Mid-gap metal) and
corresponding body dopings NA = 1 x 1018 cm-3 and NA = 1 x 1017 cm-3 respectively.
The parameters used are: VDS = 50 mV, Vsub = 0 V, L = 50 nm, ts-Si = 5 nm,
tSiGe = 5 nm, tf = 2 nm, tb = 100 nm.
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Figure 21 Threshold voltage versus SiGe film thickness tSiGe. The parameters used are:
VDS = 50 mV, Vsub = 0 V, NA = 1 x 1018 cm-3, L = 50 nm, ts-Si = 10 nm, tf = 2 nm,
tb = 100 nm, Mφ = 4.35 eV.
Figure 22 Saturation threshold voltage versus channel length L. The parameters used are:
VDS = 0.5 V, Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm, tb =
100 nm, Mφ = 4.35 eV.
Figure 23 Drain Induced Barrier Lowering (DIBL) versus channel length L. The parameters
used are: x = 0.2, Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 5 nm, tSiGe = 10 nm, tf = 2 nm,
tb = 100 nm, Mφ = 4.35 eV.
Figure 24 Output Current versus drain voltage for different values of strain x (Ge content in the
SiGe film). The parameters used are: VGS = 0.75 V, Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si
= 15 nm, tox = 2 nm, Mφ = 4.35 eV, L = 50 nm
Figure 25 Normalized current characteristics for different values of strain x (Ge content in the
SiGe film). The parameters used are: VGS = 0.75 V, Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si
= 15 nm, tox = 2 nm, Mφ = 4.35 eV, L = 50 nm
Figure 26 Output Characteristics for unstrained MOSFET (x = 0). The parameters used are:
Vsub = 0 V, NA = 1 x 1018 cm-3, ts-Si = 15 nm, tox = 2 nm, Mφ = 4.35 eV, wτ = 0.1 ps,
L = 50 nm.
Figure 27 Output Characteristics for strain x = 0.1. The parameters used are: Vsub = 0 V,
NA = 1 x 1018 cm-3, ts-Si =15 nm, tox = 4 nm, Mφ = 4.35 eV, wτ = 0.15 ps, L = 50 nm.
Figure 28 Output Characteristics for strain x = 0.2. The parameters used are: Vsub = 0 V,
NA = 1 x 1018 cm-3, ts-Si = 15 nm, tox =5 nm, Mφ = 4.35 eV, wτ = 0.2 ps, L = 50 nm.
Figure 29 Output Characteristics for strain x = 0.2. The parameters used are: Vsub = 0 V,
NA = 1 x 1018 cm-3, ts-Si = 15 nm, tox =2 nm, Mφ = 4.71 eV, wτ = 0.2 ps, L = 50 nm.
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Chapter I
Introduction Silicon-based MOSFETs have reached remarkable levels of performance through
device scaling. However, it is becoming increasingly hard to improve device performance
through traditional scaling methods. Device dimensions are approaching their scaling limit
giving rise to undesirable effects like gate leakage current, short channel effects etc.
Consequently, innovative device structures and materials are actively being investigated to
boost performance. Strained-silicon devices have been receiving considerable attention
owing to their potential for achieving higher performance due to improved carrier-transport
properties, i.e., mobility and high-field velocity [1], and compatibility with conventional
silicon processing [2]-[4].
The conventional method of producing strained Si is pseudomorphic Si epitaxial
growth on relaxed SiGe alloys. By increasing the Ge content of the relaxed SiGe alloy, the
amount of biaxial strain and therefore the magnitude of the mobility enhancement can be
enhanced. However, as the Ge content is increased, the critical thickness (the thickness to
which the strained silicon can be grown without inducing misfit dislocations to alleviate the
strain) is reduced. Strained silicon-on-insulator (SOI) MOSFETs have been proposed for
applications in high-speed CMOS devices as they combine the carrier transport advantages of
strained-Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-
film SOI [15,23]. Thin body SOI with a fully depleted layer has additional advantages, such
as steep sub-threshold slope, low junction leakage current, maximized channel mobility and
reduced threshold-voltage fluctuation due to low impurity concentration.
A number of different structures have been suggested for strained SOI devices
employing various fabrication techniques [24-26]. Among these, the strained-Si on SGOI
substrate is expected to have a high strain in the Si layer because of the underlying SiGe
layer with high Ge content, resulting in better performance [27]. Consequently, these devices
have been receiving considerable attention. Strained silicon-on-insulator (SSOI) is a new
SiGe-free material system that combines the carrier transport advantages of strained Si with
the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. The
strained silicon-on-insulator (SSOI) structure is less susceptible to misfit dislocation-induced
12
leakage current, while maintaining increased carrier mobility [21]. Tremendous improvement
in static and dynamic CMOS circuit performance has been demonstrated using strained SOI
as well as strained-Si/SiGe MOSFETs [5].
Accurate modeling of nanoscale strained-Si devices along the lines of conventional
nanoscale Si MOSFETs [6-9] thus becomes necessary for future device and circuit design.
There is no comprehensive analytical model available for the threshold voltage of SSOI or
strained-Si on SGOI MOSFETs, while earlier works on the threshold voltage of strained-
Si/SiGe MOSFETs [10]-[11] have concentrated on the band offsets due to strain and
modified the long channel threshold voltage model. One-dimensional Poisson equation
solution has also been considered [12]-[13], however for short channel devices, two-
dimensional effects such as the influence of source/drain depletion widths becomes
important.
The aim of this work is, therefore, to develop, for the first time, models for the
threshold voltage of short channel (sub 100 nm) nanoscale strained-Si/SiGe, SSOI and
strained-Si on SGOI MOSFETs by solving the 2-D Poisson equation in the strained-Si thin
film and analyzing the dependence of threshold voltage on various device parameters. Also,
an analytical model for the output current characteristics (Ids – Vds) is developed for
nanoscale strained-Si/SiGe MOSFETs to examine the effect of strain on current drive
enhancement.
Our models thus provide an efficient tool for design and characterization of high
performance SSOI, strained-Si on SGOI and strained-Si/SiGe nanoscale MOSFETs including
the short channel effects. The effect of varying device parameters can easily be investigated
using the analytical models presented in this work. The model results are verified by
comparing them with the 2-D simulation results obtained using MEDICI [14].
The dissertation is divided into seven chapters and its outline is described as given below:
Chapter I: Introduction.
Concepts and previous works related to Strained Silicon devices, its advantages &
disadvantages, objectives of the project and outline of the thesis.
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Chapter II: Effect of Strain
This chapter analyzes the effect of strain due to lattice mismatch between Si and SiGe on
various properties of silicon. The impact on various MOSFET parameters like flat band
voltage, built in voltage etc. has also been discussed.
Chapter III: Strained-Si / SiGe MOSFET
In this chapter we have derived the threshold voltage model of Strained-Si / SiGe MOSFET.
The model has been compared with 2D simulations and the results with varying device
parameters have been discussed.
Chapter IV: Fully Depleted Strained Silicon On Insulator MOSFET
In this chapter we have derived the threshold voltage model of FD-SSOI MOSFET. The
model has been compared with 2D simulations and the results with varying device
parameters have been discussed.
Chapter V: Fully Depleted Strained Silicon On Silicon-Germanium-on-Insulator
MOSFET
In this chapter we have derived the threshold voltage model of FD-strained-Si on SGOI
MOSFET. The model has been compared with 2D simulations and the results with varying
device parameters have been discussed.
Chapter VI: Analytical Drain Current Model for Strained-Si/SiGe MOSFETs
In this chapter we have developed the model for output current characteristics of Strained-Si /
SiGe MOSFETs. The model has been compared with 2D simulations and the enhancement in
current due to strain is discussed.
Chapter VII: Conclusions and Future Work.
14
Chapter II
Effect of Strain 2.1 Introduction
Silicon under biaxial tension, caused due to lattice mismatch with SiGe leads to
enhanced carrier mobility, providing improved MOSFET performance compared to standard
bulk and silicon-on-insulator (SOI) substrates [10,11]. In strained Si, the silicon 6-fold
degenerate valley in the conduction band is split into 2-fold and 4-fold degenerate valleys.
Similar splitting is observed between the light and heavy hole bands in the valence band. The
band with lower energy is preferentially occupied resulting in the reduction of the carrier
effective mass and intervalley scattering rates [22].
2.2 Effect on Silicon Band Structure
Gate
EC
Strained-Si Unstrained Si1-xGex
EV
Si
x : Ge content
Work-function
Vacuum level
0.57x (eV)
Eg,Si - 0.4x (eV)0.467x (eV)
Figure 1- Cross-sectional view of the strained-Si/SiGe MOSFET [15]
Due to strain, the electron affinity of silicon increases and the bandgap decreases
(Fig. 1). Also the effective mass of carriers decreases. The effect of strain on Si band
structure can be modeled as [10,11,15]:
xE SisC 57.0)( =Δ − , xE Sisg 4.0)( =Δ − , xmm
VNN
VSish
SihT
SisV
SiVT 075.0lnln
2/3
*,
*,
,
, ≈⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟
⎟⎠
⎞⎜⎜⎝
⎛
−−
(1)
15
where x is the Ge mole fraction in Si1-xGex substrate, ( )C s SiE −Δ is the decrease in electron
affinity of silicon due to strain, ( )g s SiE −Δ is the decrease in bandgap of silicon due to strain,
TV is the thermal voltage, ,V SiN and ,V s SiN − are the density of states in the valence band in
normal and strained silicon respectively, *,h Sim and *
,h s Sim − are the hole density of states
(DOS) effective masses in normal and strained silicon, respectively. The band structure
parameters for relaxed Si1-xGex substrate can also be estimated as [14]-[16]:
( ) 0.467g SiGeE xΔ = , ( ) 19 3, 0.6 1.04(1 ) 10V SiGeN x x cm−= + − × , 11.8 4.2SiGe xε = + (2)
where ( )g SiGeEΔ is the decrease in bandgap of Si1-xGex from that of Si, ,V SiGeN is the density
of states in the valence band in relaxed Si1-xGex, and SiGeε is the permittivity of Si1-xGex.
2.3 Effect on MOSFET parameters
The flat-band voltage of a MOSFET is thus modified due to strain as [11]
fFBSifFBSisfFB VVV ,,, )()( Δ+=− (3)
where
SiMSifFBV φφ −=)( , , ⎟⎟⎠
⎞⎜⎜⎝
⎛−
Δ+
Δ−=Δ
−
−−
SisV
SiVT
SisgSisCfFB N
NV
qE
qEV
,
,, ln
)()( ,
SiFSigSi
Si qE
q ,,
2φχφ ++= , ⎟
⎟⎠
⎞⎜⎜⎝
⎛=
Sii
ATSiF n
NV,
, lnφ .
In the above relations, Mφ is the gate work function, Siφ is the unstrained Si work function,
,F Siφ is the Fermi potential in unstrained Si, Siχ is the electron affinity in unstrained Si, ,g SiE
is the bandgap in unstrained Si, q is the electronic charge, NA is the body doping
concentration and ,i Sin is the intrinsic carrier concentration in unstrained Si.
The built-in voltage across the source-body and drain-body junctions in the strained-
Si thin film is also affected by strain as
SisbiSibiSisbi VVV −− Δ+= )(,, (4)
where SiFSig
Sibi qE
V ,,
, 2φ+= , ⎟
⎟⎠
⎞⎜⎜⎝
⎛+
Δ−=Δ
−
−−
SisV
SiVT
SisgSisbi N
NV
qE
V,
,ln)(
)( .
16
The built-in voltage across the source-body and drain-body junctions in the relaxed
Si1-xGex substrate can be written as
, , ( )bi SiGe bi Si bi SiGeV V V= + Δ (5)
where SiFSig
Sibi qE
V ,,
, 2φ+= , ,
,
( )( ) lng SiGe V Si
bi SiGe TV SiGe
E NV V
q N⎛ ⎞− Δ
Δ = + ⎜ ⎟⎜ ⎟⎝ ⎠
.
In the next three chapters, the above effects have been incorporated to derive an
analytical threshold voltage model for Strained Si/SiGe, FD-SSOI and FD-strained-Si on
SGOI MOSFETs.
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Chapter III
Strained-Si / SiGe MOSFET 3.1 Introduction
Epitaxial growth of Si on relaxed SiGe alloys creates strained-Si layers due to the
larger atomic spacing of Ge. However the film thickness cannot exceed few tens of
nanometers, otherwise misfit dislocations will creep in. Fig. 2 shows the cross-section of a
short channel strained-Si/SiGe n-MOSFET with depletion regions also indicated. The
depletion region under the gate for short channel MOSFETs is not uniform and is affected by
the lateral source-body and drain-body depletion widths (xdl ) and their respective charges, as
shown in Fig.2. The exact solution of the 2-D Poisson equation for such a case is too
complicated and would most probably require numerical methods and iterations. To obtain a
meaningful analytical solution, Fig. 2 is transformed to a box type approximation of the
depletion region as shown in Fig. 3 with a uniform charge density NA,eff and a uniform depth
of depletion thickness xd.
VDtf
xdl
Si1-xGex
VS=0
L
VSub =0
xdl
NAn+ n+ rj
VG
Gate
s-Si ts-siGate oxide
xdv
Figure 2- Cross-sectional view of the strained-Si/SiGe MOSFET
18
The gate-S/D charge sharing [17] and source-body/drain-body built-in potential barrier
lowering [18] due to overlap of the lateral source-body and drain-body depletion regions (xdl
in Fig. 2) become important as the channel length reduces.
3.2 Threshold Voltage Model
To incorporate the short channel effects, the effective doping NA,eff is defined taking
into account only the effective charge under the influence of the gate [17] as
,21 1 1 jdv
A eff Aj
rxN Nr L
⎡ ⎤⎛ ⎞⎛ ⎞⎢ ⎥⎜ ⎟= − + −⎜ ⎟⎜ ⎟⎢ ⎥⎜ ⎟⎝ ⎠⎝ ⎠⎣ ⎦
(6)
where 2 ( )SiGe th sub
dvA
VxqN
ε φ −= , ,2th F Si s Siφ φ φ −= + Δ , ⎟
⎟⎠
⎞⎜⎜⎝
⎛+
Δ−=Δ
−
−−
SisV
SiVT
SisgSis N
NV
qE
,
,ln)(
φ ,
xdv is the vertical depletion region depth due to gate bias only, thφ is the minimum surface
potential required for inversion [11], rj is the source/drain junction depth, L is the channel or
gate length, and Vsub is the substrate bias. thφ is that value of surface potential at which the
inversion electron charge density in the strained-Si device is the same as that in unstrained-Si
at threshold [11] (i.e. 0s Siφ −Δ = for unstrained-Si). The above approach is analogous to the
one used in [13], where a voltage-doping transformation [19] is used to define an effective
doping to extend the long channel threshold voltage model to the short channel case.
To complete the box approximation, an average vertical depletion region depth (xd in Fig. 3)
is calculated using simple geometry (see section III b.) from Fig. 2 as
( ) ( )42 2dl j dl dl dv
d
x r x L x xx
L
π+ + −≅ for 2 dlL x≥ (7)
22
212 4
dld j dl
xLx r xL
θ≅ + − + for 2 dlL x≤ (8)
where 1sin2 dl
Lx
θ − ⎛ ⎞= ⎜ ⎟
⎝ ⎠, and
,2 SiGe bi SiGedl
A
Vx
qNε
=
is the lateral source-body and drain-body depletion region width. It can be seen that in the
case of large channel length, i.e. L >> 2xdl, equation (7) reduces to xd ≈ xdv. Also, for
19
extremely short channel lengths i.e. L << 2xdl, equation (8) reduces to xd ≈ rj+ xdl. These
results are along expected lines. For L = 2xdl, equations (7) and (8) yield the same value for
xd.
tf
VS=0
VSub=0
x=0 x=L
Si1-xGex
VD
L
VG
rj NA,eff
φ 2(x,y')
φ1(x,y)
y' = 0 tSiGe n+n+
Gate oxideGate
s-Si xd
ts-siy = 0
Figure 3- Box approximation of the depletion region
For the simplified structure in Fig. 3, the 2-D Poisson equation in the strained silicon
thin-film, before the onset of strong inversion can be written as [20]:
2 2
,1 12 2
( , ) ( , ) A eff
Si
qNd x y d x ydx dyφ φ
ε+ = for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (9)
where Siε is the dielectric constant of silicon, and s Sit − is the strained-Si thin film thickness.
The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 3) and
the depletion region in the SiGe substrate below (y’-direction in Fig. 3) can be approximated
by a parabolic function, as done in [20] as:
21 11 12( , ) ( ) ( ) ( )sx y x c x y c x yφ φ= + + for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (10)
22 21 22( , ') ( ) ' ( ) 'subx y V c x y c x yφ = + + for 0 x L≤ ≤ , 0 ' SiGey t≤ ≤ (11)
where SiGe d s Sit x t −= − , ( )S xφ is the surface potential and the coefficients ( )11c x , ( )12c x ,
( )21c x and ( )22c x are functions of x only.
The Poisson equation is solved using the following boundary conditions:
20
1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.
1
0
( ) '( , ) ox s GS
Si fy
x Vd x ydy t
ε φφε=
⎛ ⎞⎡ ⎤ −= ⎜ ⎟⎢ ⎥ ⎜ ⎟⎣ ⎦ ⎝ ⎠
(12)
where oxε is the dielectric constant of the gate oxide, ft is the gate oxide thickness,
SisfFBGSGS VVV −−= )(' , , and GSV is the gate-to-source bias voltage.
2. Electric flux/field at the end of the depletion region (y’=0 in Fig. 3) in the SiGe substrate
is zero.
2
' 0
( , ') 0' y
d x ydy
φ
=
⎡ ⎤=⎢ ⎥
⎣ ⎦ (13)
3. Potential at the interface of strained-Si thin film and SiGe substrate is continuous.
( ) ( )1 2, ,s Si SiGex t x tφ φ− = (14)
4. Electric flux (displacement) at the interface of strained-Si thin film and SiGe substrate is
continuous.
1 2
'
( , ) ( , ')'
s Si SiGe
SiGe
Siy t y t
d x y d x ydy dy
εφ φε
−= =
⎡ ⎤ ⎡ ⎤= −⎢ ⎥ ⎢ ⎥
⎣ ⎦ ⎣ ⎦ (15)
5. The surface potential at the source end is
1 ,(0,0) (0)s sub bi s SiV Vφ φ −= = + (16)
6. The surface potential at the drain end is
1 ,( ,0) ( )s sub bi s Si DSL L V V Vφ φ −= = + + (17)
where DSV is the drain-to-source bias voltage.
The coefficients ( )11c x , ( )12c x , ( )21c x and ( )22c x in equations (10) and (11) can be
deduced from the boundary conditions (12) – (15). Substituting the values of ( )11c x and
( )12c x in (10), we obtain the expression for 1( , )x yφ . Then, substituting 1( , )x yφ in (9) and
putting y=0, we obtain
βαφφ=− )()(
2
2
xdx
xds
s (18)
where
21
( )
( )2
2
2 1
1
f f
SiGe Si
Si
SiGe
C CC C
Cs Si Ct
α−
+ +=
+ ,
( )( ) ( )
2
2 2
2 ' 21 1
f f
SiGe Si
Si Si
SiGe SiGe
C CGS C C subA
C CSi s Si s SiC C
V VqNt t
βε
− −
+= − −
+ +
where oxf
f
Ctε
= , SiSi
s Si
Ctε
−
= , SiGeSiGe
SiGe
Ctε
= .
The above equation is a simple second-order non-homogenous differential equation with
constant coefficients which has a solution of the form
σλλφ −−+= )exp()exp()( xBxAxs (19)
where αλ = and αβσ = . Now using boundary conditions (16) – (17) to solve for A and
B, we obtain
( ) ( ) ( )( ) ( ), , exp
exp1 exp 2
sub bi s Si DS sub bi s SiV V V V V LA L
Lσ σ λ
λλ
− −⎧ ⎫+ + + − + + −⎪ ⎪= −⎨ ⎬− −⎪ ⎪⎩ ⎭
( ) ( ) ( )( )
, , exp1 exp 2
sub bi s Si sub bi s Si DSV V V V V LB
Lσ σ λ
λ− −⎧ ⎫+ + − + + + −⎪ ⎪= ⎨ ⎬
− −⎪ ⎪⎩ ⎭.
The minimum surface potential can be calculated from (19) by putting
( ) 0sd xdxφ
= . (20)
The minimum surface potential is
σφ −= ABs 2min, (21)
The threshold voltage thV is that value of the gate voltage GSV at which a conducting
channel is induced under the gate oxide at the surface of a MOSFET. In a conventional
unstrained silicon MOSFET, the threshold voltage is taken to be that value of gate-source
voltage for which ,min ,2S F Siφ φ= , where ,F Siφ is the difference between the extrinsic Fermi
level in the bulk region and the intrinsic Fermi level [20]. At this potential the inversion
electron concentration becomes equal to the body doping. For the strained-Si MOSFETs, the
condition for threshold is modified as [11]:
thSisSiFs φφφφ =Δ+= −,min, 2 (22)
where ⎟⎟⎠
⎞⎜⎜⎝
⎛+
Δ−=Δ
−
−−
SisV
SiVT
SisgSis N
NV
qE
,
,ln)(
φ .
22
and thφ is that value of surface potential at which the inversion electron charge density in the
strained-Si device is the same as that in unstrained-Si at threshold [11]. So the threshold
voltage is defined as the value of GSV at which the minimum surface potential ,minSφ equals
thφ . Hence we can determine the value of threshold voltage by substituting (21) into (22)
and solving for GSV , as
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛ −+−=
ξξ φφφ
24 2
211 VVV
kVth (23)
where, ( ) ( )22cosh 2 sinhL Lξ λ λ= − −
( )( ) ( ) ( ) ( )( )21 1 21 exp 2 2 sinh 1 expbi th biV V L u L V Lφ λ φ λ λ= − + − − − −
( ) ( )2 22 1 2 sinhbi bi thV V V u Lφ φ λ= − −
( ) ( )( )1 , 1 expbi sub bi s Si DSV V V u L Vλ−= + − − − +
( ) ( )( )2 , exp 1bi sub bi s Si DSV V V u L Vλ−= + − − −
( )( )
( )2
,
2 2
( )1 1
f f
SiGe Si
f f f f
SiGe Si SiGe Si
C CC Csub A
FB f s SiC C C CSiC C C C
V qNu Vε α −
+= − −
+ + + +
( )( )
2
2
1 f f
Si SiG e
f f
Si SiG e
C CC C
C CC C
k+ +
=+
.
23
3.3 Calculation of Equivalent Depletion Region Depth (xd)
VDtf
xdl
Si1-xGex
VS=0
L
VSub =0
xdl
n+ n+ rj
VG
Gate
s-Si ts-siGate oxide
xdv2 21 3
Figure 4- Depletion region of the strained-Si/SiGe MOSFET for 2 dlL x≥
The average vertical depletion region depth (xd in Fig. 3) in equations (7) and (8) is
calculated using the constraint that the total depletion region area under the gate should
remain the same as before after transformation to the box approximation.
For 2 dlL x≥ , the total depletion region area (DA) under the gate is calculated from
Fig. 4 as DA = (Area of Region 1) + (Area of Region 2) + (Area of Region 3). Thus,
( ) ( ) ( )2 24 42j dl dl dl dv j dl dlDA r x x L x x r x xπ π≅ + + − + + (A1)
In the box approximation of Fig. 3, the total depletion region area (DA) under the gate is
dDA x L= (A2)
Equating (A1) and (A2), we get the expression for average vertical depletion region depth xd
as
( ) ( )42 2dl j dl dl dv
d
x r x L x xx
L
π+ + −≅ for 2 dlL x≥ (A3)
Equation (A3) is the same as equation (7).
24
tf
VS=0 Gate
s-SiGate oxide
xdl
ts-si
VD
n+
θ xdl
VSub =0
rjn+
Si1-xGex
L
L/2
1 2
VG
Figure 5- Depletion region of the strained-Si/SiGe MOSFET for 2 dlL x≤
Similarly, for 2 dlL x≤ , the total depletion region area (DA) under the gate is
calculated from Fig. 5 as DA = (Area of Region 1) + (Area of Region 2) = 2*(Area of
Region 1 or 2). Thus DA can be approximated as,
22 212
2 2 4 2j dl dlL LDA r x xθ⎡ ⎤⎛ ⎞
⎢ ⎥≅ + − +⎜ ⎟⎜ ⎟⎢ ⎥⎝ ⎠⎣ ⎦ (A4)
where 1sin2 dl
Lx
θ − ⎛ ⎞= ⎜ ⎟
⎝ ⎠.
Again, in the box approximation of Fig. 3, the total depletion region area (DA) under the gate
is given by equation (A2). Comparing equating (A4) and (A2), we get the expression for
average vertical depletion region depth xd as
2221
2 4dl
d j dlxLx r xL
θ≅ + − + for 2 dlL x≤ (A5)
Equation (A5) is the same as equation (8).
25
3.4 Results and Discussion
To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was
used to simulate the threshold voltage of strained-Si/SiGe MOSFETs for various device
parameters and the results were compared with the values predicted by the model. The
threshold voltage is extracted from 2-D simulation using the commonly used maximum
transconductance method. The parameters used in our simulation are given in Table 1.
0 0.1 0.2 0.3 0.4-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Model Medici
Equivalent Ge Content Strain , x
L = 50 nm
L = 30 nm
Thre
shol
d Vo
ltage
(vol
ts)
Figure 6- Threshold voltage versus strain x
Fig. 6 shows the variation of threshold voltage with change in strain i.e. Ge mole
fraction of SiGe substrate, for gate lengths of 50 nm and 30 nm. The threshold voltage
obtained from the model tracks the simulation values very well. It is evident that there is a
significant fall in threshold voltage with increasing strain, and the decrease in thV is almost
linear. thV rolls off drastically with strain x, even going negative for Ge content of 30-40 %.
The threshold voltage decreases with increasing Ge content x because of decrease in flat-
band voltage (equation (3)), decrease in source-body/drain-body built-in potential barrier
(equation (4)), and earlier onset of inversion due to decrease in thφ (equation (22)). Also, it
26
can be seen from the figure that thV for L=50 nm is noticeably greater than that for L=30 nm,
indicating the on-set of the short-channel effects.
50 100 150 200-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Model Medici
Gate Length , Lg (nm)
x=0
x=0.2
x=0.4
Thre
shol
d Vo
ltage
(vol
ts)
Figure 7- Threshold voltage versus channel length L
Fig. 7 shows the variation of threshold voltage with gate length for different values of
Ge mole fraction x in the SiGe substrate. It is observed that short channel effects become
prevalent below 70-80 nm gate length, as predicted above, and is marked by the sharp
decrease in thV value. The gate-S/D charge sharing and source-body/drain-body built-in
potential barrier lowering due to overlap of the lateral source-body and drain-body depletion
regions (xdl in Fig. 2) become significant for such short channel lengths. Also, the threshold
voltage is lower for higher strain for the same channel length, thus confirming the results
from Fig. 6. The thV values from the analytical model are in close proximity with the
simulation results, with a maximum error of approximately 20-30 mV.
27
0 0.1 0.2 0.3 0.4-0.1
0
0.1
0.2
0.3
0.4
0.5Model Medici
Equivalent Ge Content Strain , x
Thre
shol
d Vo
ltage
(vol
ts)
N = 1 10 cm Mid-gap metal gate
- 3
N = 1 10 cmn+ poly gate
- 3
17 X A
A 18
X
Figure 8- Threshold voltage versus strain x for different body dopings
In Fig. 8, the variation of threshold voltage with change in strain (Ge mole fraction x
in SiGe substrate) for a gate length of 50 nm is plotted for two different body doping
concentrations and corresponding gate work functions. It is evident from the figure that the
threshold voltage of the strained-Si/SiGe MOSFETs can be controlled by using an
appropriate gate material with a suitable work function Mφ . A higher work function (eg. Mid-
gap metal with Mφ =4.71 eV) increases the flat-band voltage (equation (3)) thereby affording
a lower doping concentration and higher strain levels for the same thV , as compared to a
normal n+ polysilicon gate ( Mφ =4.35 eV). Thus, by using a suitable gate material, we can
achieve higher mobility of charge carriers due to larger strain and consequently higher
transconductance without affecting thV . There is again a close match between the analytical
results and the 2-D simulation results [14].
In Fig. 9, the variation of threshold voltage with change in strain (Ge mole fraction x
in SiGe substrate) for a gate length of 50 nm is plotted for two different source/drain junction
depths. It is observed that thV also reduces slightly with increase in source/drain junction
depth, for the same gate length. This is because of the lower effective doping ( equation (6) )
28
0 0.1 0.2 0.3 0.4-0.1
0
0.1
0.2
0.3
0.4
Model Medici
Equivalent Ge Content Strain , x
Thre
shol
d Vo
ltage
(vol
ts)
S/D junction depth, r = 50 nm
S/D junction depth, r = 80 nm j
j
Figure 9- Threshold voltage versus strain x for various S/D junction depths
due to increased gate-S/D sharing and overlap of the lateral source-body and drain-body
depletion regions. Thus, a lower S/D junction depth is desirable for better performance.
8 10 12 14 16
-0.1
0
0.1
0.2
0.3
0.4
0.5Model Medici
Thre
shol
d Vo
ltage
(vol
ts)
Strained-Si thin film thickness, t (nm)
x=0
x=0.2
x=0.4
s-Si
Figure 10-Threshold voltage versus strained-Si film thickness ts-Si
29
The variation of threshold with the thickness of the strained-Si thin film is plotted in
Fig. 10. As can be seen from the figure, there is no discernible change in threshold voltage
with change in strained-Si film thickness from 10 nm -15 nm. This suggests that one can
allow small variations and tolerances in the fabrication process without affecting the thV too
much. The table below gives various device parameters used in the simulation.
Table 1: Device parameters used in the simulation (s-Si/SiGe) Parameter Value
Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3
Body doping, NA 1018 cm-3, 1017 cm-3 Gate Oxide Thickness, tf 2.0 nm Work function of gate material, Mφ 4.35 eV (n+ poly Si),
4.71 eV (Mid-Gap metal)
Strained-Silicon film thickness, ts-Si 10 nm - 15 nm Source/drain junction depth, rj 50 nm, 80 nm Substrate bias, Vsub 0 Volts (Gnd) Drain bias, VDS 0.05 Volts (50 mV)
3.5 Concluding Remarks Strained Si/SiGe MOSFETs offer better performance than conventional MOSFETs
due to its higher electron and hole mobility. By increasing the Ge content of the relaxed SiGe
alloy, the amount of biaxial strain and therefore the magnitude of the mobility can be
enhanced. However, as the Ge content is increased the threshold voltage rolls off as seen
from the model developed, and also the critical thickness (the thickness to which the strained
silicon can be grown without inducing misfit dislocations to alleviate the strain) is reduced
[21]. Therefore an alternate device structure has been proposed which combines the carrier
transport advantages of strained Si with the reduced parasitic capacitance and improved
MOSFET scalability of thin-film SOI i.e. Fully Depleted Strained silicon MOSFET. This has
been studied in the next chapter.
30
Chapter IV
Fully Depleted Strained Silicon On Insulator MOSFET 4.1 Introduction FD-SSOI is a Germanium free device hence it is less susceptible to misfit dislocation-
induced leakage current compared to conventional strained Si/SiGe, while maintaining
increased carrier mobility. Thus, strained Si thickness constraints for MOSFET fabrication
are eased, allowing the successful fabrication of devices on strained Si films above the
critical thickness. At the same time, SSOI provides the advantages of the SOI structure
including reduced parasitic capacitance and improved electrostatics. Fig. 11 shows the cross-
section of a FD-SSOI MOSFET. This chapter deals with the derivation of an analytical
threshold voltage model for the same.
4.2 Threshold Voltage Model The 2-D Poisson equation in the strained silicon thin-film, before the onset of strong
inversion can be written as [20]:
Si
AqNdy
yxddx
yxdε
φφ=+ 2
2
2
2 ),(),( for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (24)
where Siε is the dielectric constant of silicon, and s Sit − is the strained-Si thin film thickness.
The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 11)
can be approximated by a parabolic function, as done in [20] as:
221 )()()(),( yxcyxcxyx s ++= φφ for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (25)
where ( )S xφ is the surface potential and the coefficients ( )1c x and ( )2c x are functions of x
only.
The Poisson equation is solved using the following boundary conditions:
1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.
0
( ) '( , ) ox s GS
Si fy
x Vd x ydy t
ε φφε=
⎛ ⎞⎡ ⎤ −= ⎜ ⎟⎢ ⎥ ⎜ ⎟⎣ ⎦ ⎝ ⎠
(26)
where oxε is the dielectric constant of the gate oxide, ft is the gate oxide thickness,
31
SisfFBGSGS VVV −−= )(' , , and GSV is the gate-to-source bias voltage.
tf
VS=0
VSub=0
VD
VG
Gate
NA n+n+
φ(x,y)
Gate oxide
Substrate
ts-si
tb
x=0L
x=L
Buried oxide
s-Si y = 0
y
Figure 11- Cross-sectional view of the FD-SSOI MOSFET.
2. Electric flux at the interface of buried oxide and the back-channel is continuous.
' ( , )( , )
s Si
ox sub s Si
Si by t
V x td x ydy t
ε φφε
−
−
=
⎛ ⎞⎡ ⎤ −= ⎜ ⎟⎢ ⎥
⎣ ⎦ ⎝ ⎠ (27)
where bt is the buried oxide thickness, SisbFBsubsub VVV −−= )(' , , subV is the substrate bias,
bFBSibFBSisbFB VVV ,,, )()( Δ+=− is the back-channel flat-band voltage, ,( )FB b Si sub SiV φ φ= − ,
subφ is the substrate work function and
⎟⎟⎠
⎞⎜⎜⎝
⎛−
Δ+
Δ−=Δ
−
−−
SisV
SiVT
SisgSisCbFB N
NV
qE
qEV
,
,, ln
)()( .
3. The surface potential at the source end is
,(0,0) (0)s bi s SiVφ φ −= = (28)
4. The surface potential at the drain end is
,( , 0) ( )s bi s Si DSL L V Vφ φ −= = + (29)
where DSV is the drain-to-source bias voltage.
32
The coefficients ( )1c x and ( )2c x in equation (25) can be deduced from the boundary
conditions (26) – (27). Substituting the values of ( )1c x and ( )2c x in (25), we obtain the
expression for ( , )x yφ . Then, substituting ( , )x yφ in (24) and putting y=0, we obtain
βαφφ=− )()(
2
2
xdx
xds
s (30)
where
( )
( )22
2 1
1
f f
b Si
Si
b
C CC C
Cs Si Ct
α−
+ +=
+ ,
( )( ) ( )2 22 2
2 ' 2 '1 1
f f
b Si
Si Si
b b
C CGS C C subA
C CSi s Si s SiC C
V VqNt t
βε
− −
+= − −
+ +
where oxf
f
Ctε
= , SiSi
s Si
Ctε
−
= , oxb
b
Ctε
= .
The above equation is a simple second-order non-homogenous differential equation with
constant coefficients which has a solution of the form
σλλφ −−+= )exp()exp()( xBxAxs (31)
where αλ = and αβσ = . Now using boundary conditions (28) – (29) to solve for A and
B, we obtain
( ) ( ) ( )( ) ( ), , exp
exp1 exp 2
bi s Si DS bi s SiV V V LA L
Lσ σ λ
λλ
− −⎧ ⎫+ + − + −⎪ ⎪= −⎨ ⎬− −⎪ ⎪⎩ ⎭
( ) ( ) ( )( )
, , exp1 exp 2
bi s Si bi s Si DSV V V LB
Lσ σ λ
λ− −⎧ ⎫+ − + + −⎪ ⎪= ⎨ ⎬
− −⎪ ⎪⎩ ⎭.
The minimum surface potential can be calculated from (31) by putting
( ) 0sd xdxφ
= . (32)
The minimum surface potential is
σφ −= ABs 2min, (33)
The threshold voltage thV is that value of the gate voltage GSV at which a conducting
channel is induced under the gate oxide at the surface of SOI MOSFET. In a fully depleted
thin-film SOI, it is desirable that the front channel turns on before the back channel.
Therefore, in a conventional unstrained silicon MOSFET, the threshold voltage is taken to be
33
that value of gate-source voltage for which ,min ,2S F Siφ φ= , where ,F Siφ is the difference
between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level [20]. For the
strained-Si MOSFETs, the condition for threshold is modified as [11]:
thSisSiFs φφφφ =Δ+= −,min, 2 (34)
where ⎟⎟⎠
⎞⎜⎜⎝
⎛+
Δ−=Δ
−
−−
SisV
SiVT
SisgSis N
NV
qE
,
,ln)(
φ .
and thφ is that value of surface potential at which the inversion electron charge density in the
strained-Si device is the same as that in unstrained-Si at threshold [11]. So the threshold
voltage is defined as the value of GSV at which the minimum surface potential ,minSφ
equals thφ . Hence we can determine the value of threshold voltage by substituting (33) into
(34) and solving for GSV , as
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛ −+−=
ξξ φφφ
24 2
211 VVV
kVth (35)
where
( ) ( )22cosh 2 sinhL Lξ λ λ= − −
( )( ) ( ) ( ) ( )( )21 1 21 exp 2 2 sinh 1 expbi th biV V L u L V Lφ λ φ λ λ= − + − − − −
( ) ( )2 22 1 2 sinhbi bi thV V V u Lφ φ λ= − −
( ) ( )( )1 , 1 expbi bi s Si DSV V u L Vλ−= − − − +
( ) ( )( )2 , exp 1bi bi s Si DSV V u L Vλ−= − − −
( )( )
( ) ,' ( )
1 1
f f
b Si
f f f f
b Si b Si
C CC Csub A
FB f s SiC C C CSiC C C C
V qNu Vε α −
+= − −
+ + + +
( )( )
1 f f
b Si
f f
b Si
C CC C
C CC C
k+ +
=+
.
34
4.3 Results and Discussion
To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was
used to simulate the threshold voltage of FD-SSOI MOSFETs for various device parameters
and compared with the values predicted by the model. The threshold voltage is extracted
from 2-D simulation using the commonly used maximum transconductance method. The
parameters used in our simulation are given in Table 2.
50 100 150 200
-0.1
0
0.1
0.2
0.3
0.4
0.5Model Medici
x=0
x=0.2
x=0.4
Gate Length , Lg (nm)
Thre
shol
d Vo
ltage
(vol
ts)
Figure 12- Threshold voltage versus channel length L
Fig. 12 shows the variation of threshold voltage with gate length for different values
of effective Ge mole fraction, and strained silicon thickness of 25 nm. It is observed that
short channel effects become prevalent below 70-80 nm gate length and is marked by the
sharp decrease in Vth value. The gate-S/D charge sharing and source-body/drain-body built-in
potential barrier lowering [18] due to overlap of the lateral source-body and drain-body
depletion regions become significant for such short channel lengths.
Also, threshold voltage is lower for higher strain at the same gate length. This result
can be confirmed from Fig. 13, which shows the variation of threshold voltage with change
in strain for a gate length of 50 nm. It is evident that there is a significant fall in threshold
voltage with increasing strain, and the decrease in thV is almost linear. thV rolls off drastically
35
with strain x, even going negative for Ge content of 0.3-0.4. The threshold voltage decreases
with increasing Ge content x because of decrease in flat-band voltage (equation (3)), decrease
in source-body/drain-body built-in potential barrier (equation (4)), and earlier onset of
inversion due to decrease in thφ (equation (34)).
0 0.1 0.2 0.3 0.4
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25 Model Medici
Thre
shol
d Vo
ltage
(vol
ts)
Equivalent Ge Content Strain , x
tsi=10 nm
tsi=15 nm
Figure 13- Threshold voltage versus strain x for different strained-Si film thicknesses ts-Si
Fig. 14 shows the variation of threshold voltage with thickness of strained Si thin
film. It can be seen that Vth also reduces with decreasing thickness of strained Si thin film.
This is because of the decrease in total depletion charge under the gate in the strained-Si thin
film and increased gate-S/D sharing leading to early onset of inversion. Thus, a higher
strained-Si film thickness is desirable for better performance; however it should not be much
larger than the critical thickness to avoid misfit dislocations. The threshold voltage obtained
from the model tracks the simulation values very well.
36
10 15 20 25-0.1
0
0.1
0.2
0.3
0.4
Strained Silicon Thin Film Thickness, tsi (nm)
Thre
shol
d Vo
ltage
(vol
ts) Model
Medici
x=0
x=0.2
x=0.4
Figure 14- Threshold voltage versus strained-Si film thickness ts-Si.
Table 2: Device parameters used in the simulation (FD-SSOI) Parameter Value
Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3
Body doping, NA 1018 cm-3 Gate Oxide Thickness, tf 2.0 nm Work function of gate material, Mφ 4.35 eV (n+ poly Si) Strained-Silicon film thickness, ts-Si 10 nm – 25 nm Buried Oxide Thickness, tb 100 nm Substrate bias, Vsub 0 Volts (Gnd) Drain bias, VDS 0.05 Volts (50 mV)
4.4 Concluding Remarks
SSOI devices are free of the high off-state leakage current which can plague bulk
strained Si/SiGe devices beyond the critical thickness. SSOI devices possess immunity to this
misfit dislocation related leakage mechanism because the dislocation cores at the strained
Si/SiGe interface are eliminated during the SSOI wafer fabrication process, opening a path to
higher strain and associated performance levels. However, as the strain is increased the
37
threshold voltage rolls off, as seen from the model developed above. Therefore, the threshold
voltage needs to be controlled through methods like varying gate work function. Another
type of strained SOI device, the strained-Si on SGOI substrate is expected to have a high
strain in Si layers using SiGe layers (with high Ge content) directly on Insulator, resulting in
better performance. This has been studied in the next chapter.
38
Chapter V
Fully Depleted Strained Silicon On SiGe-on-Insulator MOSFET 5.1 Introduction
The strained-Si on SGOI MOSFET also provides the advantages of the SOI structure
including reduced parasitic capacitance and improved electrostatics. Fig. 15 shows the cross-
section of a FD-strained-Si on SGOI MOSFET. This chapter deals with the derivation of an
analytical threshold voltage model for the same. SGOI substrates can be fabricated by the
combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation
(ITOX) techniques [28-30]. For a Fully Depleted structure, a strained-Si thin film is directly
grown on this thin SGOI substrate. By varying the Ge mole fraction in SGOI layer, the
amount of strain in the thin silicon layer on top can be controlled.
5.2 Threshold Voltage Model
Before the onset of strong inversion, the two-dimensional Poisson equation in the
strained silicon thin-film of a FD-strained-Si on SGOI MOSFET can be written as [20]:
2 2
1 12 2
( , ) ( , ) A
Si
d x y d x y qNdx dyφ φ
ε+ = for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (36)
where Siε is the dielectric constant of silicon, and s Sit − is the strained-Si thin film thickness.
Similarly, the Poisson equation in the Si1-xGex layer on insulator below, for full depletion,
can be written as
2 2
2 22 2
( , ') ( , ')'
A
SiGe
d x y d x y qNdx dyφ φ
ε+ = for 0 x L≤ ≤ , 0 ' SiGey t≤ ≤ (37)
where SiGeε is the dielectric constant of Si1-xGex, and SiGet is the its layer thickness.
39
tf
VS=0
VG
Gate
n+
Gate oxideVD
n+
VSub=0
Substrate
φ1(x,y) y = 0
φ 2(x,y')
ts-sis-Si
y' = 0x=0
tb
Lx=L
Buried oxide
Si1-xGex
NA tSiGe
Figure 15- Cross-sectional view of the FD-strained-Si on SGOI MOSFET.
The potential profile in the vertical direction in the strained-Si film (y-direction in Fig. 15)
and the Si1-xGex layer below (y’-direction in Fig. 15) can be approximated by a parabolic
function, as done in [20] as:
21 11 12( , ) ( ) ( ) ( )sx y x c x y c x yφ φ= + + for 0 x L≤ ≤ , 0 s Siy t −≤ ≤ (38)
22 21 22( , ') ( ) ( ) ' ( ) 'bx y x c x y c x yφ φ= + + for 0 x L≤ ≤ , 0 ' SiGey t≤ ≤ (39)
where ( )S xφ is the front channel surface potential at the gate-oxide/strained-Si interface,
( )b xφ is the back channel potential at the SiGe/Buried-Oxide interface, and the coefficients
( )11c x , ( )12c x , ( )21c x and ( )22c x are functions of x only. The Poisson equations (36) and (37)
can be solved using the following boundary conditions:
1. Electric flux (displacement) at the gate-oxide/strained-Si film interface is continuous.
1
0
( ) '( , ) ox s GS
Si fy
x Vd x ydy t
ε φφε=
⎛ ⎞⎡ ⎤ −= ⎜ ⎟⎢ ⎥ ⎜ ⎟⎣ ⎦ ⎝ ⎠
(40)
where oxε is the dielectric constant of the gate oxide, ft is the gate oxide thickness,
SisfFBGSGS VVV −−= )(' , , and GSV is the gate-to-source bias voltage.
40
2. Electric flux at the interface of buried oxide and the SiGe back-channel is continuous.
2
' 0
( ) '( , ')'
ox b sub
SiGe by
x Vd x ydy t
ε φφε=
⎛ ⎞⎡ ⎤ −= ⎜ ⎟⎢ ⎥
⎣ ⎦ ⎝ ⎠ (41)
where bt is the buried oxide thickness, ,' ( )sub sub FB b SiGeV V V= − , subV is the substrate bias,
, , , ,( ) ( )FB b SiGe FB b Si FB b SiGeV V V= +Δ is the back-channel flat-band voltage, ,( )FB b Si sub SiV φ φ= − ,
subφ is the substrate work function and
,, ,
,
( )lng SiGe V Si
FB b SiGe TV SiGe
E NV V
q N⎛ ⎞Δ
Δ = − ⎜ ⎟⎜ ⎟⎝ ⎠
.
3. Potential at the interface of strained-Si thin film and SiGe layer is continuous.
( ) ( )1 2, ,s Si SiGex t x tφ φ− = (42)
4. Electric flux (displacement) at the interface of strained-Si thin film and SiGe layer is
continuous.
1 2
'
( , ) ( , ')'
s Si SiGe
SiGe
Siy t y t
d x y d x ydy dy
εφ φε
−= =
⎡ ⎤ ⎡ ⎤= −⎢ ⎥ ⎢ ⎥
⎣ ⎦ ⎣ ⎦ (43)
5. The surface potential at the source end is
1 ,(0,0) (0)s bi s SiVφ φ −= = (44)
6. The surface potential at the drain end is
1 ,( ,0) ( )s bi s Si DSL L V Vφ φ −= = + (45)
where DSV is the drain-to-source bias voltage.
The coefficients ( )11c x , ( )12c x , ( )21c x and ( )22c x in equations (38) and (39) can be
deduced from the boundary conditions (40) – (43). Thus, we obtain the expressions for
1( , )x yφ and 2 ( , ')x yφ . Substituting 1( , )x yφ in (36) and putting y=0, we obtain
2
1 1 12
( ) 2 ( ) 2 ( )ss b
d x b x a x cdxφ φ φ− + = (46)
where
( )1 2
22
b SiGe
s Si Si SiGe
C Cat C C−
+=
+ ,
( ) ( )( )1 2
2SiGe f SiGe Si f
s Si Si SiGe
C C C C Cb
t C C−
+ +=
+ ,
41
( )( )
( )1 2
2 1 ' 'f SiGe Si GS b subA
Si s Si Si SiGe
C C C V C VqNct C Cε −
⎛ ⎞+ −= −⎜ ⎟⎜ ⎟+⎝ ⎠
and oxf
f
Ctε
= , SiSi
s Si
Ctε
−
= , SiGeSiGe
SiGe
Ctε
= , oxb
b
Ctε
= .
Similarly, substituting 2 ( , ')x yφ in (37) and putting y’=0, we obtain
2
2 2 22
( ) 2 ( ) 2 ( )bb s
d x a x b x cdxφ φ φ− + = (47)
where
( ) ( )( )2 2
2Si b Si SiGe b
SiGe Si SiGe
C C C C Ca
t C C+ +
=+
, ( )2 2
22
f Si
SiGe Si SiGe
C Cb
t C C+
=+
,
( )( )
( )2 2
2 1 ' 'b Si SiGe sub f GSA
SiGe SiGe Si SiGe
C C C V C VqNct C Cε
⎛ ⎞+ −= − ⎜ ⎟⎜ ⎟+⎝ ⎠
Eliminating ( )b xφ from equations (46) and (47), we obtain
( ) ( ) ( )4 2
2 1 2 1 1 2 2 1 1 24 2
( ) ( )2 2 4 ( ) 2s ss
d x d xa b a b a b x a c a cdx dxφ φ φ− + + − = − + (48)
The exact solution to the above fourth-order differential equation would be too complicated
for a simple compact model that we are striving to obtain, and thus to gain any physical
insight. Noting that the surface potential variation ( )s xφ , across the front channel from the
source to the drain, is quite smooth and does not vary rapidly (especially for gate voltage
close to the threshold voltage of MOSFET), we neglect its fourth derivative with respect to
the other terms. This approximation is quite valid as we can see from Fig.16. Thus equation
(48) reduces to
2
2
( ) ( )ss
d x xdxφ αφ β− = (49)
where
2 1 1 2
2 1
2 a b a ba b
α⎛ ⎞−
= ⎜ ⎟+⎝ ⎠, 2 1 1 2
2 1
a c a ca b
β⎛ ⎞+
= ⎜ ⎟+⎝ ⎠
42
Figure 16 – Surface potential variation along the channel
Thus equation (48) reduces to
2
2
( ) ( )ss
d x xdxφ αφ β− = (49)
where
2 1 1 2
2 1
2 a b a ba b
α⎛ ⎞−
= ⎜ ⎟+⎝ ⎠, 2 1 1 2
2 1
a c a ca b
β⎛ ⎞+
= ⎜ ⎟+⎝ ⎠
The solution for equation (49), which is a simple second-order non-homogenous differential
equation with constant coefficients, can be written as:
σλλφ −−+= )exp()exp()( xBxAxs (50)
where αλ = and αβσ = . Now using boundary conditions (44) – (45) to solve for A and
B, we obtain
( ) ( ) ( )( ) ( ), , exp
exp1 exp 2
bi s Si DS bi s SiV V V LA L
Lσ σ λ
λλ
− −⎧ ⎫+ + − + −⎪ ⎪= −⎨ ⎬− −⎪ ⎪⎩ ⎭
( ) ( ) ( )( )
, , exp1 exp 2
bi s Si bi s Si DSV V V LB
Lσ σ λ
λ− −⎧ ⎫+ − + + −⎪ ⎪= ⎨ ⎬
− −⎪ ⎪⎩ ⎭.
10 20 30 40 50
0.88
0.90
0.92
0.94
0.96
0.98
Distance from source (nm)
Vgs = 0.15V actual surface potential
approximate surface potential
Pot
entia
l ,V
olts
43
In order to obtain a model for the threshold voltage, we need to find the minimum
surface potential from (50) by putting
( ) 0sd xdxφ
= (51)
This will give us the minimum surface potential as:
σφ −= ABs 2min, (52)
The threshold voltage thV is that value of the gate voltage GSV at which a conducting
channel is induced under the gate oxide at the surface of SOI MOSFET. In a fully depleted
thin-film SOI, it is desirable that the front channel turns on before the back channel.
Therefore, in a conventional unstrained silicon MOSFET, the threshold voltage is taken to be
that value of gate-source voltage for which ,min ,2S F Siφ φ= , where ,F Siφ is the difference
between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level [20]. For the
strained silicon on SGOI MOSFET, the condition for threshold is modified as [11]:
thSisSiFs φφφφ =Δ+= −,min, 2 (53)
where ⎟⎟⎠
⎞⎜⎜⎝
⎛+
Δ−=Δ
−
−−
SisV
SiVT
SisgSis N
NV
qE
,
,ln)(
φ ,
and thφ is that value of surface potential at which the inversion electron charge density in the
strained-Si device is the same as that in unstrained-Si at threshold. Therefore, the threshold
voltage is defined as the value of GSV at which the minimum surface potential ,minSφ
equals thφ . Hence we can determine the value of threshold voltage by substituting (52) into
(53) and solving for GSV as:
2
1 1 2412th
V V VV
kφ φ φξ
ξ
⎛ ⎞− + −⎜ ⎟=⎜ ⎟⎝ ⎠
(54)
where
( ) ( )22cosh 2 sinhL Lξ λ λ= − −
( )( ) ( ) ( ) ( )( )21 1 21 exp 2 2 sinh 1 expbi th biV V L u L V Lφ λ φ λ λ= − + − − − −
( ) ( )2 22 1 2 sinhbi bi thV V V u Lφ φ λ= − −
44
( ) ( )( )1 , 1 expbi bi s Si DSV V u L Vλ−= − − − +
( ) ( )( )2 , exp 1bi bi s Si DSV V u L Vλ−= − − −
( )( )( )( ) ( ) ( )
1 2 2 1,2 2
2 1 1 2 2 1 1 2
2 1' ( )2 2 2
b Si SiGesub b AFB f s Si
SiGe Si SiGe s Si Si SiGe Si SiGe
a C C CV a C qN a au k Va b a b t C C t C C a b a b ε ε −
−
⎡ ⎤+ ⎛ ⎞= − − + −⎢ ⎥ ⎜ ⎟− + + −⎢ ⎥ ⎝ ⎠⎣ ⎦
( )( )( )( ) ( )
2 12 2
2 1 1 2
2 112 2
f SiGe Si f
s Si Si SiGe SiGe Si SiGe
a C C C a Ck
a b a b t C C t C C−
⎡ ⎤+= −⎢ ⎥
− + +⎢ ⎥⎣ ⎦
5.3 Results and Discussion
To verify the proposed analytical model, the 2-D device simulator MEDICI [14] was
used to simulate the threshold voltage of FD-strained-Si on SGOI MOSFETs for various
device parameters and compared with the values predicted by the model. The threshold
voltage is extracted from 2-D simulation using the commonly used maximum
transconductance method. The parameters used in our simulation are given in Table 3.
Fig. 17 shows the variation of threshold voltage with change in strain (Ge content in
SiGe) for a gate length of 50 nm (effective channel length of 45 nm). We can observe that the
threshold voltage decreases almost linearly with increasing strain (even becoming negative
for a Ge content of 0.3-0.4), and the decrease in thV is quite significant. This reduction in the
threshold voltage with increasing Ge content x can be attributed to a decrease in the flat-band
voltage (equation (3)), decrease in the source-body/drain-body built-in potential barrier
(equation (4)), and an earlier onset of inversion due to a decrease in thφ (equation (53)). It
can also be noticed that the threshold voltage is slightly higher for a thicker strained-silicon
film, which may be due to an increase in the depletion charge. The threshold voltage
obtained from the model tracks the simulation values well.
Fig. 18 shows the variation of threshold voltage with gate length for different values
of Ge mole fraction in the SGOI layer, for a strained-silicon thickness of 5 nm and SiGe
thickness of 10 nm. It is observed that thV falls sharply below ~75nm gate length, due to
short channel effects like Drain Induced Barrier Lowering (DIBL), the gate-S/D charge
sharing etc. The thV values from the analytical model are in close proximity with the
simulation results.
45
Figure 17- Threshold voltage versus strain x for different strained-Si and SiGe film thicknesses
Figure 18- Threshold voltage versus channel length L
46
Fig. 19 also shows the variation of threshold voltage with gate length – however, here
thV is extracted from MEDICI as the gate voltage at which surface inversion electron
concentration becomes equal to background doping. It is evident that there is an excellent
match between model and simulation, thus confirming the model calculations. Therefore, the
small difference between model and simulations in various plots can be attributed to the
difference in the method of thV calculation (Model: Ninv = NA; MEDICI: Maximum
Transconductance).
Figure 19- Threshold voltage versus channel length L
Fig. 20 shows the effect of variation in body doping concentrations and gate work
functions on the threshold voltage for a gate length of 50 nm. It is evident that by using a
higher work function (eg. Mid-gap metal with Mφ =4.71 eV) material, we can afford a lower
doping and higher Ge concentration for the same Vth, thus achieving higher carrier mobility
due to lower impurity scattering and higher strain. This is because a higher workfunction gate
increases the flat-band voltage (equation (3)) as compared to a normal n+ poly-Si gate
( Mφ =4.35 eV).
47
Figure 20- Threshold voltage versus strain x for different body dopings
Fig. 21 shows the variation of threshold voltage versus the SiGe layer thickness, for a
fixed strained-Si film thickness. It can be seen that Vth is almost constant with change in
thickness of SiGe. The possible increase in Vth due to increase in the total depletion charge
under the gate (with increase in SiGe thickness), is mitigated by the enhanced SCEs due to
higher permittivity of SiGe. The higher permittivity of SiGe enhances the SCEs, leading to
worse roll-off in thicker SiGe. This is probably because the number of lines of electric force,
which increase in SiGe with the high permittivity, can lower the source-to-channel potential
barrier, leading to increase drain-induced barrier lowering (DIBL) [15]. As a result, thinner
SiGe layers are preferable.
48
Figure 21- Threshold voltage versus SiGe film thickness tSiGe.
In order to examine the Drain Induced Barrier Lowering (DIBL) effect for short-
channel strained-Si on SGOI MOSFETs, the saturation threshold voltage was extracted from
MEDICI simulations using the modified constant-current method at VDS = 0.5 V, where the
critical current is defined as the drain current when the gate voltage is equal to the linear
threshold voltage [31]. Fig. 22 shows the variation of saturation threshold voltage with gate
length for different values of Ge mole fraction in the SGOI layer, for a strained-silicon
thickness of 5 nm and SiGe thickness of 10 nm. Again, it is evident that thV falls drastically
below ~75nm gate length, due to short channel effects. The thV values from the analytical
model are in close proximity with the simulation results. The DIBL is computed as the
difference between the linear (VDS = 0.05 V) and saturation (VDS = 0.5 V) threshold voltages.
Fig. 23 shows the DIBL variation with gate length for 20% Ge mole fraction. It is observed
that the DIBL is significant for small channel lengths (below 60-70 nm), while it is negligible
for longer channel lengths (above 100 nm).
49
Figure 22- Saturation Threshold voltage versus channel length L
Figure 23- Drain Induced Barrier Lowering (DIBL) versus channel length L
50
Table 3: Device parameters used in simulation (FD-strained-Si on SGOI MOSFET) Parameter Value
Ge mole fraction in SiGe layer 0 – 0.4 (0 – 40%) Source/Drain doping 2x1020 cm-3
Body doping, NA 1017 cm-3 , 1018 cm-3
Gate Oxide Thickness, tf 2.0 nm Work function of gate material, Mφ 4.35 eV (n+ poly Si),
4.71 eV (Mid-Gap metal gate) Strained-Silicon film thickness, ts-Si 2 nm – 10 nm Silicon-Germanium film thickness, tSiGe 2 nm – 10 nm Buried Oxide Thickness, tb 100 nm Substrate bias, Vsub 0 Volts (Gnd) Drain bias, VDS 0.05 V, 0.5 V
5.4 Concluding Remarks
Strained Silicon-on-Insulator technology offers significant performance enhancement
over conventional bulk silicon and Silicon-on-Insulator technology [32]. The increase in
strain, i.e. Ge content in SiGe, enhances the performance of strained-Si on SGOI MOSFETs
in terms of improved transconductance and speed because of an increase in the carrier
mobility and velocity overshoot effects. However, as we have demonstrated, deleterious
effects of Vth roll-off with increasing strain, can affect the device characteristics and
performance significantly.
In the next chapter, we investigate into the current drive enhancement promised by
strained-Si devices and whether the same can be achieved for extremely short channel
devices. An analytical model for the output characteristics of nanoscale strained-Si/SiGe bulk
MOSFETs is developed for this purpose.
.
51
Chapter VI
Analytical Drain Current Model for Strained-Si/SiGe MOSFETs 6.1 Introduction
The low field mobility of carriers (μeff) is enhanced due to strain in Si thin films
grown pseudomorphically over a relaxed SiGe substrate [33]. However, for short channel
devices, high-field effects like velocity saturation work against this enhancement, and hence
the benefits of strained-Si for sub-100 nm CMOS are not obvious. In spite of this, enhanced
current drive and transconductance has been experimentally observed in deep submicron
strained-Si devices as well [49]. Non-local effects like velocity overshoot become prominent
as MOSFET dimensions shrink to the nanoscale regime, and this is directly related with the
aforementioned improvement in current drive observed in short-channel MOSFETs [34]. It
has been shown that an electric field step can result in the electron velocity exceeding the
saturation velocity for a period shorter than the energy relaxation time τw (which is an
average time constant associated with the energy scattering process, or the time needed by
the electron to once again reach equilibrium with the lattice), thus causing the electron to
approach ballistic transport conditions. Strain in the silicon thin film also leads to an increase
in the energy relaxation time (τw) of carriers, thus increasing the velocity overshoot [48].
Hence, to account for current enhancement in short channel strained-Si devices, the velocity
overshoot effect has to be considered [35].
6.2 Model for output characteristics of Strained-Si/SiGe nMOSFET
The low-field mobility of carriers is enhanced in strained-Si channels on SiGe
substrates due to reduced phonon scattering [22] and carrier redistribution in the modified
energy-subband structure [36]. The mobility enhancement factor ‘en’ for electrons, for
different values of Ge mole fraction ‘x’ of the relaxed SiGe substrate, is calculated based on
theoretical models [22,37] as
en = 1 for x = 0, en = 1.46 for x = 0.1, en = 1.68 for x = 0.2 (55)
The above values are found to agree well with experimental data [38]. The electron mobility
enhancement is found to be sustained at high values of the transverse electric field ‘ effE ’ as
well ( ~ 70% enhancement (en = 1.7) for x = 0.2, even for effE as high as 1.5 MV/cm) [3].
52
Using the Watt mobility model, the effective mobility of inversion layer electrons in the
channel at the gate-oxide / strained-Si film interface can be written as [14,39,40]:
( ) 11 1 1eff ph sr cμ μ μ μ
−− − −= + + (56)
where ( )0.16
648110
effph n
Eeμ
−⎛ ⎞
= ⎜ ⎟⎝ ⎠
, ( )2.17
659110
effsr n
Eeμ
−⎛ ⎞
= ⎜ ⎟⎝ ⎠
, ( )1.07 18
12
10127010
invc n
A
NeN
μ⎛ ⎞⎛ ⎞= ⎜ ⎟⎜ ⎟
⎝ ⎠ ⎝ ⎠.
Here phμ is the mobility associated with phonon scattering, srμ is the mobility associated
with surface roughness scattering and cμ is the mobility associated with coulomb/ionic
impurity scattering, all in units of cm2/V.s. The transverse electric field effE is given by [41]:
2inv
eff dSi
NqE Nε
⎛ ⎞= +⎜ ⎟⎝ ⎠
(57)
where ( )oxinv GS th
CN V Vq
≅ − and d A dN N x≅ .
In equation (57), invN is the inversion electron sheet density (per unit area), dN is the bulk
depletion charge density per unit area under the gate, and dx is the average depletion depth
under the gate (see equation (7) and (8)).
To account for velocity saturation in nanoscale devices at high longitudinal electric
fields, the following two-region piecewise empirical model for velocity ( )DDv x versus
longitudinal electric field xE (for electrons in the inversion layer) has been used [42,43]:
( )1
2
effDD x
eff x
sat
v x EEv
μμ=
+ for ( ) satE x E≤ (58)
( )DD satv x v= for ( ) satE x E> (59)
where 2 satsat
eff
vEμ
= is the saturation electric field, 71 10 /satv cm s×; is the saturation
velocity [14], and x is the distance from the source along the channel.
The above is the simple drift-diffusion model for carrier transport. However, for
nanoscale devices, non-local effects like velocity overshoot play a significant role. This
overshoot occurs in scaled devices because of the large gradient in the longitudinal electric
field in the channel, and the average carrier transit time from source to drain being
53
comparable to, or less than, the average energy relaxation time, wτ [47]. The carrier kinetic
energy, or equivalently the carrier temperature, lags the local field due to this finite energy
relaxation time wτ , or relaxation length ( )xEδ . When carriers are injected into the high-field
region of a scaled MOSFET channel, their random thermal kinetic energy is smaller than that
implied by the local field. Since the carrier mobility is inversely proportional to the carrier
energy, these carriers have mobilities that are high, and therefore move with velocities higher
than those implied by a local velocity-field model, i.e., they experience, on the average,
quasi-ballistic flow. The average velocity of the carriers can hence be higher than the
saturation velocity. Thus, including the velocity overshoot effect, the expression for carrier
velocity along the channel is modified as [44-46]:
( ) ( ) ( ) ( ) 21 13
x x sat w xDD DD
x x
E dE v dEv x v x v xE dx E dx
δ τ⎛ ⎞ ⎛ ⎞= + ≅ +⎜ ⎟ ⎜ ⎟
⎝ ⎠⎝ ⎠ (60)
Due to strain, the high field transport properties of carriers in the inversion layer are
also modified. Although the change in the saturation velocity with strain is expected to be
small, transient transport calculations at high lateral (longitudinal) fields show a significant
enhancement of the transient velocity overshoot with increasing energy splitting between the
conduction subbands i.e. with increasing strain [48]. This effect can be attributed to an
increase in the energy relaxation time with increasing strain [49]:
0.1w psτ = for x=0, 0.15w psτ = for x=0.1, 0.2w psτ = for x=0.2 (61)
where x is the Ge mole fraction in Si1-xGex substrate.
From equations (58) and (60), we get
( ) 2131
2
eff sat w xx
eff x x
sat
v dEv x EE E dxv
μ τμ
⎛ ⎞= +⎜ ⎟
⎝ ⎠+ (62)
To estimate the gradient of the longitudinal electric field along the channel, we assume a
quadratic variation of the electrostatic potential along the channel as
2
2( ) 12 2
DS DSV Va aV x x xL L
⎛ ⎞≅ − +⎜ ⎟⎝ ⎠ (63)
where a is a constant that could be dependent on device parameters and technological
features of the MOSFET. Comparing model with simulation, we get 0.2a ≈ . Thus,
54
( )2
2 2x DSd V xdE Va
dx dx L= =
(64)
This approximation is quite valid in strong inversion conditions and similar expressions can
also be found in [50,51]. It helps us in finally obtaining a closed form analytical expression
for the output drain current. Substituting (64) into (62) we get,
( ) 2
12
eff DSx
eff x
sat
Vv x E kE Lv
μμ
⎛ ⎞= +⎜ ⎟⎝ ⎠+
(65)
where 23sat wavk τ
= .
To derive the current expression, we first write the current at any point x along the channel as
( ) ( ) ( )( ) ( )D inv ox GS thI WQ x v x WC V V V x v x= = − − (66)
where W is the device width. Therefore,
( ) ( )( )D
ox GS th
Iv xWC V V V x
=− −
(67)
Putting (65) in (67) and using ( )x
dV xE
dx= we get:
( ) ( )( ) ( )21
2eff DS
D eff ox GS thsat
dV x dV x VI WC V V V x kv dx dx Lμ
μ⎛ ⎞ ⎛ ⎞+ = − − +⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠ (68)
By integrating the above equation from x= 0 to x= L and V(0) = 0 to V(L) =VDS, we arrive at
( )2 2
12 12
12
eff ox DS DSD GS th DS
eff DS
sat
WC V Vk kaI V V VV L L
Lv L
μμ
⎡ ⎤⎛ ⎞⎛ ⎞= − − + +⎢ ⎥⎜ ⎟⎜ ⎟⎛ ⎞ ⎝ ⎠⎝ ⎠⎣ ⎦+⎜ ⎟⎝ ⎠
for ,DS DS satV V≤ (69)
where ,
1
GS thDS sat
GS th
sat
V VV V VE L
−=
−+
is the drain voltage at which the carriers at the drain become
velocity saturated [43]. When VDS is greater than VDS,sat, the velocity saturation or pinch-off
point moves towards the source, away from the drain, by a distance ld. The voltage difference
VDS - VDS,sat is dropped across this distance ld, where ld is the channel length modulation,
given by [51]:
55
⎟⎟⎠
⎞⎜⎜⎝
⎛ −= −
satc
satDSDScd El
VVll ,1sinh (70)
where ( )2
av dvc
ox d
xlC Cε
=+
, 2
Si SiGeav
ε εε +; , avd
dv
Cxε
= and dvx is the vertical depletion region
depth under the gate (as defined in equation (6)). Hence, to obtain the current expression in
the saturation region, we integrate equation (68) from x = 0 to x = L - ld, and get
( )22 2
,,
, ,
1 1 1 12 2 6 3
12
eff ox DS satDS d DS d dDsat GS th DS sat
eff DS sat DS satd
sat
WC VV l V l lk k a aI V V VV LV L L L LlL
L v L
μμ
⎡ ⎤⎛ ⎞⎛ ⎞ ⎛ ⎞ ⎛ ⎞= − + − − − − − −⎢ ⎥⎜ ⎟⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟⎛ ⎞ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠⎢ ⎥⎝ ⎠⎣ ⎦− +⎜ ⎟⎝ ⎠
for ,DS DS satV V> (71)
Equations (69) and (71) reduce to the familiar velocity saturation limited drift-diffusion
current model given in [43] - and used in many previous works - for k = 0 i.e. no velocity
overshoot. To complete the analysis, we consider the impact ionization and avalanche
multiplication of carriers in the high-field region near the drain in the saturation regime. The
generation current (due to holes flowing into the substrate and electrons flowing out of the
drain), can be written as [52]:
( ) satDG IMI ,1−= (72)
where the multiplication factor ( )1M − is given by [53]
( ) ( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛
−−
−=−satDSDS
satDSDS VVVVM
,, exp1 βα (73)
where α and β are fitting parameters [54]. We have used 0.15α = and 15.7β = (from [7,
53]) in our model. For strained Si devices, the ionization rate increases with increasing strain,
because of the reduction in the bandgap of Si - ( )g s SiE −Δ (see eqn. (1)) - induced by the strain
at the Si/SiGe heterointerface [48]. Hence the multiplication factor is modified as:
( ) ( ),,
( )1 exp exp g s Si
DS DS satDS DS sat T
EM V V
V V qVβα −⎛ ⎞ Δ⎛ ⎞−
− = − ⎜ ⎟ ⎜ ⎟⎜ ⎟− ⎝ ⎠⎝ ⎠ (74)
Hence the total drain current in the saturation region can be written as:
GsatDD III += , for ,DS DS satV V> (75)
56
6.3 Results and Discussion
The low-field mobility enhancement in strained-Si n-MOSFETs can be explained by
suppressed intervalley scattering and reduced effective mass, due to the strain-induced
conduction band energy splitting [1]. However, high-field and transient transport properties
are expected to dominate the characteristics of deep submicron MOSFETs. Hence,
hydrodynamic (HD) (energy balance) device simulations were carried out using MEDICI
[14] to analyze the impact of low field mobility and high field transport on device
characteristics. In hydrodynamic modeling of current transport, the strength of transient
transport behavior is represented by the energy relaxation time wτ . With increasing strain, wτ
increases and almost doubles for x = 0.2, indicating that the transient electron velocity
overshoot is significantly enhanced. The Watt surface mobility model is used to model the
transverse-field dependent low field mobility, whereas, the high lateral-field transport is
modeled with “carrier temperature based mobility” (TMPMOB) [14]. In this approach, the
energy balance equation is locally solved concurrently with the drift-diffusion equation, to
calculate the local mobility as a function of the local carrier temperature. The simulation
parameters used are given in Table 4.
Fig. 24 shows the drain current enhancement with change in strain (Ge content in
SiGe) for a gate length of 50 nm and VGS = 0.75 V. We can observe that there is a significant
increase in the drain current with increasing strain. This can be attributed to three main
factors: 1) the increase in electron velocity overshoot due to increase in the energy relaxation
time wτ , 2) increase in low field mobility and 3) decrease in threshold voltage thV . Thus it is
evident that strained Si provides current enhancement even for nanoscale devices. However,
for a particular technology, it is desirable to have approximately the same thV for various
devices. Therefore, to exclude the contribution of decrease in thV to current enhancement, we
plot the normalized current ( ( )DS GS thI V V− ) versus drain voltage in Fig. 25. Clearly, we can
see that strained Si offers tremendous improvement in current drive. The model predictions
are in close proximity with simulation data.
57
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2 x 10-3
Ids
(A/u
m)
Vds (Volts)
MEDICIModel
x = 0
t = 2 nmox
Vgs = 0.75 V
x = 0.2
x = 0.1
Figure 24- Comparison of drain current for different Ge concentrations.
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2
2.5
3 x 10-3
Vds (Volts)
Ids/
(Vgs
-Vth
) (A
/um
/V)
MEDICIModel
x = 0
t = 2 nmox
Vgs = 0.75 V
x = 0.2
x = 0.1
Figure 25- Comparison of normalized drain current for different Ge concentrations.
58
Figs. 26, 27 and 28 show the output characteristics for different Ge mole fractions ‘x’
in the SiGe substrate (0, 0.1 and 0.2 respectively), and corresponding gate oxide thicknesses
tox, in order to keep roughly the same value of Vth ~ 0.25 V. It is observed that strained-Si
MOSFETs are able to achieve the same current drive as conventional unstrained MOSFETs,
even with a drastic increase in oxide thickness. There is a good agreement between model
and simulation throughout the range of device parameters and bias conditions.
Our model deviates slightly from the simulation results for GSV very close to Vth and
GS thV V? , because for these voltages our approximation for the inversion charge,
( )oxinv GS th
CN V Vq
≅ − , is not valid. However, as can be seen from the figures, an excellent
agreement is obtained for gate voltages ( GSV ) upto 1.0 volt, which is expected to be the
supply voltage for this technology (50 nm gate length).
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2 x 10-3
Ids
(A/u
m)
Vds (Volts)
MEDICIModel
x = 0t = 2 nmox
Vgs = 1 V
Vgs = 0.4 V
Vgs = 0.6 V
Vgs = 0.8 V
Figure 26- Output characteristics for conventional unstrained MOSFET (x = 0)
59
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2 x 10-3
Vds (Volts)
Ids
(A/u
m)
MEDICIModel
x = 0.1t = 4 nmox
Vgs = 1 V
Vgs = 0.4 V
Vgs = 0.6 V
Vgs = 0.8 V
Figure 27- Output characteristics for x = 0.1 and tox = 4 nm
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2 x 10-3
Ids
(A/u
m)
Vds (Volts)
MEDICIModel
x = 0.2t = 5 nmox
Vgs = 1 V
Vgs = 0.4 V
Vgs = 0.6 V
Vgs = 0.8 V
Figure 28- Output characteristics for x = 0.2 and tox = 5 nm
60
Fig. 29 shows the output characteristics for 20% Ge fraction in the SiGe substrate,
with a mid-gap metal gate. We can again see that the model values track the simulation data
well, thus confirming the validity of the model over different gate workfunctions as well.
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
2 x 10-3
Ids
(A/u
m)
Vds (Volts)
MEDICIModel
x = 0.2t = 2 nmox
Vgs = 1 V
Vgs = 0.5 V
Vgs = 0.75 V
Mid-gap metal gate4.71 eV
Figure 29- Output characteristics for x = 0.2, tox = 2nm and Mφ = 4.71 eV
Table 4: Device parameters used in the simulation (output characteristics of s-Si/SiGe MOSFET)
Parameter Value Ge mole fraction of SiGe substrate, x 0 – 0.2 (0 – 20%) Source/Drain doping 2x1020 cm-3
Body doping, NA 1018 cm-3 Gate Length, L 50 nm Gate Oxide Thickness, tf 2.0 nm – 6.0 nm Work function of gate material, Mφ 4.35 eV (n+ poly Si) Strained-Silicon film thickness, ts-Si 15 nm Source/drain junction depth, rj 50 nm Substrate bias, Vsub 0 Volts (Gnd) Drain bias, VDS 0.0 – 1.0 Volts Gate bias, VGS 0.4 – 1.0 Volts
(Vth ~ 0.25 V)
61
6.4 Concluding Remarks
Strain in the Si channel is emerging as a powerful technique of increasing MOSFET
performance. As we have demonstrated above, strain-induced enhancements will persist even
for extremely short channel length devices. Non-equilibrium high-field effects like velocity
overshoot contribute highly to the increase in current drive of these nanoscale devices.
Improvements in n-MOSFET performance can be obtained in a wide range of operating
conditions with moderate strain. Experimental evidence corroborating the same is also
widely reported [49,55].
62
Chapter VII
Conclusions For the first time, we have examined the effect of various device parameters like
strain (Ge mole fraction), gate length, source/drain junction depths, substrate (body) doping,
strained silicon thin film thickness, and gate work function on the threshold voltage of
nanoscale Strained-Si/SiGe, Fully Depleted-Strained Silicon On Insulator (FD-SSOI), and
Fully Depleted-Strained Silicon On SiGe-on-Insulator (SGOI) MOSFETs by developing
analytical models for the same. The 2-D Poisson equation is solved in the strained-Si thin
film using appropriate boundary conditions. The model results are compared with accurate
two-dimensional simulations [14]. The calculated values of the threshold voltage obtained
from the proposed model agree well with the simulated results. There is a significant drop in
threshold voltage with increasing equivalent Ge content and decreasing channel length. The
increase in strain, i.e. Ge content, enhances the performance of MOSFETs in terms of
transconductance and speed because of an increase in the carrier transport properties [1]-[5].
However, as demonstrated by our results, there are undesirable side effects with increasing
Ge content such as a roll-off in Vth, which may affect the device characteristics and
performance significantly. Our compact model accurately predicts the threshold voltage over
a large range of device parameters and can be effectively used to design and characterize
nanoscale Strained Si/SiGe, FD-SSOI, and FD-strained-Si on SGOI MOSFETs with the
desired performance.
We have also developed an analytical model for the output drain current
characteristics of short channel Strained-Si/SiGe MOSFETs by taking into account various
high field effects like velocity overshoot, velocity saturation, DIBL, Impact Ionization etc.
We demonstrate a significant current enhancement due to strain even in the nanoscale
regime, thus corroborating the advantages of strained-Si devices over a wide range of device
parameters. Our model gives a simple method for predicting the performance of strained-
Si/SiGe MOSFETs given the device parameters and bias conditions.
63
Future Work:
To extend our I-V model to the entire range of MOSFET operation (subthreshold current
etc.) and different strained Si device structures like SSOI and SGOI MOSFETs thus
completing the current modeling of strained Si devices. Also, methods for controlling Vth
roll-off with increasing strain and decreasing channel length need to be investigated.
64
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