Transcript
  • The Samsung Foundry MIPI M-PHY IP is a hard macro PHY for the UFS protocol. IO pads and ESD structures are included with extensive built-in self test features such as loopback and scan support. It offers a cost-effective and low-power solution. It builds on silicon-proven designs that are in volume production.

    MIPI M-PHY HS-G4 2-Lane

    Features • SamsungFoundry10nmlowpowerCMOSdevicetechnology

    • 1.8V,0.85Vdualpowersupply

    • ComplianttoMPHY4.1specification

    • SupportsHS-G1/HS-G2/HS-G3/HS-G4SeriesAandB(SeriesA:1.248G,2.496G,4.992G,9.984GbpsSeriesB:1.456G,2.912G,5.824G,11.648Gbps)

    • ChannelConfigurationforDataLanes •Common(CMN)and2DataLanes

    • Supportsthefollowingpre-emphasislevels •-1.5/3/6dB

    • 19.2Mor26MHzreferenceclockisrequired

    • Built-inselftestcapableofproducingandcheckingPRBSrandom patterns

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    Allinformationprovidedisforreferencepurposesonlyandmaybechangedwithoutnotice.

    Deliverables• Front-endDK:TimingLIB,Verilogmodel,sampletestbench

    • Back-endDK:PhysicalviewLEF,GDSIIlayout,DRC,LVS

    • Documentation:Datasheetanduserguide

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