May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Use of Hierarchy in Fault Collapsing
Raja K. K. R. Sandireddy
Intel CorporationHillsboro, OR 97124,
USA
Vishwani D. Agrawal
Auburn UniversityAuburn, AL 36849,
USA
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Outline• Introduction
– Main idea
– Background on fault collapsing
• Hierarchical fault collapsing– Method
– Advantages:• Smaller collapse ratio
• Reduced CPU time
• Results• Conclusions
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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The General Idea of Hierarchy
Circuit(top levelIn hierarchy)
Subnetwork analyzed once, placed in library.
interconnects
Lowest-level block (gates and interconnects),analyzed in detail, saved in library.
Analysis at nth level: 1. Copy preprocessed internal detail of n-1 level from library.2. Process nth level interconnects.
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Background on Fault Collapsing
DUT
Generate fault list
Collapse fault list
Generate test vectors
Fault model
Required fault coverage
Test Vector Generation Flow
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Structural Fault Collapsing
• Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set.– Equivalence collapsed set = {a0, b0, c0, c1}– Collapse ratio = 4/6 = 0.67
• Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults.– Dominance collapsed set = {a0, b0, c1}– Collapse ratio = 3/6 = 0.5
a0 a1
b0 b1
c0 c1 Total faults = 6
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Functional Collapsing: XOR Cell
a
b
c
d
e
g
h
i
j
k
m
c0 c1
d0
d1
Functional dominance examples: d0 → j0, k1 → g0
f
All faults = 24Str. Equ. Faults = 16Str. Dom. Faults = 13Func. Dom. Faults = 4
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Hierarchical Fault Collapsing• Create a library
– For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done.
– For larger circuits, use structural collapsing.• For hierarchical circuits, at any level of hierarchy, say
nth level:– Read-in preprocessed (library) collapse data of (n-1) level
sub-circuits.– Structurally collapse the interconnects and gate faults of nth
level.References:- R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault
Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014–1019.
- R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Results: Collapse Ratio Advantage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
FullAdder
64-bitAdder
1024-bitAdder
c432 c499
Structural Equiv.
Hierarchical Equiv.
Structural Dom.
Hierarchical Dom.
Co
llap
se
rati
o
Total faults 60 3,714 59,394 1,116 2,646
In hierarchical collapsing, faults in lowest level cells (XOR, full-adder) are functionally collapsed.Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign)
2. Fastest (obtained from Univ. of Wisconsin at Madison)3. Our program
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Fault Collapsing Time for Flattened Circuits
CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory.
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Analysis of CPU Time (s) for Flattened Circuits
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Analysis of CPU Time (s) for Hierarchical Circuits
14.33.10.379.254096-bit
50.26.00.7940.18192-bit
4.721.520.202.102048-bit
1.820.730.080.551024-bit
0.810.360.040.17512-bit
0.390.190.020.05256-bit
0.190.130.020.03128-bit
0.100.070.010.0164-bit
TotalLibraryEquiv.
+Dom.CollapsingStructure
Processing
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Comparison of CPU Times for Hierarchical and Flattened Circuits
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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CPU Time (s) Improvement by Hierarchy
Hierarchical circuitFlattened circuit
16.635.1674.112584096-bit
55.0127.22676--8192-bit
4.8010.3166.43262048-bit
2.313.6039.977.71024-bit
1.051.529.3819.5512-bit
0.490.692.495.09256-bit
0.240.320.751.47128-bit
0.100.160.240.5764-bit
Multi-levelTwo-levelOur ProgramHitec
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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CPU time (s) for Hierarchical Collapsing
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Rent’s rule
• Rent’s Rule: Number of inputs and outputs terminals (T) for a typical block containing G logic gates is given by:
T = K × G
~ 0.5 to 0.65
• For ripple carry adders, ~ 1. CPU time for collapsing is proportional to G2.
G isproportional
to area
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Hierarchical Multipliers
n/2×n/2
Additional Circuitry
n × n multiplier
~ √G inputs ~ √G outputs
n/2×n/2
n/2×n/2 n/2×n/2
Here ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size.
May 13, 2005 Sandireddy & Agrawal: Hierarchy in Fault Collapsing
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Conclusions• For larger circuits described hierarchically, use
hierarchical fault collapsing.• Hierarchical fault collapsing:
– Better (lower) collapse ratios due to functional collapsed library
– Order of magnitude reduction in collapse time.
• Smaller fault sets:– Fewer test vectors
– Reduced fault simulation effort
– Easier fault diagnosis.
Dom. Collapsed Set Size (Collapse Ratio)
CPU s
Flat Hierarchical Flat Hier.
229378 (0.48) 98304 (0.21) 2676 55
8192-bit Adder