1 Verilint Coding Rules
Introduction
This chapter provides detailed reference information for the Leda Verilint policy, which is centered on the former Avant! Nova-Verilint tool. These rules are for Verilog only.
Note that Avant! Corporation marketed Nova-Verilint before its acquisition by Synopsys Inc. The Leda Verilint policy covers most of the synthesis and simulation-related checks that were performed by Nova-Verilint. Leda performs these checks during:
o Language syntactic and semantic analysis o Specific post-analysis checking phase
In the Leda environment, rules checked during the post-analysis phase are organized into policies and rulesets that you can activate and manage from the command-line using the -p or -r options, or from the GUI using the Rule Configuration Wizard. For more information on activating and configuring rules to meet your own design team's needs, see the Leda User Guide. The rules in the Verilint policy that are checked during the post-analysis phase are organized into one ruleset named CHECKER_ERROR. The labels for these rules are the same as the ones used in Nova-Verilint for similar checks. It is the descriptions for these CHECKER_ERROR rules that make up the bulk of this chapter.
CHECKER_ERROR Ruleset
The following rules are from the CHECKER_ERROR ruleset:
E25
Message: Bits are backwards
DescriptionLeda fires for this rule when it detects that the high index of the width range is in the RHS.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example: a[1:2]
module top(a, b);input [2:1]a;output [2:1]b;reg [2:1]b;
always @ (a[1:2] or a[2]) if(a[2]) b<=1'b0; else if(b) b<=1'b0; else b<=a;endmodule
E54
Message: Instance name required for module
DescriptionLeda fires for this rule when there is no instance name for a module. To solve this problem, name the instance.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example: test(clk, reset, d, q);
module top (clk, reset, d, q);input clk, reset, d;output q;
test (clk, reset, d, q); //E54, no instance name.
endmodule
module test (clk, reset, d, q);input clk, reset, d;output q;reg q;
always @(posedge clk or posedge reset)if (reset == 1'b1)q <= 1'b0;elseq <= d;
endmodule
E66
Message: Not a constant expression
DescriptionLeda fires for this rule when it detects variables in parameter or defparam definitions. To solve this problem, use a constant expression.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example: i
module test;
integer i;parameter k = i;
endmodule
E267
Message: Range index out of bound
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example: input [2:1]a;...always @ (posedge a[1:0])...module top(clk, reseta, resetb, a, b);input clk, reseta, resetb;input [2:1]a;output [2:1]b;reg [2:1]b;
always @ (posedge a[1:0]) if(reseta) b<=1'b0; else if(resetb) b<=1'b0; else b<=a;
endmodule
E268
Message: Index out of bound
DescriptionLeda fires for this rule when it finds an index that is not in the interval of the width range.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example: index 0
module top(a, b);input [2:1]a;output [2:1]b;reg [2:1]b;
always @ (a[1] or a[0]) b<=a;endmodule
E304
Message: Drive strength cannot be given to a net
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Error
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
wire (weak1, pull0) b = a ;module warn; wire a; wire (weak1, pull0) b = a ;endmodule
E368
Message: Variable previously declared as vector
DescriptionThis rule fires when Leda finds a variable previously declared as a vector.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: wire a;
module test ( a , y ); input [7:0] a; output [7:0] y;
wire a; //E368 wire [7:0] y; assign y=~a;
endmodule
W19
Message: Truncation of error bits
DescriptionFlags if size of literal is too small for value. For example:In 3'h10, hex 10 requires 8 bits, but bit size of literal is specified to 3 bits.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W20
Message: Assign statement may not be synthesizable
Description
Leda fires for this rule when it finds a statement that may not be synthesizable. This applies only to procedural continuous assignment statements. Continuous assignments are synthesizable.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example
module proc_conti_assignment(D, Clr, Clk, Q);input D, Clr, Clk;output Q;reg Q;
always@(Clr) beginif (Clr == 0)assign Q=0; //W20elsedeassign Q; //W21
end
always@(negedge Clk) Q=D;
endmodule
W21
Message: Deassign statement may not be synthesizable
DescriptionLeda fires for this rule when it finds a statement that may not be synthesizable.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module proc_conti_assignment(D, Clr, Clk, Q);input D, Clr, Clk;output Q;reg Q;
always@(Clr) beginif (Clr == 0)assign Q=0; //W20elsedeassign Q; //W21end
always@(negedge Clk) Q=D;
endmodule
W43
Message: Wait statement may not be synthesizable
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: wait(reset)
module test(clk, reset, q);input clk, reset;output q;
always @(clk)wait(reset) //W43, wait is not synthesizedq <=1'b1;
endmodule
W67
Message: Not a constant expression
Description
Leda fires for this rule when it finds a variable expression where a constant expression is expected. A constant expression is suspicious if it is used as the conditional expression in a control statement. Similarly, a constant expression is not expected in an event expression. Note that constant expressions can be made of literals and/or parameters. This rule is only checked in MinTypMax expressions.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: nand #(i:5:7, 5:6:7) (out, in1, in2);
module test(in1, in2, out);input in1, in2;output out;integer i;nand #(i:5:7, 5:6:7) (out, in1, in2); //W67endmodule
W69
Message: Case statement without default clause but all the cases are covered
Description
Leda fires for this rule when it finds a case statement that has no default clause, but which appears to cover all cases. Even if all cases that have 1's and 0's are covered, there may be others that are not covered. A default clause can cover these additional cases.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg r;...case(r) 1'b0: ... 1'b1: ...endcase
module test(clk,reset,gate,phase);input clk, reset;
input [1:0] gate;output [3:0] phase;wire clk, reset;wire [1:0] gate;reg [3:0] phase;
always @(posedge clk) begin if (reset) begin phase <= 4'b0000; end else begin case (gate) 2'b00: phase <= 4'b0001; 2'b10: phase <= 4'b0100; 2'b01: phase <= 4'b0010; 2'b11: phase <= 4'b0001; endcase endend
endmodule
W71
Message: Case statement without default clause and not all cases are covered
DescriptionLeda fires for this rule when it finds a case statement that does not have a default clause, and not all cases are covered.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg [1:0] r;...case(r) 2'b00: ... 2'b01: ... 2'b10: ...
//W71, 2'b11 is missingendcase
W110
Message: Incompatible width
DescriptionLeda fires for this rule when it finds an instance port expression that has a different width than the module port.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: i1, o1
module top(i1, o1);input [5:0] i1;output [5:0] o1;
mm u1(i1, o1); //W110
endmodule
module mm(i, o);input [3:0] i;output [3:0] o;
assign o = ~i;
endmodule
W112
Message: Nested event control construct
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: @(posedge clk or posedge reset) in always block
module test(clk,reset,gate,phase);input clk, reset;input [1:0] gate;output [3:0] phase;wire clk, reset;wire [1:0] gate;reg [3:0] phase;
always @(posedge clk) begin if (reset) begin phase <= 4'b0000; end else begin :block1 @(posedge clk or posedge reset); //W112 case (gate) 2'b00: phase <= 4'b0001; 2'b10: phase <= 4'b0100; 2'b01: phase <= 4'b0010; default: ; endcase endend
endmodule
W121
Message: Variable hides a variable in outer scope <%item>
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of Verilog code exhibits this problem:
// Variable NG is in both outside and inside of functionmodule TEST ( A, RST, ENV, B); input A,RST,ENV; output B; reg NG; function latch; input A,RST,ENV; reg NG; if( RST ) begin latch = 1'b0; end else if( ENV ) begin latch = A; end endfunction assign B = latch(A,RST,ENV); endmodule
W122
Message: Variable is not in the sensitivity list
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W126
Message: Non integer delay
DescriptionLeda fires for this rule when it finds a delay that is not an integer, but a real type.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of Verilog code exhibits this problem:
module test (in1, out1, out2);
input in1;output out1, out2;reg out1, out2;
parameter TP1 = 0.5;parameter TP2 = 5;
always @(posedge in1)begin
out1 <= #TP1 in1; //Rule W126 firesout2 <= #TP2 in1;
endendmodule
W127
Message: Delay has X or Z
DescriptionLeda fires for this rule when it finds a delay that is not a positive integer, because it contains an X or Z.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: #(1'bz)
`timescale 1ns/100psmodule test(in1, in2, out1, out2, out3);input in1, in2;output out1, out2, out3;integer i;
assign #(0.987) out1= in1& in2;assign #(1'bz) out2 = in1 & in2; //W127, delay has x or zassign #(i) out3 = in1 & in2; //W129, delay is not a constant
endmodule
W129
Message: Delay is not a constant
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: #(i)
`timescale 1ns/ 100psmodule test(in1, in2, out1, out2, out3);input in1, in2;output out1, out2, out3;integer i;
assign #(0.987) out1= in1& in2;assign #(1'bz) out2 = in1 & in2; //W127, delay has x or zassign #(i) out3 = in1 & in2; //W129, delay is not a constant
endmodule
W131
Message: Potential loss of precision in multiplication
DescriptionLeda fires for this rule when there is a potential loss of precision in multiplication. This can be caused by an incorrect wire scale declaration.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: out = in1 * in2; out, in1 and in2 are all one bit.
module test(in1,in2,out);input in1, in2;output out;wire in1, in2;wire out;
assign out = in1 * in2; //W131endmodule
W154
Message: Implicit wire declaration
Description
Leda fires for this rule when it finds an implicitly declared wire that is not declared explicitly, but appears in the argument list of an instantiation. Leda flags such wires because undeclared variables can be caused by typos. If your netlist is generated automatically (for example, from a schematic), you can suppress this warning.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
wire i, b, c;and (j, b, c); //W154, should have been and (i, b, c);
W159
Message: Constant condition expression
Description
Leda fires for this rule when it finds a constant expression used as the conditional expression in a control statement. Similarly, a constant expression is not expected in an event expression. Note that constant expressions can be made of literals and/or parameters.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
if(2>1)
W161
Message: Constant expression in conditional select
DescriptionLeda fires for this rule if the condition in a conditional expression is constant.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
a = (1'b0) ? b : c;
W163
Message: Truncation of bits in constant. Most significant bits are lost
DescriptionLeda fires for this rule when it finds an integer converted to a vector that is shorter than 32 bits, and some of the bits that are discarded are non-zero.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
r[3:0]=16;
W175
Message: A parameter/generic has been defined but is not used
DescriptionLeda fires for this rule when it finds a parameter/generic has been defined but not used in the file.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog/VHDL
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module test (input wire reset, clk, D, output reg Q);Parameter P = 5; //W175, parameter declared but not usedalways@(posedge clk)beginif(!reset) Q <= 1'b0;else Q <= D;end
endmodule
W182
Message: Illegal statement for synthesis
Description Leda fires for this rule when it finds a statement that cannot be synthesized. This rule applies to the following statements:
o repeat o while -> (event triggering) o fork o force
o release
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
module w182 (go, clk, inp);input go, clk;input [9:0]inp;reg [15:0]r1;always @(posedge go) r1 <= repeat (2) @(posedge clk) inp*2; //W182endmodule
W187
Message: Default clause is not the last clause in case statement
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:case(...)
... default: ... ... 2'b0x: ...endcase
W188
Message: Destination variable is input
Description
Leda fires for this rule when it finds a destination variable declared as an input port. This rule is flagged only if the destination variable is a vector or a part-select of a vector. Leda does not flag this rule if the destination variable is a bit-select. You can use rule W397 to identify destination variable that are bit-select.To solve this problem, declare the destination variable as an inout or output.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: input x ; assign x = .....;module w188 ( a, b, ps, bs, x);input a, b;input [3:0] ps;input [1:0] bs;input x;
assign ps[1:0] = a & b; // Rule W188 is flagged hereassign bs[1] = a | b; // Rule W188 does not flag hereassign x = a & b; // Rule W188 is flagged here
endmodule
W192
Message: Empty block
DescriptionLeda fires for this rule when it finds a "begin ..end" block without any statements.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: begin ... end
module test(enable);input enable;always @(enable) begin //W192, empty blockendendmodule
W215
Message: Bit select for integer or time variable
DescriptionBit-selects are taken from integer variables. Integers should not be treated as vectors. If you want to take a bit-select or part-select from a variable, declare the variable as a vector.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
integer i;
initial i[0] = 1'b0; // W215
initial i[2:1] = 2'b11; // W216
W216
Message: Range select for integer or time variable
DescriptionPart-selects are taken from integer variables. Integers should not be treated as vectors. If you want to take a bit-select or part-select from a variable, declare the variable as a vector.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
integer i;
initial i[0] = 1'b0; // W215
initial i[2:1] = 2'b11; // W216
W218
Message: Illegal event expression
Description Leda flags this rule when it finds an illegal event expression.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W224
Message: Multi-bit expression when one bit expression is expected
DescriptionThe condition expression in an if statement or in a conditional expression is wider than 1 bit.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
if (a[3:0]) //W224, should be if (a[3:0]!=4'b0000)
W225
Message: Case item expression is not constant
DescriptionSome of the case items have constant expressions and some do not.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a) 2'b01: b=a; 2'b10: b=-a; c+d: b=1; //W225, c+d is not constant ...endcase
W226
Message: Case-select expression is constant.
Description The case expression is constant.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (1) 2: ... ...endcase
W228
Message: While condition expression is constant
Description
A variable expression was found where a constant expression was expected. A constant expression is suspicious if it is used as the conditional expression in a control statement. Similarly, a constant expression is not expected in an event expression. Note that constant expressions can be made of literals and/or parameters.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example
while(1) //W228, always true--forever loop
W239
Message: Hierarchical references may not be synthesizable
DescriptionLeda flags this rule if it finds hierarchical refernces as they are not synthesizable.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
module TEST (input in1);endmodule
module mW239 (input in1, output out1);
TEST T1(in1);
assign out1 = T1.in1; // Rule W239 fails here
endmodule
W244
Message: Shift by non-constant
Description
Leda fires for this rule when it finds a shift expression that has a non-constant shift operand. In synthesized code, this may be translated into a selector; whereas, a shift by constant does not generate any hardware, only wiring. Note that constant expressions can be made of literals and/or parameters.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// wire [2:0] a;
wire [7:0] b;... b << a ...
W250
Message: Disable statement is not synthesizable
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module test(in1, in2, out1);input [7:0] in1, in2;output [7:0] out1;wire [7:0] in1, in2;reg [7:0] out1;
always @(in1 or in2 ) begin : b1 integer i; for(i=0;i<=10;i=i+1) begin: b2 if(i > 7) disable b2; //W250, disable statement is not synthesizable out1[i] = in1[i] ^ in2[i]; end endendmodule
W256
Message: A notifier must be a one-bit register
Description A notifier must be a one-bit register.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
//This test case has a notifier which is 2 bits wide.module mW256(input clk, output out2);wire [1:0] notifier = 2'b10;always @ (clk)$setup(out2, clk, 2, notifier); //FAIL: notifier is 2 bits wideendmodule
W257
Message: Delays ignored by synthesis tools
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: assign #3 out1 = in1 ^ in2;
`timescale 1ns/100psmodule test(in1, in2, out1, out2);input in1, in2;output out1, out2;
assign #3 out1 = in1 ^ in2; //W257, delays ignored by synthesis tool
and #(2, 3) AL (out2, in1, in2); //no W257.
endmodule
W263
Message: Case expression out of range
DescriptionLeda fires for this rule when it finds an integer constant used in a case item expression that is larger than the largest representable case expression.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a[2:0]) // numbers between 0 and 7 -1: ...; //W263, number too small 9: ...; //W263, number too big
W280
Message: Delay in non blocking assignment
Description This test is done only in sequential always blocks.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
c <= #1 d; //W280, could be a blocking assignment
W287
Message: Unconnected port
DescriptionLeda fires for this rule when it finds a port that is not connected in a module instantiation.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W289
Message: Multiply connected port
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module m(a, b); input a; output b; assign b=~a;endmodulemodule mm(x, y); input x; output y; m u1(.a(x), .a(y)); //W289, port a is connected twiceendmodule
W292
Message: Real operands in comparison
Description Leda flags this rule when it finds real operand comparison.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W294
Message: Unsynthesizable real variable
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: K
module top(a, b);input [2:1]a;output [2:1]b;wire c;real K; //W294
assign b[2] = a[1];endmodule
W299
Message: Blocking repeat assignment
DescriptionLeda fires for this rule when it finds a repeat event control as the intra-assignment delay of a blocking assignment. These statements cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W300
Message: Non-blocking repeat assignment
DescriptionLeda fires for this rule when it finds a repeat event control as the intra-assignment delay of a non-blocking assignment. These statements cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: r1 <= repeat (2) @(posedge clk) inp*2;
module warn(go, clk, inp);input go, clk;input [9:0]inp;reg [15:0]r1;always @(posedge go) r1 <= repeat (2) @(posedge clk) inp*2;endmodule
W306
Message: Converting integer to real
Description
Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to different types depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: rl1 = int1;
module warn;integer int1;real rl1;initial begin rl1 = int1; //W306endendmodule
W307
Message: Converting unsigned to real
Description
Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to a different type depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: f_time_xin = (f_time_sysc * 1.5);
module ec;time f_time_xin, f_time_sysc;initial f_time_xin = (f_time_sysc * 1.5);endmodule
W308
Message: Converting real to integer
Description
Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to different types depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: int1 = rl1;
module warn;integer int1;real rl1;initial begin int1 = rl1; //W308endendmodule
W311
Message: Converting real to unsigned
Description
Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to a different type depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: r1 = rl1;
module warn;reg [1:0] r1;real rl1;initial begin r1 = rl1; //W311endendmodule
W312
Message: Converting real to single bit (logical)
Description Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to different types depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is
converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: r1 = rl1;
module warn;reg r1;real rl1;initial begin r1 = rl1; //W312endendmodule
W313
Message: Converting integer to single bit (logical)
DescriptionLeda fires for this rule when it finds an integer that is set to a one-bit signal.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: 6 is set to one-bit signal x.
module top(clk,f);input clk;output f;function top;input x;top=x; //W313, x=6, and top is a bit wire.endfunction
reg f;
always @clkf=top(6);endmodule
W314
Message: Converting vector (unsigned) to single bit (logical)
Description
Verilog allows type mixing in expressions. When subexpressions of different types are used in an expression, they may be converted to a common type. This conversion is done automatically by the Verilog processor (that is, simulator). Additionally, expressions are converted to different types depending on the context in which they are used. For example, if an expression is assigned to a variable, then the expression is converted to the same type as the variable. Leda detects such conversions and issues warnings.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: vector "in" is set to one-bit "out".
module test(in, out);input [1:0] in;output out;wire [1:0] in;
assign out =~in; //W314
endmodule
W322
Message: Multiple event control statement
DescriptionLeda fires for this rule when it detects multiple event control statements in an always block.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module warn;wire a, b;reg o;
always #5 begin @(posedge a); @(posedge b); o = a ^ b; endendmodule
W332
Message: Not all possible cases covered but default case exists
DescriptionYou may want to use the default to catch Xs and Zs but not to catch missing cases.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a[1:0]) 2'b00: ...; 2'b01: ...; 2'b10: ...; default: ...;endcase //W332, 2'b11 is not covered
W335
Message: Non blocking delay assignment in combinational always block
Description
Leda fires for this rule when it finds a non-blocking delay assignment in a combinational always block. Synthesis tools ignore delays, causing simulation mismatches between pre- and post-synthesis. Avoid using delays in non-blocking assignments.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top (a, b); input a; output b; reg b;
always @(a)
b <= #1 a;
endmodule
W336
Message: Blocking delay assignment. In sequential always blocks consider using nonblocking assignment
DescriptionBlocking assignment. In sequential always blocks, consider using nonblocking assignment. This rule is flagged for unintentional latches also.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code demonstrates the potential race condition using a two-stage shift register.
// Example:
always @(posedge clk) begin c = b;end
always @(posedge clk) begin b = a;end
W337
Message: Real comparison in case item
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a)2.0: ...; // Reals are typically not used in comparisons
W339
Message: Non synthesizable operator
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized. This applies to the === and !== operators.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: if (w1===w2)
module warn;wire [3:0] w1, w2;reg result;initial begin if (w1===w2) //W339 result = 1;endendmodule
W341
Message: Extension of zero bits in a constant
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: assign a = 4'b0; module test(set, d, a, b, c);input set;input [3:0] d;output[3:0] a, b, c;wire set;wire [3:0] a, b, c, d;
assign a = 4'b0; //W341assign b = set? 4'bx : d; //W342assign c = set? 4'bz : d; //W343endmodule
W342
Message: Extension of X bits in a constant
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: assign b = set? 4'bx : d;
module test(set, d, a, b, c);input set;input [3:0] d;output[3:0] a, b, c;wire set;wire [3:0] a, b, c, d;
assign a = 4'b0; //W341assign b = set? 4'bx : d; //W342assign c = set? 4'bz : d; //W343
endmodule
W343
Message: Extension of Z bits in a constant
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: assign c = set? 4'bz : d;
module test(set, d, a, b, c);input set;input [3:0] d;output[3:0] a, b, c;wire set;wire [3:0] a, b, c, d;
assign a = 4'b0; //W341assign b = set? 4'bx : d; //W342assign c = set? 4'bz : d; //W343
endmodule
W359
Message: For-condition expression is constant
Description
A constant expression was found where a variable expression was expected. A constant expression is suspicious if it is used as the conditional expression in a control statement. Similarly, a constant expression is not expected in an event expression. Note that constant expressions can be made of literals and/or parameters.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
for (i=1; 3; i=i+1)
W372
Message: Undefined PLI task
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: $pli(1);
module test;reg r1;initial $pli(1); //W372, $pli is an undefined PLI task
endmodule
W373
Message: Undefined PLI function
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: r1 = $pli(1);
reg r1;initial r1 = $pli(1); //W373, $pli is an undefined PLI function module test
endmodule
W389
Message: Multiple clocks in the module
Description
Leda infers clock and reset signals in a way that is similar to synthesis. This may not apply to all design methodologies.For a description of Leda 's interpretation of Verilog hardware semantics, see the sections on "About Hardware-Based Rules" and "Verilog Hardware Semantics" in the Leda User Guide.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clk1,clk2, reset, a, b);input clk1,clk2, reset, a;output b;reg b;
always @ (posedge clk2) b = a;
always @ (posedge clk1) if(reset) b<=1'b00; else b<=a;endmodule
W390
Message: Multiple resets in the module
Description
Leda infers clock and reset signals in a way that is similar to synthesis. This may not apply to all design methodologies. Verilint only checks asynchronous resets.For a description of Leda 's interpretation of Verilog hardware semantics, see the sections on "About Hardware-Based Rules" and "Verilog Hardware Semantics" in the Leda User Guide.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clk, reset1, reset2, a, b, c);input clk, reset1, reset2, a;output b, c;reg b, c;
always @ (posedge clk or posedge reset1) if (reset1) b<=1'b0; else b<=a;
always @ (posedge clk or posedge reset2) if (reset2) c<=1'b0; else c<=~a;endmodule
W392
Message: Wrong reset polarity
Description
The same reset is used both as a positive edge and a negative edge. Some methodologies require that all reset and clock lines be primary inputs to the module. If they are generated internally to the module, Leda issues this message.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: posedge reset
module test(clk, reset, q);input clk, reset;output q;wire clk, reset;
reg q;
always @ (posedge clk or posedge reset) //W392, wrong reset polarityif (reset == 1'b0)
q <= 1'b0;
endmodule
W394
Message: Multiple clocks in the always block
DescriptionLeda issues this message when it detects more than one signal used as a clock in an always block.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clk1, clk2, a, b);input clk1, clk2, a;output b;reg b;
always @ (posedge clk1 or posedge clk2) b<=a;endmodule
W396
Message: A flipflop without reset
Description
Leda infers clock and reset signals in a way that is similar to synthesis. This may not apply to all design methodologies.For a description of Leda 's interpretation of Verilog hardware semantics, see the sections on "About Hardware-Based Rules" and "Verilog Hardware Semantics" in the Leda User Guide.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module test(clk, reset, d, q);input clk, reset, d;output q;reg q;
always @(posedge clk )begin:block if (reset==0)// q=0;// else q=d;end
endmodule
W397
Message: Destination bit is input
Description
Leda fires for this rule when it finds a destination bit variable is used as an input port. This rule is flagged does not flag for if the destination variable is a vector or a part-select of a vector. Leda flags this rule only if the destination variable is a bit-select. You can use rule W188 to identify destination variable that are part-select or vectors.To solve this problem, declare the destination variable as an inout or output.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
module w188 ( a, b, ps, bs, x);input a, b;input [3:0] ps;input [1:0] bs;input x;
assign ps[1:0] = a & b; // Rule W397 does not flag hereassign bs[1] = a | b; // Rule W397 is flagged hereassign x = a & b; / Rule W397 does not flag hereendmodule
W401
Message: Clock is not an input to the module
Description
Leda fires for this rule when it finds a clock that is not an input to the module, but an internal signal. For a description of Leda 's interpretation of Verilog hardware semantics, see the sections on "About Hardware-Based Rules" and "Verilog Hardware Semantics" in the Leda User Guide.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
clkInt module w401 (clkExt1,clkExt2,dataIN,dataOUT,testMode);
input clkExt1,clkExt2,dataIN,testMode; output dataOUT; reg dataOUT;
wire clkInt; assign clkInt = testMode ? clkExt2 : clkExt1;
always @ (posedge clkInt) begin
dataOUT <= dataIN; endendmodule
W402
Message: Reset is not an input to the module
Description
Leda fires for this rule when it finds a reset that is not an input to the module, but an internal signal. For a description of Leda 's interpretation of Verilog hardware semantics, see the sections on "About Hardware-Based Rules" and "Verilog Hardware Semantics" in the Leda User Guide.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
resetInt module w402 (clk,dataIN,dataOUT,testMode);
input clk,dataIN,testMode; output dataOUT; reg dataOUT; wire resetInt; assign resetInt = testMode ? 1'b1 : 1'b0;
always @ (posedge clk or posedge resetInt) begin
if (resetInt) dataOUT <= 0;
else dataOUT <= dataIN;
end endmodule
W403
Message: Clock is used as data
Description
Leda fires for this rule when it finds a clock used as data. A signal used as a clock is also providing data to a register input, either directly or through combinational logic. This can cause timing violations and race conditions. To solve this problem, check for clocks that are not in the sensitivity list of an always block. To check this rule on the entire design, you must specify a top design unit using the -top option.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Chip-level
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: b = clk;
module top(clk, reset, a, b);input clk, reset, a;output b;reg b;
always @ (posedge clk) b = clk;
always @ (posedge clk) if(reset) b<=1'b00; else b<=a;endmodule
W410
Message: A latch is inferred
Description
Leda fires for this rule if it finds a latch in the design. A latch is inferred if, within a combinational always block, there is a variable assigned in some, but not all threads of the block. The algorithm is similar to the algorithm used in synthesis.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(d or g) if (g) q=d; //W410, if g is 0, then q is not assigned
always @(a) case 2'b00: c=2'b11; case 2'b01: c=~a; case 2'b10: c=a; // The case a=2'b11 is missing endcase
W414
Message: Non blocking assignment in combinational block
Description
Leda infers always blocks as either combinational or sequential. For sequential always blocks, Leda issues a warning if there is blocking assignment. For combinational blocks, Leda issues a warning if there is a non-blocking assignment. Using non-blocking assignments in sequential blocks removes the risk of a race condition in the simulation.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(a or b) begin c = a+b; d <= a-b; //W414end
always @(posedge clk) beginc = a+b; //W336d <= a-b;end
W415
Message: Multiple drivers to a net
Description
Leda fires for this rule when it finds a net that has more than one driver. The driver can be an output from a gate, an output from a module instance, a left-hand side of a continuous assignment, or a left-hand side of an assignment in a combinational always block.Leda checks the compatibility between the declaration of a port and the declaration of the net or reg to which the port is connected.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Chip-level
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
assign w=a;and (w, b, c);
W416
Message: Instance connections not by name
Description
Leda fires for this rule when it finds a module instantiation that is connected by position rather than by name. Some companies require that all instances be connected by name to reduce the probability of switching connections.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
mm u1(a, b); //W416 mm u2(.port2(b), .port1(a)); //no W416
W421
Message: Non event-control statement (@) in always block
DescriptionThe first statement in an always block is not an event-control statement (that is, not an @).
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always begin a = b; //W421, <-- The first statement is an assignment. @(c or d) //Only the second statement is an event-control. ...end
W424
Message: Function sets a global variable
DescriptionLeda fires for this rule when it detects a function that sets a variable outside of the function.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: out
module w424 (in,out); input in; output out; reg out ; function val; input in; out = in; endfunction // val
endmodule
W425
Message: Function uses a global variable
DescriptionLeda fires for this rule when it finds a function which uses a variable that does not come from the input of the function.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: in
module w425 (in,out); input in; output out; reg out ; function val; input func_in; val = in; endfunction // val initial out = val(in); endmodule
W426
Message: Task sets a global variable
Description Leda fires for this rule when it finds a variable set outside of the task. This breaks the task. To solve this problem, use a function
to replace the task, and make the global variable a value of the function.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: out module w426(reset,out); input reset; output out; reg out; task test; input reset; begin
if (reset) out = 1'b0;
end endtask // test initial test(reset); endmodule
W427
Message: Task uses a global variable
DescriptionLeda fires for this rule when it finds a variable used outside of the task. This breaks the task. To solve this problem, make the global variable an input to the task.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: reset module w427;
wire reset; task test; reg a; begin
if (reset) a = 1'b0;
end endtask // test initial test; endmodule
W430
Message: Initial statement is not synthesizable
DescriptionLeda fires for this rule when it finds an initial statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module Top (clock);output clock;
initial clock = 1'b0;
always #5 clock = ~clock;endmodule
W434
Message: Top level module is a primitive
DescriptionLeda fires for this rule when there is only a primitive in the design or the top-level module of the design is a primitive.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: primitive MUX2x1
primitive MUX2x1 (Z, Hab, Bay, Sel); output Z; input Hab, Bay, Sel;
table endtableendprimitive
W438
Message: Tristate is not in a top level module
DescriptionYou must specify the top-level module name using the -top option of the Leda Checker, or its name must begin with "TOP".
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clock, a, b);input clock, a;output b;reg b;
sub test(clock, a,b);
endmodule
module sub(clk, c, d);input clk, c;output d;
always @ (posedge clk) begin if(clk) d = c; else d = 1'bZ;endendmodule
W443
Message: X in based number constant
DescriptionLeda fires for this rule if it finds a constant with a value including an X (even if the constant is used in a case item of a casex/casez statement).
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:module w443 (); wire d;assign d = 1'bX;endmodule
W444
Message: High Z in based number constant
DescriptionLeda fires for this rule if it finds a constant with a value including a Z.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clock, a, b);input clock, a;output b;reg b;
sub test(clock, a,b);
endmodule
module sub(clk, c, d);input clk, c;output d;
always @ (posedge clk) begin if(clk) d = c; else d = 1'bZ; //W444, High Zendendmodule
W445
Message: Output or inout tied to supply
DescriptionLeda fires for this rule when it finds an output or inout port declared as supply0 or supply1 net.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w445 (OUT, INO);output OUT;inout INO;supply0 OUT;supply1 INO;endmodule
W446
Message: Reading from an output port
DescriptionLeda fires for this rule when it finds an output signal used as an input signal.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clk, reset, a, b);input clk, reset, a;output b;reg b;
always @ (posedge clk) if(reset) b<=1'b00; else b <= a & b;endmodule
W450
Message: Multi-bit expression (e.g., a[2:0]) used as clock
DescriptionLeda fires for this rule when it finds more than one bit used as a clock.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:module w450 (q, d, clock); output q; input d; input [2:0] clock;
reg q;always @(posedge clock) q <= d;endmodule
W455
Message: Not all cases are covered in full case
DescriptionLeda fires for this rule when it finds a full case (that is, one that has the comment //synopsys full_case) which has some cases that are not covered.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module m(in, out); input in; output out; reg out; always @in case (in) // Synopsys full_case 1'b0: out=1'b1; endcaseendmodule
W456
Message: Variable in the sensitivity list but not used in the block
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module ww(clk, a, b);input clk;input [2:0]a;output [2:0]b;reg [2:0]b;
always @ ( clk or a[0]) b <= a;endmodule
W459
Message: Constant is extended to the implied width of 32 bits
DescriptionLeda fires for this rule when it detects that the size of the basic constant is not defined. To solve this problem, set the size of the constant
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w459; integer i;
initial i = 'b0;
endmodule
W464
Message: Unrecognized synthesis directive
DescriptionLeda flags this rule if it any unrecognized synthesis directive used in the design. This rule is flagged for all synthesis directives that DC does not supports.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
module test (input wire reset, clk, D, output reg Q);
always@(posedge clk or reset) // synopsys rule_testing //unsupported synthesis directive by DCbeginif(!reset) Q <= 1'b0;else Q <= D;end
endmodule
W467
Message: '?' in based number constant
DescriptionLeda fires for this rule if it finds a constant with a value including a ?, (even if the constant is used in a case item of a casex/casez statement).
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w467 (i); output i; assign i = 1'b?;
endmodule
W468
Message: Index variable is too short
DescriptionLeda fires for this rule if it detects that some bits of the bus cannot be reached because the index variable is too small. To solve this problem, make the index variable bigger.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:module w468( clock,enable,i,DI,memory); input clock,enable; input [0:2] i; //W468, index variable i is too short input DI;
output [0:8] memory; reg [0:8] memory; //memory cellsalways @(posedge clock) begin
if(~enable) memory[i] <= DI ; endendmodule
W473
Message: A port without range is re-declared with a range
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
input i;wire [3:0] i; //W473, i was declared as input without a range
W478
Message: Bad loop initialization statement
DescriptionLeda fires for this rule when it finds an incorrect initial assignment in a for statement.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w478 (clk); input clk; reg [7:0] r1; always @ clk begin
for ({r1[0],r1[2:1]} = 0; r1 < 10; r1 = r1 + 1) begin endfor (r1[2:1] = 0; r1 < 10; r1 = r1 + 1) begin endfor (r1[1] = 0; r1 < 10; r1 = r1 + 1) begin end
endendmodule
W479
Message: Bad loop step statement
DescriptionLeda fires for this rule when it finds an incorrect step assignment in a for statement.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:module w479 (CLK);input CLK;reg [7:0]r1;always @(CLK) begin for (r1 = 0; r1 < 10; {r1[0],r1[2:1]} = r1 + 1) begin end for (r1 = 0; r1 < 10; r1[2:1] = r1 + 1) begin end for (r1 = 0; r1 < 10; r1[1] = r1 + 1) begin endendendmodule
W483
Message: Assigning to self. This could imply a latch in synthesis
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w483 (in, sel, out); input in, sel; output out;
wire in, sel; reg tmp;
assign out = tmp; always @ ( sel or in ) case(sel) 1'b0 : tmp = in; 1'b1 : tmp = tmp; //W483 endcase
endmodule
W484
Message: Possible loss of carry/borrow in addition/subtraction
Description
This rule fires when Leda detects an operand whose left-hand side is smaller than right-hand side. It flag a warning for conditional expressions in declarations except those whose condition is a unary operations | or &. For example wire A = (&B)?C:D;
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
module test(in1,in2,out);input in1, in2;output out;wire in1, in2;wire out;
assign out = in1 + in2; //W484, one-bit signalsendmodule
W485
Message: Non-negative (reg) is compared to 0
DescriptionBecause the reg is non-negative, there is no need to compare it to 0.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w485 (out); output out; reg out; reg r1;
always begin
if (r1 <= 0) //W485 out = 1;
endendmodule
W488
Message: Bus variable in the sensitivity list but not all its bits are used in the block
DescriptionLeda fires for this rule when it finds a bus variable in the sensitivity list, but not all its bits are used in the block. To solve this problem, put only the used bits in the sensitivity list.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w488 (portr, out); input [11:0] portr; output out; wire [11:0] portr; reg out; always @ ( portr ) begin
if ( portr[1] ==1'b0 ) //W488 out = 1'b1 ; endendmodule
W489
Message: Last function statement does not assign to the function
DescriptionLeda fires for this rule when it detects that the value of a function is not assigned in some condition.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w489 ( );function val; input sel; input in; reg el ; if (sel == 1'b1)
val = in; else
el = 1'b0; //W489, el = 1'b0 not assigned to valendfunctionendmodule
W490
Message: Tristate control expression is not a variable name
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module w490( bus, ctl, inbus ); output [7:0] bus; input [1:0]ctl; input [7:0] inbus; assign bus = (ctl[1] & ctl[0]) ? inbus : 8'hzz;endmodule
W491
Message: Extension of ? bits in a constant
DescriptionLeda fires for this rule when it finds that the most significant bit is ?. The most significant bit is extended up to the size of the expression.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: 8'b?
module w491(a, ctrl, y); input [7:0] a; input ctrl; output [7:0] y;
assign y = ctrl ? a : 8'b?; endmodule
W496
Message: Comparison to three state are treated as false
Description
For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, the result is a one-bit unknown value (X).
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: 1'bx
module w496 (in); input in; always @(in) begin
if (in == 1'bx) begin end endendmodule
W499
Message: Last function statement does not assign to all the bits of the function
DescriptionLeda fires for this rule when it finds that not all the bits of a function are assigned.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: function [15:0] f1
f1[7:0] = inp; module w499; function [15:0] f1; input [7:0]inp; begin
f1[7:0] = inp; end endfunctionendmodule
W502
Message: A variable in the sensitivity list is modified inside the block
DescriptionLeda fires for this rule when it finds a variable in the sensitivity list that is modified inside the block.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module DspIP (gate);output gate;reg gate;always @(gate) gate = 1'b1; //W502, gate is modifiedendmodule
W503
Message: An event variable is never triggered
DescriptionLeda flags this rule if it finds an event variable declared but never triggered. Event variables that are never triggered are redundant.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
//This testcase has an event temp which is not triggered anywhere.
module W503 (input in1, output out1);event temp; //FAIL
always @(temp)out1 = in1;
endmodule
W504
Message: Integer is used in port expression
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module m;integer i;mm u1(i); //W504endmodulemodule top (clk, reset, q);input clk, reset;output q;integer d;test t1 (clk, reset, d, q);endmodule
module test (clk, reset, d, q);input clk, reset, d;output q;reg q;
always @(posedge clk or posedge reset)if (reset == 1'b1)q <= 1'b0;elseq <= d;
endmodule
W505
Message: Mixed assignment styles (delay and nonblocking)
Description
It is good coding style to use either non-blocking or delay assignments in sequential blocks, but not both. If Leda finds a mixture of these types of assignments in the same always block, it issues this message.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(posedge clk) begin a = #1 b;
c <= d;end
W505_a
Message: Value assigned inconsistently - may not be synthesizable
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// This example has a signal assigned with both blocking and non-blocking assignments in same always block.
module mW_505 (input in1, in2, in3, output out1);reg temp;always @ (in1 or in2 | in3) if (in2) temp = in1; else temp <= in2;endmodule
// This example has a signal assigned with both blocking and non-blocking assignments in different always block.
module mW_505_1 (input in1, in2, in3, output out1); reg temp; always @ ( in1 ) temp = in1; always @ ( in2 ) temp <= in2;endmodule
W507
Message: Too many strengths for a pullup/pulldown gate (only one is needed)
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W509
Message: Defparam may not be synthesizable
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top;defparam k = 1; //W509endmodule
W521
Message: Not all the bits of the variable are in the sensitivity list
DescriptionSome of the bits of a vector that are used in a combinational always block are not present in the sensitivity list.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W526
Message: Nested ifs. Consider using case or casex statement instead
DescriptionIt is good coding practice to use a case statement instead of a sequence of nested if statements.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
if (a) if (b) $display (a and b); else $display (a and ~b);else if (b) $display (~a and b); else $display (~a and ~b);
// This can be rewritten as:
case ({a, b})2'b11: $display (a and b);
2'b10: $display (a and ~b);2'b01: $display (~a and b);2'b00: $display (~a and ~b);endcase
W527
Message: 'if' without an 'else' when one may be expected (dangling 'else' for a nested 'if'). Make sure the nesting is correct
Description
A dangling else in the code occurs when an else is missing inside a nested if-else statement. A dangling else can be misinterpreted, as the following example shows. To solve this problem, make sure the nesting is correct.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: if: (if (...) ... else ...)
module test(clk, a, b);input clk, a, b;
always @(posedge clk)if (a) if (b) $display ("a and b");else //W527, indentation is wrong. This else belongs to the second if.$display ("Not a");endmodule
W529
Message: `ifdef may not be supported by some synthesis tools
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: `ifdef word
`ifdef word //W529, ifdef cannot be synthesized`else`define word 7`endifmodule test;endmodule
W531
Message: Truncating leading zeros (or x's or z's)
Description
Leading zeros are truncated in a constant. For example, the construct 3'h0 causes this warning. This is a relatively benign situation; the more serious ones like 3'hf or 3'h00 generate different messages.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: assign a = 6'h11;
module test(a,b);output [5:0] a, b;wire [5:0] a, b ;assign a = 6'h11; //W531assign b = 6'hff; //no W531 //Truncation of extra bits: 6'hff -- W19
endmodule
W541
Message: Tristate is inferred
DescriptionLeda fires for this rule when it finds a variable assigned to a conditional expression in which one of the branches is Z, as shown in the example below.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
assign a = ctl ? b : 8'hzz;
W547
Message: Redundant case expression
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a)2'b01, 2'b01: // Harmless, possibly an oversight...
module test(gate, q);input gate;output q;reg q;
always @gate begincase (gate)1'b1,1'b1: q=1'b1; //W547, redundant case expressiondefault:q= 1'b0;endcaseend
always @gate begincase (gate)1'b1: q=1'b1;1'b0: q=1'b1; //no W547default:q= 1'b0;endcaseend
W548
Message: Synchronous flipflop is inferred
DescriptionLeda fires for this rule when it finds a flip-flop that has a synchronous reset.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module test(clk, reset, d, q);input clk, reset, d;output q;wire clk, reset, d;reg q;
always @(posedge clk) //W548, synchronous flip-flop is inferredif (reset == 1'b0)q <= 1'b0;else q <= d;
endmodule
W549
Message: Asynchronous flipflop is inferred
DescriptionLeda fires for this rule when it finds a flip-flop that has an asynchronous reset.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(posedge clk or posedge rst) if (rst) q <= 1'b0; else q <= d;
W550
Message: Mux is inferred
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: case (gate) ... endcase
module test(gate, q);input gate;output q;wire gate;reg q;
always @ (gate ) begincase (gate)1'b0:q= 1'b0;1'b1:q= 1'b1;endcase //W550, mux is inferred: case (gate) ... endcase endendmodule
W551
Message: full_case has a default clause
DescriptionA Synopsys full_case directive implies that only the cases that are specified can occur. Therefore, a default clause is redundant and can cause a discrepancy between simulation and synthesis.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (a[1:0]) //synopsys full_case 2'b00: ...; 2'b01: ...; 2'b10: ...; default: ...; //W551endcase
W554
Message: Unconventional assigning to a function. Consider using regular assignment statement ('=')
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
module top(clk,f);input clk;output f;function top;input x;
if (!x)assign top=1'b1; //W554, assign should not be used in functionelsedeassign top; //W555, deassign should not be used in function
endfunction
reg f;
always @clkf=top(1'b1);
endmodule
W555
Message: Unconventional deassigning to a function
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
function f;input i;begin assign f = i; //W554deassign f; //W555endendfunction
W556
Message: Complex condition expression. Could be as a result of wrong interpretation of operator precedence
Description Leda fires for this rule if the expression for a condition is too complicated. Sometimes a complex expression results from a misinterpretation of the operator precedence. A complex expression is any expression that contains an arithmetic
operator, shift operator.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
abc = a + c?d:e; //W556
// The intention was: abc = a + (c?d:e);
// But the result is: abc = (a + c) ? d : e;
W557
Message: Illegal use of range for scalar parameter
Description
Bit-selects or part-selects are taken from integer parameters. Such parameters should not be treated as vectors. To take a bit-select or part-select from a parameter, declare the parameter as a vector.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
parameter p = 12'hf23;
// parameter [11:0] p = 12'hf23; // This eliminates the warning
initial $display (p[2:1]); //W557
initial $display (p[0]); //W558
W558
Message: Illegal use of bit select for scalar parameter
Description
Bit-selects or part-selects are taken from integer parameters. Such parameters should not be treated as vectors. To take a bit-select or part-select from a parameter, declare the parameter as a vector.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
parameter p = 12'hf23;
// parameter [11:0] p = 12'hf23; // This eliminates the warning
initial $display (p[2:1]); //W557
initial $display (p[0]); //W558
W561
Message: Based number with 0 width is extended to the implied width of 32 bits
DescriptionLeda fires for this rule when it finds a based number with 0 width extended to the implied width of 32 bits.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg r;initialif (a==0'bz) // W561
W562
Message: Variable is assigned in both blocking and nonblocking assignments
DescriptionLeda fires for this rule when it finds a variable assigned in both blocking and non-blocking assignments. Statements like this cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(posedge clk or posedge rst) if (rst) q = 1'b0; // blocking assignment else
q <= d; // non-blocking assignment
W563
Message: Reduction of a single bit expression is redundant
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg r;...a = |r; //W563. this is equivalent to a = r;
W565
Message: Inferred a shift register
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(posedge clk) s = s<<1;
W570
Message: Inferred a counter
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
always @(posedge clk) s = s+1;
W575
Message: Logical NOT_OP operating on a vector
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg [3:0] r;reg s;...s = !r; //W575, should use s = (r!=4'b0000);
W576
Message: Multibit operand in a logical expression
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
reg [3:0] r, s;reg t;t = r && s; //W576, should be ôt=(r!=4'b0000)&&(s!=4'b0000);
W592
Message: Constant (parameter or specparam) is used in event control expression
DescriptionLeda fires for this rule when it finds a constant (parameter or specparam) used in an event control expression. To solve this problem, remove the redundant statement.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
parameter p=1;always @p //W592, p is constant...
W594
Message: Not all cases are covered in full case, but default case exists
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
case (exp) // Synopsys full_case case1: ... case2: ... ... default:endcase
W599
Message: This construct is not supported by Synopsys
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W601
Message: The loop index is being modified
Description
Leda fires for this rule when it finds a loop index variable being modified. A loop index is typically not supposed to be modified inside the loop. In fact, some languages do not allow this. Leda checks to make sure the loop index is not modified, except in the loop increment statement.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example:
for (i = 0; i < 8; i = i + 1) begin i = i + 2;end
W631
Message: Assigning to self. This is harmless but can reduce simulation speed
Description None.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
W639
Message: For synthesis, operands of a division or modulo operation need to be constants
DescriptionLeda fires for this rule when it finds a statement that cannot be synthesized.
Policy VERILINT
Ruleset CHECKER_ERROR
Language Verilog
Type Block-level
Severity Warning
Example
The following example of invalid Verilog code exhibits this problem:
// Example: if (a%2 == 1)
module test(clk, a, b);input clk, a;output b;reg b;always @(posedge clk)if (a%2 == 1) //W639, detect variable b <= 1'b0;endmodule
Example
The following example of invalid Verilog code exhibits this problem:
// Example: always @ (posedge clk & a[1:0])
module w17(clk, a, b);input clk;input [2:0]a;