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VLSI DesignLecture 2(MOSFET Structure)
Waqar Ahmad
Department of Electrical Engineering
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Silicon LatticeTransistors are built on a silicon substrate
Silicon is a Group IV materialForms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
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DopantsSilicon is a semiconductor
Pure silicon has no free carriers and conductspoorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
VLSI Design 3
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p-n Junctions
A junction between p-type and n-type
semiconductor forms a diode.Current flows only in one direction
p-type n-type
anode cathode
VLSI Design 4
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The MOS Transistor
How old is the idea?
The first experimental observation of the surface
and its impact on the electric current was
disclosed in the paper The action of light on
Selenium by W. G. Adams and R. E. Day in the
Proceeding of Royal Society in 1876.
VLSI Design 5
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Field effect control device proposed by J. Lilienfield
1928
VLSI Design 6
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Physical structure of the enhancement-typeNMOS transistor
VLSI Design 7
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3-D perspective
Polysilicon Aluminum
VLSI Design 8
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L = 0.1 to 3 m cross-section.Typically, W= 0.2 to 100 m, and the
thickness of the oxide layer (tox) is in
the range of 2 to 50 nm.
VLSI Design 9
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MOS Transistor Gate oxide body stack looks like a capacitor
Gate and body are conductors SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
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MOS Transistors - Types and Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOSEnhancement NMOS
PMOS
Depletion
Enhancement
B
NMOS with
Bulk Contact
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nMOS operation
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
g=0: When the gate is at a low voltage (VGS < VTN):
p-type body is at low voltage source and drain-junctions diodes are OFF
transistor is OFF, no current flows
g=1: When the gate is at a high voltage (VGS V TN):
negative charge attracted to body
inverts a channel under gate to n-type
transistor ON, current flows, transistor
can be viewed as a resistor
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nMOS pass 0 more strongly than 1
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
Why does 1 pass degraded?
VLSI Design 13
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pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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pMOS operationSiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
g=0: When the gate is at a low voltage (VGS < VTP):
positive charge attracted to body inverts a channel under gate to p-type
transistor ON, current flows
g=1: When the gate is at a high voltage (VGS V TP):
negative charge attracted to body source and drain junctions are OFF
transistor OFF, no current flows
VLSI Design 15
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pMOS pass 1 more strongly than 0SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
Why does 0 pass degraded?
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Applying a Small VDS
VDS causes a current (ld) to flow through source and drain. Conductance of
the channel is proportional to the excess gate voltage VGS above Vt
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Channel Formation
VLSI Design 19
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Operation as VDS Is Increased
Channel depth depends on this voltage
Channel is no longer of uniform depth; Channel will take the tapered form shown:
Deepest at the source end and shallowest at the drain end.
As VDS is increased, the channel becomes more tapered and its resistance
increases correspondingly
VLSI Design 20
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Cross-section of a CMOS IC
Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also
possible in which an n-type body is used and the n device isformed in a p well. Not shown are the connections made to the
p-type body and to the n well; the latter functions as the body
terminal for the p-channel device.
VLSI Design 21
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Transistor in Linear
VLSI Design 22
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Transistor in Saturation
VLSI Design 23
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The Threshold Voltage
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Operating the MOS Transistor in theSubthreshold Region
It has been found that for values of Vgs smaller than but close to Vt a
small drain current flows. (weak inversion)
In this subthreshold region of operation drain current is exponentially
related to Vgs.
In most digital applications, it is desirable to have faster current drop as
voltage falls below Vt.
The rate of current decline w.r.t. Vgs below Vt is thus a quality measure.
There are special, but a growing number of applications (mostly analog)
that make use of subthreshold operation.
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Channel Charge MOS structure looks like parallel plate capacitor while operating in
inversion (Gate oxide channel)
Qchannel = CV
C = Cg
= ox
WL/tox
= Cox
WL
V = Vgc Vt = (Vgs Vds/2) Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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Carrier velocity Charge is carried by e-
Carrier velocityv
proportional to lateral E-field between source anddrain
v= E called mobility
E = Vds
/L
Time for carrier to cross channel:
t= L / v
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nMOS Linear I-V Now we know
How much charge Qchannel is in the channel How much time teach carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
Q
I t
W VC V V V
L
VV V V
=
=
=
ox=W
CL
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nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt Now drain voltage no longer increases current
( )
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
=
=
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A model for manual analysis
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MOS Capacitances
Dynamic Behavior
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Dynamic Behavior of MOS Transistor
DS
G
B
CG DCG S
CSB CDBCGB
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Capacitance in CMOS Two conductors separated by an insulator have
capacitance
Overlap Capacitance
Gate to channel capacitance is very important
Creates channel charge necessary for operation
Source and Drain have (Junction) capacitance tobody
Across reverse-biased diodes Called diffusion capacitance because it is associated with
source/drain diffusion
Interconnect wires also have (distributed) capacitance
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Capacitive Device Model
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Capacitive Device Model CGS = CGSO + CGCS
CGD = CGDO + CGCD CGB = CGCB
CSB
= CSDiff
CDB = CDDiff
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Overlap Capacitance Source and Drain diffusion areas tend to extend
below gate oxide (lateral diffusion)
Effective channel length decreases by a factor
Creates parasitic capacitance between gate andsource/drain
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Overlap Capacitance CGSO = CGDO = CoxxdW
Cox =
xd xd
Ld
Polysilicon gate
Top view
Gate-bulkoverlap
Source
n+
Drain
n+W
tox
n+ n+
Cross section
L
Gate oxide
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Channel Capacitance Off region
No channel exists
Only gate to body capacitance
CG = CGCB = CoxWL
S D
G
CGC
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Channel Capacitance Linear region
Inversion layer formed Gate to body capacitance becomes zero
Capacitance equally distributed between drain andsource
CGCS = CGCD =
CoxWL
CG = CGCS + CGCD
S D
G
CGC
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Channel Capacitance Saturated region
Region under the channel is heavily inverted
Drain region of channel is pinched off
CGCD reduces to zero
CG = CGCS = CoxWLS D
G
CGC
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Diffusion (Junction) Capacitance Csb , Cdb
Two components
An area component
A sidewall component
Let diffusion capacitance isCg for contacted diffusion
Cg for un-contacted
Varies with process
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Diffusion (Junction) Capacitance
Cdiff =Cbottom +Csw
=CjLsW +Cswxj(2Ls +W)
WhereCj =Junctioncapacitanceperunitarea
Csw =Sidewallcapacitanceperunitarea
Bottom
Side wall
Side wallChannel
SourceND
Channel-stop implantNA1
Substrate NA
W
xj
L S
Type equation here.
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Parasitic Resistances
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
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Future Perspectives
25 nm FINFET MOS transistor
VLSI Design 44
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ReviewPolysilicon Gate
SiO2Insulator
n+ n+
p substrate
channel
Source Drain
n transistor
G
S
D
SB
L
W
G
S
D
substrate connectedto GND
p+ p+
n substrate
channel
Source Drain
p transistor
G
S
D
SB
Polysilicon GateSiO2
Insulator L
W
G
substrate connectedto VDD
VLSI Design 45
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References Contents of this lecture are courtesy of
Jan M. Rabaey Sherief Reda
Neil H. E. Weste
J. Abraham