Introduction toCMOS VLSI
Design
Lecture 19: Design for Skew
David Harris
Harvey Mudd CollegeSpring 2004
19: Design for Skew Slide 2CMOS VLSI Design
Outlineq Clock Distributionq Clock Skewq Skew-Tolerant Static Circuitsq Traditional Domino Circuitsq Skew-Tolerant Domino Circuits
19: Design for Skew Slide 3CMOS VLSI Design
Clockingq Synchronous systems use a clock to keep
operations in sequence– Distinguish this from previous or next– Determine speed at which machine operates
q Clock must be distributed to all the sequencing elements– Flip-flops and latches
q Also distribute clock to other elements – Domino circuits and memories
19: Design for Skew Slide 4CMOS VLSI Design
Clock Distributionq On a small chip, the clock distribution network is just
a wire– And possibly an inverter for clkb
q On practical chips, the RC delay of the wire resistance and gate load is very long– Variations in this delay cause clock to get to
different elements at different times– This is called clock skew
q Most chips use repeaters to buffer the clock and equalize the delay– Reduces but doesn’t eliminate skew
19: Design for Skew Slide 5CMOS VLSI Design
Exampleq Skew comes from differences in gate and wire delay
– With right buffer sizing, clk1 and clk2 could ideally arrive at the same time.
– But power supply noise changes buffer delays– clk2 and clk3 will always see RC skew
3 mm
1.3 pF
3.1 mmgclk
clk1
0.5 mm
clk2clk3
0.4 pF 0.4 pF
19: Design for Skew Slide 6CMOS VLSI Design
Review: Skew Impact
F1 F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
( )setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
≤ − + +
≥ − +
144424443
q Ideally full cycle isavailable for work
q Skew adds sequencingoverhead
q Increases hold time too
19: Design for Skew Slide 7CMOS VLSI Design
Cycle Time Trendsq Much of CPU performance comes from higher f
– f is improving faster than simple process shrinks– Sequencing overhead is bigger part of cycle
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elay
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19: Design for Skew Slide 8CMOS VLSI Design
Solutionsq Reduce clock skew
– Careful clock distribution network design– Plenty of metal wiring resources
q Analyze clock skew– Only budget actual, not worst case skews– Local vs. global skew budgets
q Tolerate clock skew– Choose circuit structures insensitive to skew
19: Design for Skew Slide 9CMOS VLSI Design
Clock Dist. Networksq Ad hocq Gridsq H-treeq Hybrid
19: Design for Skew Slide 10CMOS VLSI Design
Clock Gridsq Use grid on two or more levels to carry clockq Make wires wide to reduce RC delayq Ensures low skew between nearby pointsq But possibly large skew across die
19: Design for Skew Slide 11CMOS VLSI Design
Alpha Clock Grids
PLL
gclk grid
Alpha 21064 Alpha 21164 Alpha 21264
gclk grid
Alpha 21064 Alpha 21164 Alpha 21264
19: Design for Skew Slide 12CMOS VLSI Design
H-Treesq Fractal structure
– Gets clock arbitrarily close to any point– Matched delay along all paths
q Delay variations cause skewq A and B might see big skew A B
19: Design for Skew Slide 13CMOS VLSI Design
Itanium 2 H-Treeq Four levels of buffering:
– Primary driver– Repeater– Second-level
clock buffer– Gater
q Route aroundobstructions
Primary Buffer
Repeaters
Typical SLCBLocations
19: Design for Skew Slide 14CMOS VLSI Design
Hybrid Networksq Use H-tree to distribute clock to many pointsq Tie these points together with a grid
q Ex: IBM Power4, PowerPC– H-tree drives 16-64 sector buffers– Buffers drive total of 1024 points– All points shorted together with grid
19: Design for Skew Slide 15CMOS VLSI Design
Skew Toleranceq Flip-flops are sensitive to skew because of hard edges
– Data launches at latest rising edge of clock– Must setup before earliest next rising edge of clock– Overhead would shrink if we can soften edge
q Latches tolerate moderate amounts of skew– Data can arrive anytime latch is transparent
19: Design for Skew Slide 16CMOS VLSI Design
Skew: Latches
Q1
L1
φ1
φ2
L2 L3
φ1 φ1φ2
CombinationalLogic 1
CombinationalLogic 2
Q2 Q3D1 D2 D3
( )
( )
sequencing overhead
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
2
,
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
Tt t t t
≤ −
≥ − − +
≤ − + +
123
2-Phase Latches
( )
( )
setup skew
sequencing overhead
hold skew
borrow setup skew
max ,pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
≤ − + − +
≥ + − +
≤ − +
1444442444443Pulsed Latches
19: Design for Skew Slide 17CMOS VLSI Design
Dynamic Circuit Reviewq Static circuits are slow because fat pMOS load inputq Dynamic gates use precharge to remove pMOS
transistors from the inputs– Precharge: φ = 0 output forced high– Evaluate: φ = 1 output may pull low
A B
Yφ
C DY
A B C D
A
B
C
D
19: Design for Skew Slide 18CMOS VLSI Design
Domino Circuitsq Dynamic inputs must monotonically rise during
evaluation– Place inverting stage between each dynamic gate– Dynamic / static pair called domino gate
q Domino gates can be safely cascaded
A
W
φ
B
X
domino AND
dynamicNAND
staticinverter
19: Design for Skew Slide 19CMOS VLSI Design
Domino Timingq Domino gates are 1.5 – 2x faster than static CMOS
– Lower logical effort because of reduced Cin
q Challenge is to keep precharge off critical pathq Look at clocking schemes for precharge and eval
– Traditional schemes have severe overhead– Skew-tolerant domino hides this overhead
19: Design for Skew Slide 20CMOS VLSI Design
Traditional Domino Cktsq Hide precharge time by ping-ponging between half-
cycles– One evaluates while other precharges– Latches hold results during precharge
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tic
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amic
Latc
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clk
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tic
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amic
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tatic
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amic
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tic
Dyn
amic
Latc
h
Sta
tic
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amic
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tic
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amic
Dyn
amic
clk clk clk clk clk
clk
clk
tpdq tpdq
2pd c pdqt T t= −
19: Design for Skew Slide 21CMOS VLSI Design
Clock Skewq Skew increases sequencing overhead
– Traditional domino has hard edges– Evaluate at latest rising edge– Setup at latch by earliest falling edge
Sta
tic
Dyn
amic
Latc
hclk
Sta
tic
Dyn
amic
clkD
ynam
icclk clk
Sta
tic
Dyn
amic
Latc
h
Sta
tic
Dyn
amic
Dyn
amic
clk clk clk clk
clk
clk
tskewtsetup
setup skew2 2pd ct T t t= − −
19: Design for Skew Slide 22CMOS VLSI Design
Time Borrowingq Logic may not exactly fit half-cycle
– No flexibility to borrow time to balance logic between half cycles
q Traditional domino sequencing overhead is about 25% of cycle time in fast systems!
Sta
tic
Dyn
amic
Latc
hclk
Sta
tic
Dyn
amic
clk clk
Sta
tic
Dyn
amic
Latc
h
Sta
tic
Dyn
amic
clk clk clk
clk
clk
tskewtsetup
19: Design for Skew Slide 23CMOS VLSI Design
Relaxing the Timingq Sequencing overhead caused by hard edges
– Data departs dynamic gate on late rising edge– Must setup at latch on early falling edge
q Latch functions– Prevent glitches on inputs of domino gates– Holds results during precharge
q Is the latch really necessary?– No glitches if inputs come from other domino– Can we hold the results in another way?
19: Design for Skew Slide 24CMOS VLSI Design
Skew-Tolerant Dominoq Use overlapping clocks to eliminate latches at phase
boundaries.– Second phase evaluates using results of first
a
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tic
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amic
φ1
Sta
tic
Dyn
amic
φ2
b c d
a
φ1
φ2
b
c
a
φ1
φ2
b
c
No latch atphase boundary
19: Design for Skew Slide 25CMOS VLSI Design
Full Keeperq After second phase evaluates, first phase prechargesq Input to second phase falls
– Violates monotonicity?q But we no longer need the valueq Now the second gate has a floating output
– Need full keeper to hold it either high or low
φ
weak fullkeepertransistors
f
XH
19: Design for Skew Slide 26CMOS VLSI Design
Time Borrowingq Overlap can be used to
– Tolerate clock skew– Permit time borrowing
q No sequencing overhead
tskew
Sta
tic
Dyn
amic
Sta
tic
Dyn
amic
Sta
tic
Dyn
amic
Dyn
amic
Sta
tic
Dyn
amic
Sta
tic
Dyn
amic
Sta
tic
Dyn
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Dyn
amic
Sta
tic
Sta
tic
φ1
φ2
φ1 φ1 φ1 φ1 φ1 φ2 φ2 φ2
Phase 1 Phase 2
toverlap
tborrow
pd ct T=
19: Design for Skew Slide 27CMOS VLSI Design
Multiple Phasesq With more clock phases, each phase overlaps more
– Permits more skew tolerance and time borrowing
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Sta
tic
Sta
tic
φ3
φ4
φ1 φ1 φ2 φ2 φ3 φ3 φ4 φ4
Phase 1 Phase 2 Phase 3 Phase 4
φ1
φ2
19: Design for Skew Slide 28CMOS VLSI Design
Clock Generation
clken
φ1
φ2
φ3
φ4
19: Design for Skew Slide 29CMOS VLSI Design
Summaryq Clock skew effectively increases setup and hold
times in systems with hard edgesq Managing skew
– Reduce: good clock distribution network– Analyze: local vs. global skew– Tolerate: use systems with soft edges
q Flip-flops and traditional domino are costlyq Latches and skew-tolerant domino perform at full
speed even with moderate clock skews.