Lecture 11, Advance Digital Design
Hassan Bhatti, Spring 2009
Today’s Topics
Simple Adder Architectures Efficient Adders Division Algorithms Multipliers Efficient Multipliers (Booth Multiplier, Wallace
Tree)
HALF ADDER
HALF Adder in Verilog
Half Adder Using Data Flow
Full Adder Architecture
FULL adder using Data Flow Model
Ripple Carry Adder
Ripple Carry Adder
Pipeline Adders: Single Stage
Single Stage Pipelining
Three Stage Pipeline Adder
Carry Select Adder
Uniform Stage Carry Select Adder
Non Uniform Stage Carry Select Adder
Non Uniform Stage Carry Select Adder
Non Uniform Stage Carry Select Adder
Carry Look Ahead Adder
Carry Look Ahead
Carry Look Ahead
Carry Look Ahead Adders
Carry Look Ahead Block
Delay of Carry Look Ahead
Delay of Carry Look Ahead
Implementation of Carry Look Ahead
Area and Delay of Adders
Conditional Sum Adder
Conditional Sum Adder
Conditional Sum Adder: Example
Conditional Sum Adder: Example 8-Bits
Conditional Sum Adder: Example 16-Bits
Dividers-1:
For Details See Chapter-6-7-4 Bernard Sklar, Digital Communication
Dividers-1: Verification of the Result
For Details See Chapter-6-7-4 Bernard Sklar, Digital Communication
Dividers-2
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design
Dividers-2: Example
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design
Divisors-2: Easy Circuit
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design
Divisors-2: Improved Circuit
Reference: Article 3-5 Hennesy,Patterson, Computer Organization and Design
Courtesy and Acknowledgement of Slides and Pictures Adder Architecture are Taken for Dr. Shoab
A. Khan Lectures