1
EEE 525: VLSI Design, L-01EEE 525: VLSI Design, L-01
Spring 2007, ASUYu (Kevin) Cao, [email protected], GWC 336
IntroductionIntroduction
EEE525, ASU, Y. Cao Lecture 01 - 2 -
HighlightHighlightCourse orientation– Objective, textbook, assignments, and grading policy
VLSI design– History, today, and tomorrow– Design flow: Integration and abstraction
Key design metrics: – Area, performance, power, reliability, and cost
Challenges and trend for nano-VLSIReading: Chapter 1Handout: the syllabus and schedule
2
EEE525, ASU, Y. Cao Lecture 01 - 3 -
Basic InformationBasic InformationInstructor: Y. Kevin Cao, GWC 336– Office hour: MW, 1:30-2:30pm; E-mail: [email protected]
Textbook: – CMOS VLSI Design: A Circuits and Systems Perspective, by
Neil H. E. Weste and David Harris
Other references: – Design of High-Performance Microprocessor Circuits, Edited by
A. Chandrakasan, et al.– Digital Integrated Circuits: A Design Perspective, by Jan M.
Rabaey, et al. (http://bwrc.eecs.berkeley.edu/IcBook/)
Lab at GWC 273, with TA availableLectures etc. are available at http://my.asu.edu
EEE525, ASU, Y. Cao Lecture 01 - 4 -
What will you learnWhat will you learnVLSI design knowledge that is both fundamental and practical, in the context of key design principles– ~40% overlapped with EEE 425; focus on VLSI system design
Pre-requisite: basic understanding of CMOS and digital circuits– Online students are required to have their own access to design tools
Content:
Further study: computer architecture, CAD, and analog design
ALU, memory, datapath, clock, power, I/O, CAD
CMOS, interconnect, inverter, logic styles
PracticalFundamentalDesign metrics
cost, performance,
power, and reliability
3
EEE525, ASU, Y. Cao Lecture 01 - 5 -
AssignmentsAssignmentsHomework (15%): exercise your learning– Totally five: three before Midterm and two after it– Part of them will be software labs
Project : design and optimization of a datapath circuit– Phase I (15%): schematic design with Spectre/SPICE– Phase II (15%): layout, extraction, and optimization– Two people per group, with balanced contribution– The load will be adjusted for online students– Grade is based on the ranking of design quality: speed, power,
area, layout, and report
Examination: evaluate your knowledge– One mid-term (25%): design fundamentals– Final (30%): majority of the final is from the second half
EEE525, ASU, Y. Cao Lecture 01 - 6 -
Grading PolicyGrading PolicyLetter grade depends on the relative distribution, with + and – (µ: average; σ: standard deviation)– A+: top 10%– A: > µ + 0.5·σ– A-: > µ– B+: > µ - 0.5·σ– B: > µ - σ– C: > µ - 1.5·σ– D: else
HW (15%), Project (30%), Midterm (25%), Final (30%)
4
EEE525, ASU, Y. Cao Lecture 01 - 7 -
HighlightHighlightCourse orientation– Objective, textbook, assignments, and grading policy
VLSI design– History, today, and tomorrow– Design flow: Integration and abstraction
Key design metrics: – Area, performance, power, reliability, and cost
Challenges and trend for nano-VLSIReading: Chapter 1Handout: the syllabus and schedule
EEE525, ASU, Y. Cao Lecture 01 - 8 -
The First Computing SystemThe First Computing SystemAbacus
(3000 B.C. – 300 A. D.)
by Chinese
and Mesoamerican
Size: > 10cm
Speed: your finger-run
Power: no sweating
Cost: home made
5
EEE525, ASU, Y. Cao Lecture 01 - 9 -
The First Electronic ComputerThe First Electronic Computer
ENIAC
(1946)
by U.S.A.
Size: 1800 ft2
Speed: 40 div./sec.
Power: 160kW
Cost: $486, 804.22
EEE525, ASU, Y. Cao Lecture 01 - 10 -
The First Transistor: A RevolutionThe First Transistor: A Revolution
Transistor
(1947)
by Bell Labs
Nobel Prize, 1951
Shockley, Bardeen, and Brattain
Much better scalability and reliability
6
EEE525, ASU, Y. Cao Lecture 01 - 11 -
The First Integrated CircuitThe First Integrated Circuit
Integrated Circuit
(1958)
by TI
Nobel Prize, 2000
Kilby
1 transistor, 3 resistors, and 1 capacitor
EEE525, ASU, Y. Cao Lecture 01 - 12 -
The First Microprocessor ChipThe First Microprocessor Chip4004 CPU
(1971)
by Intel
Size: ~ 9mm2,
2.3 K transistors @10µm
Speed: 1MHz
Design team: 3
7
EEE525, ASU, Y. Cao Lecture 01 - 13 -
The Pentium 4 CPUThe Pentium 4 CPU
P4 CPU (2002)
Size: ~217mm2, 42M @ 0.18µm
Speed: 2GHz
Design team: 1000
MOSFET
Interconnect
EEE525, ASU, Y. Cao Lecture 01 - 14 -
Moore’s LawMoore’s LawIn 1965, Gordon Moore (Intel) noted that the number of transistors on a chip doubled every 18 to 24 months.Prediction: semiconductor technology will double its effectiveness every 18 months
1 61 51 41 31 21 11 0
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG
2 OF
THE
NU
MB
ER O
FC
OM
PON
ENTS
PER
INTE
GR
ATE
D F
UN
CTI
ON
Electronics,
April 19, 1965
8
EEE525, ASU, Y. Cao Lecture 01 - 15 -
Moore’s Law in MicroprocessorsMoore’s Law in Microprocessors
Transistors
100K
1M
10M
100M
1000M
1980 1990 2000 2010Year Chip
Frequency (Hz)
80868086
8038680386
PentiumPentium
5M
200M
1.0G
3.2G
3.0µmTechnology Node
33M
1.0µm 0.35µm 180nm 50nm
ItaniumItanium
• Transistor counts: 2x / 2 years
• Channel length: 0.7 / 18 months
EEE525, ASU, Y. Cao Lecture 01 - 16 -
Clock FrequencyClock Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Freq
uenc
y (M
hz)
Doubles every2 years
Courtesy, Intel
• Clock frequency: 2x / 2 years
9
EEE525, ASU, Y. Cao Lecture 01 - 17 -
Evolution in ComplexityEvolution in Complexity
EEE525, ASU, Y. Cao Lecture 01 - 18 -
Die Size GrowthDie Size Growth
Courtesy, Intel
40048008
80808085
8086286
386486 Pentium ® procP6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
• Die Size: 14% / 2 years
or 2x in 10 years
10
EEE525, ASU, Y. Cao Lecture 01 - 19 -
Driving ForcesDriving ForcesTechnology scaling– Semiconductor device shrinks by 0.7x / generation
Circuit and System design“Cleverness”Functions per chip doubles every generation; chip cost does not increase significantly– Cost of a function decreases by 2x
On the other hand:– Design population does not double every two years…– Productivity per designer decreases due to
complexities of design and team management
EEE525, ASU, Y. Cao Lecture 01 - 20 -
Design AbstractionDesign Abstraction
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
11
EEE525, ASU, Y. Cao Lecture 01 - 21 -
Top-Down Design FlowTop-Down Design Flow
system softwaresystem software
platform / architectureplatform / architecture
systemssystemssystems
structuresstructuresstructures
materialsmaterialsmaterials
physicsphysicsphysics
circuitscircuits
application softwareapplication software
devices/interconnectdevices/interconnect
h = 3;
k = h; h >3;
Output
M1
k
h
M2
h < 3;
L A T C Hs a b it
s a b it#
T
s a p c h g #
EEE525, ASU, Y. Cao Lecture 01 - 22 -
Job of a VLSI DesignerJob of a VLSI DesignerDesign objectives:
Design knobs:– Architecture (gates/block, register count, etc)– Circuit style (static, dynamic, etc)– Circuit implementation (sizing, layout, VDD, etc.)– Physical design (placement, routing, etc.)
power
speed speed
low power
area/cost
speed/power/reliability
speed/powerreliable ultra-
low power
12
EEE525, ASU, Y. Cao Lecture 01 - 23 -
IC Design ToolsIC Design ToolsSynthesis– Micro-architectural, Logic, Automatic physical generation
Static Analysis– Design rule checking (DRC), Circuit parasitics extraction,
Timing analysis, Test generation
Dynamic Analysis– Architectural simulation, Logic, Circuit simulation (SPICE)
for speed and power, Test verification
Tool capability is limited and exploited by your physical understanding
EEE525, ASU, Y. Cao Lecture 01 - 24 -
HighlightHighlightCourse orientation– Objective, textbook, assignments, and grading policy
VLSI design– History, today, and tomorrow– Design flow: Integration and abstraction
Key design metrics: – Area, performance, power, reliability, and cost
Challenges and trend for nano-VLSIReading: Chapter 1Handout: the syllabus and schedule
13
EEE525, ASU, Y. Cao Lecture 01 - 25 -
Challenges in Future VLSIChallenges in Future VLSI
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability
• Main roadblocks: power, cost, and reliability
EEE525, ASU, Y. Cao Lecture 01 - 26 -
Power DissipationPower Dissipation
Year
Pow
er (W
atts
)
5KW 18KW
1.5KW 500W
40048080
8086 386486
Pentium® proc
0.1
1
10
102
103
104
105
1971 1974 1978 1985 1992 2000 2004 2008
Courtesy, Intel
• Power delivery and dissipation will be prohibitive
1µm 100nm 10nm10µmTechnology node
10-4
10-3
10-2
10-1
100
101
102
103
Pow
er (W
)
Switching
LeakageSource: Intel
14
EEE525, ASU, Y. Cao Lecture 01 - 27 -
Power DensityPower Density
40048008
8080
8085
8086
286386
486Pentium
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Source: Intel
Power/transistor switching goes down with technology scaling, but:
EEE525, ASU, Y. Cao Lecture 01 - 28 -
Innovative Design DemandedInnovative Design Demanded
Technology used to be the answer for this trouble; but, no candidate around the corner
1950
IBM360IBM370
IBM3033Fujitsu
M380
IBM3084IBM4381
CDC Cyber 205IBM3090
Fujitsu M-780
NTTIBM 3090S
Fujitsu VP2000
IBM ES9000
Pentium IIApache
IBM RY4
IBM RY6Pulsar
IBM RY7
IBM RY5
1960 1970 1980 1990 2000 20100
2
4
6
8
10
12
14
Mod
ule
Hea
t Flu
x (w
/cm
2 )
Year of Announcement
Bipolar CMOS
15
EEE525, ASU, Y. Cao Lecture 01 - 29 -
Cost of Integrated CircuitsCost of Integrated CircuitsNRE (non-recurrent engineering) costs– design time and effort, mask generation– one-time cost factor
Recurrent costs– silicon processing, packaging, test– proportional to volume– proportional to chip area
EEE525, ASU, Y. Cao Lecture 01 - 30 -
NRE CostNRE Cost
16
EEE525, ASU, Y. Cao Lecture 01 - 31 -
Recurrent CostRecurrent Cost
1µm 100nm 10nm10-9
10-8
10-6
10-5
10-4
10-7
Dollar
Cost per Transistor
Wafer size goes up to 12” (300mm)Cost per production line increases to ~$5 BillionDefect rate also explodes with technology scaling
EEE525, ASU, Y. Cao Lecture 01 - 32 -
ReliabilityReliabilityProcess variationsDynamic uncertainties:– Temperature– Power supply (Ldi/dt noise)– Crosstalk– Soft error
138 W/cm2
All degrade your yieldand waste resource
17
EEE525, ASU, Y. Cao Lecture 01 - 33 -
Design Trend I: IntegrationDesign Trend I: IntegrationIntegrate various technologiesIntegral design solutions
Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
EEE525, ASU, Y. Cao Lecture 01 - 34 -
Design of NanoelectronicsDesign of Nanoelectronics
???Carbon Nanotube
FET
1947 1958
1993 2006
18
EEE525, ASU, Y. Cao Lecture 01 - 35 -
Design Trend II: ParallelismDesign Trend II: Parallelism
Concurrency for better reliability, programmability, and cost factor Examples:– Multiple core processor– Regular array structures
EEE525, ASU, Y. Cao Lecture 01 - 36 -
Digital IC have come a long way and still have quite some potential left for the coming decades:– Computation and Communications– Automobile (30-70 chips/car now)– Consumer electronics– Energy conservation– Security and intelligence– Biomedical– Much more with your innovation
Broader ApplicationsBroader Applications
19
EEE525, ASU, Y. Cao Lecture 01 - 37 -
SummarySummaryEEE 525: design fundamentals and practices underlying the VLSI system integrationMetrics: area, speed, power, reliability, and costChallenges ahead: power, cost, and reliabilityClear understanding from a circuit perspectiveContact: [email protected] hours: MW 1:30-2:30pm, GWC 336Web access: http://my.asu.edu