Lecture 13
MOS Electrostatics
Outline
• Introduction to MOS structure
• Electrostatics of MOS in thermal equilibrium
• Electrostatics of MOS with applied bias
Key questions
What is the big deal about the metal-oxide-
semiconductor structure?
What do the electrostatics of the MOS structure look
like at zero bias?
How do the electrostatics of the MOS structure get
modified if a voltage is applied across its terminals?
3
1. Introduction Metal Oxide Semiconductor structure
4 Fig by MIT OpenCoursesWare
MOS at the heart of the electronics revolution:
• Digital and analog functions
– Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
is key element of Complementary Metal Oxide Semiconductor
(CMOS) circuit family
• Memory function
– Dynamic Random Access Memory (DRAM)
– Static Random Access Memory (SRAM)
– Non Volatile Random Access Memory (NVRAM)
• Imaging
– Charge Coupled Device (CCD) and CMOS cameras
• Displays
– Active Matrix Liquid Crystal Displays (AMLCD)
5
6
Why the gate is made of
polysilicon instead of metal?
In the early days of PMOS technology, a metal gate was used.
• it is difficult to align the metal over the channel precisely.
•An offset creates a non-functioning transistor (either a short or
an open)
Today
•A polysilicon material deposited before the source and drain
diffusions is introduced to serve as a gate.
•Source and drain is easy to align gate.
•Gate is heavily doped to keep its resistance low and supposed
to behave like a metal.
Metal: does not tolerate volume charge
–⇒ charge can only exist at its surface
Oxide: insulator and does not have volume charge
–⇒ no free carriers, no dopants
Semiconductor: can have volume charge
–⇒ Space charge region (SCR)
In thermal equilibrium we assume Gate contact is shorted
to Bulk contact. (i. e, VGB = 0V)
-- Thermal equilibrium can’t be established through oxide;
need wire to allow transfer of charge between metal and
semiconductor.
7
8
Technology development
Horizontal device dimensions (channel length,
source and drain area) are smaller and smaller
• to maximize circuit density
•To improve high-speed performance
Vertical device dimensions are smaller and
smaller
• maintain field levels
2. MOS Electrostatics in equilibrium
9
Idealized 1D structure:
10
We interconnect gate to substrate to let VD=0 (the applied voltage is zero),
which is a necessary condition for equilibrium.
Since gate is heavily doped with donors, 550 mVn
The potential of p-type substrate is ln ap th
i
NV
n
So the electric field E0 is positive, resulting positive charges on the bottom of the
gate and negative charges in the p-type silicon underlying the gate oxide to
balance it.
An intuitive understanding of depletion region is the positive charges of the gate
repel holes and leave the immobile negatively-charged acceptors.
Fig Qualitative picture of charge distribution in an MOS
capacitor with p-type substrate in thermal equilibrium
For most metals on p-Si, equilibrium achieved by electrons
flowing from metal to semiconductor and holes from
semiconductor to metal:
11
2
0 0Remember : in p n
Fewer holes near Si/SiO2 interface
Ionized acceptors exposed (volume charge)
Space Charge Density
• In semiconductor: space charge
region close Si /SiO2 interface –
can use depletion approximation
• In metal: sheet of charge at metal
/SiO2 interface
• Overall charge neutrality
12
;
;
0;
0 ;
ox
ox
do
do
x t
t x
x x
x x
0
0
0
( ) 0
( )
( ) 0
G
a
Q
x
x qN
x
Electric Field
Integrate Poisson’s equation
At interface between oxide and semiconductor, there is a
change in permittivity ⇒ change in electric field
13
2
1
' '
2 1
1( ) ( ) ( )
x
o o
x
E x E x x dx
ox ox s sE E
3ox s
s ox
E
E
Start integrating from deep inside
semiconductor:
14
;
'
( ) 0
10 ; ( ) ( ) ( )
0; ( ) ( 0 )
; ( ) 0
do
do o
x
ado o o do a do
s sx
s a doox o o
ox ox
ox
x x E x
qNx x E x E x qN dx x x
qN xt x E x E x
x t E x
Electrostatic Potential
In QNRs, no and po are known ⇒ can determine φ
15
0lni
nkT
q n 0ln
i
pkT
q n
0
0
in p-QNR: ln
in n -gate:
aa p
i
d g n
NkTp N
q n
n N
With @no=po=ni0
16
Built-in potential:
ln aB g p n
i
NkT
q n
To obtain φo(x), integrate Eo(x); start from deep inside
semiconductor bulk:
17
2
1
' '
2 1( ) ( ) ( )
x
o o o
x
x x E x dx
2
, ,2
a do a do oxB B o ox o
s ox
qN x qN x tV V
a doox
ox
qN xE
a do
s
s
qN xE
18
Surface potential (0)s
;
' '
( )
0 ; ( ) ( ) ( )
do
do o p
x
ado o o do do
sx
x x x
qNx x x x x x dx
' 2( ) ( )2
ao p do
s
qNx x x
2 0 (0) ( )2
ao p do
s
qNAT x x
20; ( ) ( ) ( )2
; ( )
a a doox o p do
s ox
ox o n
qN qN xt x x x x
x t x
Still do not know xdo⇒need one more equation
Potential difference across structure has to add up to φB:
Solve quadratic equation:
where Cox is the
capacitance per unit
area of oxide
19
2
, ,2
a do a do oxB B o ox o
s ox
qN x qN x tV V
oxox
ox
Ct
2
2
2
21 1
21 1
s ox Bdo ox
ox s a do
s ox B
ox s a
x tq N t
C
C q N
20
rewrite
where γ is body factor coefficient
2
2 2
2 41 1 1 1s ox B s B
do ox
ox s a do ox
x tq N t C
12 s a
ox
qNC
1/2units: V
21
20 3 17 3
7 2
1/2
:
10 , 10 , 8
550 420 970
4.3 10 /
0.43
91
d a ox
B
ox
do
Numerical example
N cm N cm t nm
mV mV mV
C F cm
V
x nm
There are also contact potentials
⇒ total potential difference from contact to contact is zero!
22
3. MOS with applied bias VGB
Apply voltage to gate with respect to semiconductor:
23
Electrostatics of MOS structure affected
⇒ potential difference across entire structure now ≠ 0
24
How is potential difference accommodated?
Potential can drop in:
•gate contact
•n+-polysilicon gate
• oxide
•semiconductor SCR
•semiconductor QNR
•semiconductor contact
Potential difference shows up across oxide and SCR in
semiconductor
• Oxide is an insulator
⇒ no current anywhere in structure
• In SCR, quasiequilibrium situation prevails
⇒ New balance between drift and diffusion
25
2
inp n
Apply VGB>0: potential
difference across structure
increases
⇒ need larger charge dipole
⇒ SCR expands into
semiconductor substrate:
Simple way to
remember: with VGB>0,
gate attracts electrons
and repels holes.
26
Qualitatively, physics unaffected by application of VGB >0.
Use mathematical formulation in thermal equilibrium, but:
For example, to determine xd(VBG):
27
B B GBV
2
( ) ( )
( ) ( )
2
B GB B GB ox GB
a d GB a d GB ox
s ox
V V V V V
qN x V qN x V t
28
2
2
2 ( )( ) 1 1
( ) (0)
s ox B GBd GB
ox s a
a d GBs p
s
C Vx V
C q N
qN x V
GB dV x
gives & concentration at the surfaces n p
Summary of Key Concepts
• Charge redistribution in MOS structure in thermal
equilibrium
– SCR in semiconductor
–⇒ built in potential across MOS structure.
• In most cases, we can use depletion approximation in
semiconductor SCR
• Application of voltage modulates depletion region
width in semiconductor
–⇒No current flows
29
MOS Electrostatics(II)
Outline
•Overview of MOS electrostatics under bias
•Depletion regime
•Flatband
•Accumulation regime
•Threshold
•Inversion regime
30
Key questions
Is there more than one regime of operation of the MOS
structure under bias?
What does ”carrier inversion” mean and what is the big deal
about it?
How does the carrier inversion charge depend on the gate
voltage?
31
32
1. Overview of MOS electrostatics under bias
33
Application of bias:
• Built-in potential across MOS structure increases from φB
to φB + VGB
• Oxide forbids current flow
⇒ – J=0 everywhere in semiconductor
– Need drift = diffusion in SCR
• Must maintain boundary condition at Si/SiO2 interface
– Eox / Es ≈ 3
How can this be accommodated simultaneously?
⇒ quasi equilibrium situation with potential build-up across
MOS equal to φB + VGB
34
Important consequence of quasiequilibrium:
⇒ Boltzmann relations apply in semiconductor
[they were derived starting from Jn = J p =0]
( )/
( )/
2
( )
( )
at every x
q x kT
i
q x kT
i
i
n x n e
p x n e
and
np n
35
2. Depletion regime
For VGB>0, metal attracts electrons and repels holes
⇒ Depletion region widens
For VGB<0, metal repels electrons and attracts holes
⇒ Depletion region shrinks
36
37
In depletion regime, all results obtained for thermal
equilibrium apply if φB →φB+VGB.
Depletion region thickness:
Potential drop across semiconductor SCR:
Surface potential
Potential drop across oxide:
22 ( )( ) 1 1s ox B GB
d GB
ox s a
C Vx V
C qN
2
( )2
a dB GB
s
qN xV V
(0) ( )p B GBV V
( ) a d oxox GB
ox
qN x tV V
38
3. Flatband
At a certain negative VGB,
depletion region is wiped out
⇒ Flatband
Flatband Voltage:
= ( )
GB FB B
pN
V V
39
4. Accumulation regime
If VGB < VFB accumulation of holes at
Si/SiO2 interface
40
5. Threshold
Back to VGB>0.
For sufficiently large VGB > 0, electrostatics change when n(0)
= Na⇒ threshold -Strong Inversion.
Beyond threshold, cannot neglect contributions of electrons
towards electrostatics.
Let’s compute the voltage
(threshold voltage) that
leads to n(0) = Na.
Key assumption: use
electrostatics of depletion
(neglect electron
concentration at threshold).
41
Computation of threshold voltage.
Three step process: • First, compute potential drop in semiconductor at threshold.
Start from:
Hence:
(0)/(0)
(0) :
(0) (0) ln ln
T
T
q kT
i
GB T
apV
i iV
n n e
Solve for at V V
NkT n kT
q n q n
( ) 2B T pV V
42
• Second, compute potential drop in oxide at threshold.
Obtain xd(VT) using relationship between VB and xd in depletion:
Solve for xd(VT):
Then:
2 ( )( ) 2
2
a d TB GB T p
s
qN x VV V V
max
2 ( 2 )( )
s p
d T d
a
x V xqN
( )( ) ( ) 2a d T
ox T ox T ox ox p
s
qN x VV V E V t t
43
Finally, sum potential drops across structure.
1( ) ( ) 2 2 ( 2 )T B B T ox T p s a p
ox
V V V V V qNC
44
Key dependencies:
• If Na ↑⇒VT ↑. The higher the doping, the more voltage
required to produce n(0) = Na
• If Cox ↑ (tox ↓) ⇒VT ↓. The thinner the oxide, the less
voltage dropped across the oxide.
1 2 2 ( 2 )
T
GB T FB p s a p
ox
Solve for V
V V V qNC
45
6. Inversion
What happens for VGB > VT?
More electrons at Si/SiO2 interface than acceptors
⇒ inversion.
46
Want to compute QN vs. VGB [charge control relation]
Make sheet charge approximation: electron layer at Si/SiO2
is much thinner than any other dimension in problem (tox, xd).
Electron concentration at Si/SiO2 interface modulated by VGB
⇒ VGB ↑→ n(0) ↑→ |QN| ↑ :
Field effect control of mobile charge density!
[essence of MOSFET]
47
Charge Control Relation
To derive the charge control relation, let’s look at the
overall electrostatics:
48
49
Key realization:
Hence, as VGB ↑ and φ(0) ↑ , n(0) will change a lot, but |QB|
will change very little.
=> In approximation, QB will not increase with VGB when it
operates beyond threshold (VGB>VT).
(0)
(0)q
kTin n e
(0)
(0)q
kTnQ n e
(0)BQ 2 ( )(0)
2
B a d
a d GBs p
s
Q qN x
qN x V
50
Several consequences:
• xd does not increase much beyond threshold:
• VB does not increase much beyond VB(VT) =-2φP (a thin
sheet of electrons does not contribute much to VB.):
s p In threshold
,max
2 ( 2 )( ) ( )
s p
d d T d
a
x inv x V xqN
( ) ( ) 2B B T pV inv V V
51
• All extra voltage beyond VT used to increase inversion charge
Qn. Think of it as capacitor:
– Top plate: metal gate
– Bottom plate: inversion layer
Though QN is not zero for VGB=VT, it is very small as shown in the
figure of next page.
( ) For N ox GB T GB T
Q CV
Q C V V V V
Existence of QN and control over QN by VGB
Key to MOS electronics
52
MOS Electrostatics(III)
MOS Capacitor
Electrons flow
Holes flow
MOS Electrostatics in equilibrium
-p type substrate
54
Fig Qualitative picture of charge distribution in an MOS capacitor
with p-type substrate in thermal equilibrium.
Operation regimes
under bias
55
56
1. Accumulation (VGB < VFB )
QG=Cox(VGB-VFB)
where
2. Depletion ( VFB<VGB < VT)
where
G B a d GBQ Q qN x V
3. Inversion (VGB > VT)
QG=-QN(VGB)-QBmax
where
max maxB a dQ qN x
Gate charge on a
p-type substrate
Fig (a) Gate charge as a function of gate-bulk voltage
for an MOS capacitor with a 150 Ǻ-thick gate oxide
and a substrate doping Na=1017cm-3
( )FB pNV
22 ( )( ) 1 1s ox B GB
d GB
ox s a
C Vx V
C qN
12 2 ( 2 )T FB p s a p
ox
V V qNC
( )N ox GB TQ C V V
max
2 ( 2 )s p
d
a
xqN
MOS capacitor on
a p-type substrate
Capacitor as the
slope of qG(VGB)
57
Fig (a) Gate charge as a function
of gate-bulk voltage for an MOS
capacitor on a p-type substrate
with a 150 Ǻ-thick gate oxide and
a substrate doping Na=1017cm-3
(b) Capacitance as a function
of gate-bulk voltage, found by
graphically differentiating (a).
GB
G
GB V
dqC
dv
58
Gate charge for:
Accumulation
depletion inversion
2
2
( )
2 ( )( ) 1 1 ( )
2 ( )( ) 1 1
G ox GB FB GB FB
s a ox GB FBG B GB FB GB Tn
ox s a
s a ox Tn FBG ox GB Tn Tn GB
ox s a
Q C V V for V V
q N C V VQ Q V V V V
C q N
q N C V VQ C V V for V V
C q N
( )
GB FB
ox GB FB ox GB FB
GB V V
dC C v V C for V V
dv
( )
Tn GB
ox GB Tn ox
GB V V
dC C v V C
dv
22 ( )1FB GB Tn
G ox
GB V V V ox GB FB
s a
dq CC
dv C V V
q N
59
ox b
ox b
C CC
C C
In depletion region, MOS
capacitor is the capacitances
Cox and Cb in series.
22 ( )1FB GB Tn
G ox
GB V V V ox GB FB
s a
dq CC
dv C V V
q N
22 ( )( ) 1 1s ox B GB
d GB
ox s a
C Vx V
C qN
( )=
( ) 1( )
sox
d GBoxFB GB Tn
ox sd GB ox
s d GB
Cx VC
C for V V VC
x V Cx V
The capacitance Cb of the depletion region
( )
sb
d GB
Cx V
MOS Electrostatics in equilibrium
n-type substrate
60
Fig MOS capacitor with n-type substrate. VGB=0
for investigate capacitor in thermal equilibrium
61
Built in potential for
Flat band voltage
Threshold voltage
17 310dN cm
550 420 130nnmV mV mV
12 2 (2 )Tp FB n s a n
ox
V V qNC
( ) 130FB nnV mV
62
Fig Gate charge as a function of gate-bulk voltage
for an MOS capacitor an n-type substrate with
doping Nd=1017cm-3 and a 150 Ǻ–thick gate oxide.
( ) G ox GB FB GB FBQ C V V for V V
( ) ( )G GB B a d GBQ V Q qN x V
,max ,max( ) G p B ox GB Tp B GB TpQ Q Q C V V Q for V V
Example 1
Consider a MOS capacitor with tox=2 × 10-6 cm on a p-type substrate with
acceptor concentration Na=5 × 1016cm-3.
a) Find the electric field in the oxide and the charge per unit area in the
substrate for VGB=-2.5V.
b) Find the numerical value of the depletion width and depletion charge
when the capacitor is biased in the inversion region.
c) Find the electric field in the oxide and the inversion-layer electron charge
for VGB=2.5V.
d) Electric fields with magnitudes greater than Eox,max=5 × 106 V/cm will
cause irreversible damage to the gate oxide. Find the permissible rage of
gate-bulk voltages.
63
64
(A) Solution
The first step is to determine the operation regime
(accumulate depletion or inversion regime).
The flatband voltage:
The threshold voltage:
We substitute the permittivity of silicon and SiO2
( ) (550 60 log )
550 ( 402 ) 952
aFB B pn
i
NV mV mV
n
mV mV mV
2 ( 2 )2
s a p
Tn FB n
ox
qNV V
C
12 131.04 10 / and 3.45 10 / oxs ox ox
ox
F cm F cm Ct
19 12
13 6
2 (1.6 10 ) (1.04 10 / ) ( 2 0.4 )0.95 2( 0.4 )
(3.45 10 / ) / (2 10 )
0.95 2( 0.4 ) 0.67 0.52
Tn
C F cm VV V V
F cm cm
V V V V
65
Since , MOS operates in accumulation regime.
The electric field from the accumulation charge is
2.5 0.95GB FBV V V V
5
6
( ) 2.5 0.55 ( 0.4 )7.8 10 /
2 10
GB pox nox
ox ox
VV V V VE V cm
t t cm
The charge in the substrate consists of accumulated
holes 13
6
7 2 7 7 2
2
3.45 10 /( ) [ 2.5 ( 0.95 )]
2 10
/1.72 10 / ( 1.55 ) 2.67 10 2.67 10 /
G ox GB FB
F cmQ Q C V V V V
cm
C VF cm V V C cm
cm
66
(B) Solution
In inversion, the potential drop across the depletion region is
max
125max
max 19 16 3
can be solved as:
2 2 1.04 10 / 0.81.44 10
1.6 10 5 10
d
s Bd
a
x
V F cm Vx cm
qN C cm
,max 2( 0.4 ) 0.8B s p p pV V V
2
max,max
1Since
2
a dB
s
qN xV
The bulk charge in the depletion region is
19 16 3 5
max max
7 2
(1.6 10 )(5 10 ) 1.44 10
1.15 10 /
B a dQ qN x C cm cm
C cm
67
(C) Solution
Since , MOS operates in inversion regime.2.5 0.52GB TnV V V V
max
6
6
( ) ( ) ( )
2.5 0.55 (0.4 ) 1.32 10 /
2 10
GB s GB pox n nox
ox ox ox
V VVE
t t t
V V VV cm
cm
Using Gauss’s law, we can relate the electric
field in the oxide to the substrate charge.
max( )B Nox
ox
Q QE
Solving for the inversion-layer charge, we find
max
13 6 7 2
7 2
3.45 10 / 1.32 10 / ( 1.15 10 / )
3.4 10 /
N ox ox BQ E Q
F cm V cm C cm
C cm
The inversion layer charge can also be calculated from 7 2( ) 3.4 10 /N ox GB TnQ C V V C cm
68
(D) Solution
In accumulation, the electric field in the oxide is
( )GB pox nox
ox ox
VVE
t t
Solving for the most negative gate-bulk voltage using6
,min
6 6
5 10 / , we find that
( 5 10 / )(2 10 ) 0.55 ( 0.4 ) 10.95
ox
GB ox ox pn
E V cm
V E t
V cm cm V V V
In inversion, the electric field in the oxide is( ) ( )GB pox n
ox
ox ox
VVE
t t
Substituting the maximum positive field 6
,max
6 6
5 10 / , we find that
(5 10 / )(2 10 ) 0.55 ( 0.4 ) 9.05
ox
GB ox ox pn
E V cm
V E t
V cm cm V V V
Example 2
Given a MOS capacitor on an n-type substrate with an n+ poly
gate( ), a donor concentration Nd=1016 cm-3, and
an oxide thickness tox=5x10-6 cm. the contact potentials have
values
a) Find the flatband voltage VFB
b) Plot the potential distribution in thermal equilibrium
c) Find the threshold voltage VTp
d) Plot the potential for VGB=VTP.
69
550mVn
400mVmn 210mVnm
70
(A) Find the flatband voltage VFB
Solution
The flatband voltage is equal and opposite to the built-in
voltage in the MOS structure
( ) (550 360 ) 190FB nnV mV mV mV
(B) Plot the potential in thermal equilibrium
SolutionThe MOS capacitor is accumulated in
thermal equilibrium, since accumulate
electrons under the gate balance the positive
gate charge. We can sketch the potential
since the substrate charge is a delta function
at the SiO2 silicon interface with value
QNO=-QGO, as shown in the figure.
0 ( )x
71
(C) Find the threshold voltage VTp
SolutionIn order to invert the surface, we must first apply VFB to reach flatband. To deplete the
substrate, we must apply VGB<VFB to repel the mobile electrons from the surface and
leave the positively charged ionized donors. At the onset of inversion, the surface
potential will be lowered to the point where it is equal and opposite to that of the n-
type bulk: . Adding the flatband voltage, the voltage drop across the depletion
region and the voltage drop across the oxide the threshold voltage
VTp is
'
s n '
,max 2B B nV V '
oxV
,max'2 2B
Tp FB n ox FB n
ox
QV V V V
C
Note that the drop across the oxide is negative since the substrate has a positive
depletion charge QB,max>0 and the gate charge is negative. Substituting for the
maximum depletion charge QB,max .we find
8 2
8
2 (2 ) 4.88 10 /2 0.19 0.72 1.62
6.9 10 /
s d n
Tp FB n
ox
qN C cmV V V
C F cm
72
(D)Plot the potential
14
,max 16
2 (2 ) 2 11.7 8.85 10 0.720.31
1.6 10
s nd
a
x mqN
( ) GB Tpx for V V
Solution
When VGB=VTp=-1.62V, the n+ polysilicon gate has a potential
of 0.55-1.62=-1.07V. The potential in the n-type bulk remains
fixed at with the surface potential at the onset of
inversion . The potential varies quadratically
in the depletion region, which has a width
0.36n V 0.36s n V
73
Fig Potential of MOS structure with n-type
substrate for the case where VGB=VTp.
Consider a MOS capacitor with tox=2 × 10-6 cm on a p-type
substrate with acceptor concentration Na=5 × 1016cm-3.
(a)Compute and plot the MOS capacitance versus VGB.
(b) Compute and plot the gate charge versus VGB.
Homework 14