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VLSI Design06-88-531-01
Assignment- 01
Golam Md. Zubaer Kaiser Khan
[ID: 103061528]
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ID: 103061528
Layout Design of Inverter
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron
The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
The width of the PMOS is 1.68 times greater than the NMOS. As it was made to give higher speed,
less delay times and switching times, that is why the width of PMOS is about to double of the NMOS
width. In this type of design there may be higher power consumption due to the size of the PMOS.
For reducing the power consumption, in the PMOS active layer, two contacts were used instead of
one so that the total area of the active layer of PMOS would be reduced. It is good to say here that,
the design is not an ideal one, and the measurements I have got from the simulation, has some
distortions from the ideal measurements.
Some screenshots, Tables and calculations from the inverter without Parasitic Capacitance:
Layout View Extracted View
The overall area of the Transistor:2.65 X 7.6 = 20.14 Pico SqM.
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The Output Graph: (Normal mode and Strip Mode)
The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n Period: 8ns
Input Output
0 1
1 0
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Calculation of Rise/Fall, Delay times:
Total 3 inverters were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
Diagram for testing the Inverter and measuring delay afterwards
The graphs used for measuring the delay are given below:
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10% rise time for IN and OUT2 are respectively: 4.122ns and 4.214ns, delay= (91.28ps/2) = 45.64ps
90% rise time for IN and OUT2 are respectively: 4.213ns and 4.27ns, delay= (57.122ps/2) = 28.56ps
10% fall time for IN and OUT2 are respectively: 8.295ns and 8.382ns, delay= (86.80ps/2) = 43.4ps
90% fall time for IN and OUT2 are respectively: 8.365ns and 8.42ns, delay= (57.41ps/2) = 28.7ps
Total Delay = Sum of all delay/4 = 36.57ps
Rise time = 90% rise time 10% rise time= 4.270n 4.214n = 56ps
Fall time = 90% fall time 10% fall time= 8.423n- 8.382n = 41ps
Calculation of Power Consumption:
The output waveform of the Power Circuit:
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Final Calculation of Power:
The joule got from the calculator* 1.8V/ The period (here 8.049ns)= 3.72W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
The output graph:
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Delays with Effect of Fan Out:
10% rise time: 12.257ns and 12.117ns, Delay= (140.398ps/2) =70.199ps
90% rise time: 12.387ns and 12.257ns, Delay= (130.153ps/2) =65.07ps
10% fall time: 16.4341ns and 16.307ns, Delay= (127.072ps/2) =63.536ps
90% fall time: 16.520ns and 16.395ns, Delay= (125.705ps/2) =62.8525ps
Total Delay = Sum of all delay/4 = 65.413ps
Rise time = 90% rise time 10% rise time= 12.3877n 12.2577n = 130ps
Fall time = 90% fall time 10% fall time= 16.520n 16.434n = 86ps
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DC Analysis of the Inverter:
Graph with the marker in the 10% and 90% value
Comparing the two graphs, it is seen that, as I have increase the width of my PMOS than NMOS, so
the switching point also increases. If the width of the PMOS and NMOS would same, then the
switching point would me most likely in the range of 10% to 90%. But in this case, the switching
point and the range increases. The range starts from less than 10% and goes beyond 90%, this will
consume more power to operate. As the design is for the consideration of both speed and power, so
the inverter will not be high speedy as well as it will not consume more power.
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Parametric Analysis of the Inverter: (DC Mode)
Normal Mode
Strip mode
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From the above two graph, it is seen that the inverter will be fully optimized if the width of the
PMOS would have 0.7 micron. The red color strip shows the most optimized ones. But if the PMOS
width changed to 0.7 micron, then the NMOS width will be the same as PMOS width. That design
will be more power efficient but the speed of the transistor will not be so high.
The Parametric Analysis is shown inTransient modebelow:
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Measurements with Parasitic Capacitance:
Extracted View:
It is seen that as capacitor is placed in front of each of the transistors. The values of the capacitors
are shown in the extracted view.
The same circuit diagram has to be used in the test of measuring delays, power consumption etc.
Just in the place of normal Inverter, one same size and same area Inverter extracted with Parasitic
Capacitance have to use. And all other circuit diagram and the simulation values will remain same.
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Delay Measurement:
Total 3 inverters were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
10% rise time 12.121ns and 12.207ns, Delay= (85.941ps/2) =42.970ps
90% rise time: 12.215ns and 12.277ns, Delay= (62.46ps/2) =31.23ps
10% fall time: 16.2955ns and 16.3855ns, Delay= (90.017ps/2) =45ps
90% fall time: 16.368ns and 16.429ns, Delay= (60.476ps/2) =30.238ps
Total Delay = Sum of all delay/4 = 37.3595ps
Rise time = 90% rise time 10% rise time= 12.277n 12.207n = 70ps
Fall time = 90% fall time 10% fall time= 16.4291n 16.385n = 44ps
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Calculation of Power Consumption:
The output graph after the Simulation comes like this:
Here the period for the selected wave output is 8nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is =3.9W.
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DC Analysis of the Inverter with Parasitic Capacitance:
From the graph it is seen that, the switching point increases as it is connected with a capacitor. The
previous result was: M0(693mV, 1.622V) where as the recent value is M0(704.8mV, 1.622V). The M1
point did not change much as that increases from 854mV to 856mV. But the M0 increased more forthe capacitor connection.
Summarize Table of the Inverter:
Comparison Difference in Rise
Time
Difference in Fall
Time
Total Delay Power
Consumption
Without
Parasitic 56ps 41ps 36.57ps 3.77W
With Parasitic 70ps 44ps 37.36ps 3.90 W
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Layout Design of 2-Input NAND Gate
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron
The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
Overall Area of NAND Transistors:4.12 X 7.7 = 31.724 Pico SqM.
Some screenshots, Tables and calculations from the NAND without Parasitic Capacitance:
Layout View
Schematic View
Layout View
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Extracted View
The Output Graph:
The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n Period: 8ns
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For logic 11 and 00:
Output Line
Calculation of Rise/Fall, Delay times without Parasitic Capacitance:
Total 3 NAND were used after the shown NAND to measure the delay. The input was inand the
output wasout2.
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The graphs used for measuring the delay are given below:
10% rise time: 12.1067ns and 12.1965ns, Delay= (89.857ps/2) =44.9285ps
90% rise time: 12.1745s and 12.2763ns, Delay= (101.848ps/2) =50.924ps
10% fall time: 16.3232ns and 16.4283ns, Delay= (105.133ps/2) =52.5665ps
10% fall time: 16.4086ns and 16.4982ns, Delay= (89.56ps/2) =44.78ps
Total Delay = Sum of all delay/4 = 48.29ps
Rise time = 90% rise time 10% rise time= 12.2763n 12.1965n = 79.8ps
Fall time = 90% fall time 10% fall time= 16.4982n 16.4283n = 69.9ps
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ID: 103061528
Calculation of Power Consumption without Parasitic Capacitance:
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Final Calculation of Power without Parasitic Capacitance:
The joule got from the calculator* 1.8V/ The period (here 8.007ns)= 4.33W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
The output graph:
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Delays with Effect of Fan Out without Parasitic Capacitance:
10% rise time: 12.1152ns and 12.2443ns, Delay= (129.07ps/2) =64.535ps
90% rise time: 12.207ns and 12.373ns Delay= (165.23ps/2) =82.615ps
10% fall time: 16.314ns and 16.478ns Delay= (163.549ps/2) =81.77ps
90% fall time: 16.447ns and 16.601ns Delay= (154.402ps/2) =77.201ps
Total Delay = Sum of all delay/4 = 76.530ps
Rise time = 90% rise time 10% rise time= 12.373n 12.2443n = 128.7ps
Fall time = 90% fall time 10% fall time= 16.601n 16.478n = 123ps
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Measurements with Parasitic Capacitance:
Extracted View:
Delay Measurement with Parasitic Capacitance:
Total 3 NAND were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
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10% rise time 12.1802ns and 12.2022ns, Delay= (93.98ps/2) =46.99ps
90% rise time: 12.1785ns and 12.2856ns, Delay= (107.125ps/2) =53.56ps
10% fall time: 16.324ns and 16.4315ns, Delay= (107.171ps/2) =53.58ps
90% fall time: 16.411ns and 16.506ns, Delay= (94.72ps/2) =47.368ps
Total Delay = Sum of all delay/4 = 50.3745ps
Rise time = 90% rise time 10% rise time= 12.2856n 12.2022n = 83.4ps
Fall time = 90% fall time 10% fall time= 16.506n 16.4315n = 74.5ps
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ID: 103061528
Calculation of Power Consumption with Parasitic Capacitance:
The output graph after the Simulation comes like this:
Here the period for the selected wave output is 8.028nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is =1.710W.
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Effect of Fan Out for the NAND with Parasitic Capacitance:
Delays with Effect of Fan Out with Parasitic Capacitance:
10% rise time: 12.117ns and 12.255ns, Delay= (138.23ps/2) =69.115ps
90% rise time: 12.208ns and 12.402ns Delay= (192.41ps/2) =96.205ps
10% fall time: 16.32ns and 16.49ns Delay= (164.58ps/2) =82.29ps
90% fall time: 16.45ns and 16.62ns Delay= (166.5ps/2) =83.25ps
Total Delay = Sum of all delay/4 = 82.715ps
Rise time = 90% rise time 10% rise time= 12.402n 12.255n = 147ps
Fall time = 90% fall time 10% fall time= 16.62n 16.49n = 130ps
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Summarize Table of the 2-Input NAND:
Comparison Difference in Rise
Time
Difference in Fall
Time Total Delay
Power
Consumption
Without
Parasitic 79.8ps 69.9ps 48.29ps 4.33W
With Parasitic 83.4ps 74.5ps 50.374ps 1.710 W
Fan Out Difference in Rise
Time
Difference in Fall
Time Total Delay
Without
Parasitic 128.7ps 123ps 76.53ps
With Parasitic 147ps 130ps 82.715ps
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Layout Design of 2-Input NOR Gate
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron
The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
Overall Area of NAND Transistors:4 X 7.6 = 30.4 Pico SqM.
Some screenshots, Tables and calculations from the NAND without Parasitic Capacitance:
Layout View
Schematic View
Layout View
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Extracted View
The Output Graph:
The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n Period: 8ns
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For logic 11 and 00:
Output Line
Calculation of Rise/Fall, Delay times without Parasitic Capacitance:
Total 3 NOR were used after the shown NAND to measure the delay. The input was inand the
output wasout2.
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The graphs used for measuring the delay are given below:
10% rise time: 4.1415ns and 4.2752ns, Delay= (133.67ps/2) =66.835ps
90% rise time: 4.2911ns and 4.4092ns, Delay= (118.12ps/2) =59.06ps
10% fall time: 16.296ns and 16.4297ns, Delay= (133.64ps/2) =66.82ps
10% fall time: 16.37ns and 16.492ns, Delay= (119.23ps/2) =59.615ps
Total Delay = Sum of all delay/4 = 63.08ps
Rise time = 90% rise time 10% rise time= 4.4092n 4.2752n = 134ps
Fall time = 90% fall time 10% fall time= 16.492n 16.4297n = 62.3ps
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Calculation of Power Consumption without Parasitic Capacitance:
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Final Calculation of Power:
The joule got from the calculator* 1.8V/ The period (here 8.007ns)= 4.996W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
Delays with Effect of Fan Out without Parasitic Capacitance:
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10% rise time: 12.15ns and 12.36ns, Delay= (213.71ps/2) =106.855ps
90% rise time: 12.40ns and 12.61ns Delay= (208.11ps/2) =104.055ps
10% fall time: 16.31ns and 16.50ns Delay= (198.08ps/2) =99.04ps
90% fall time: 16.41ns and 16.62ns Delay= (213.75ps/2) =106.875ps
Total Delay = Sum of all delay/4 = 104.21ps
Rise time = 90% rise time 10% rise time= 12.61n 12.36n = 250ps
Fall time = 90% fall time 10% fall time= 16.62n 16.50n = 120ps
Measurements with Parasitic Capacitance:
Extracted View:
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Delay Measurement with Parasitic Capacitance:
Total 3 NOR were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
10% rise time 4.141ns and 4.276ns, Delay= (135.23ps/2) =67.615ps
90% rise time: 4.297ns and 4.419ns, Delay= (122.34ps/2) =61.17ps
10% fall time: 8.295ns and 8.435ns, Delay= (139.62ps/2) =69.81ps
90% fall time: 8.377ns and 8.51ns, Delay= (129.99ps/2) =64.995ps
Total Delay = Sum of all delay/4 = 65.89ps
Rise time = 90% rise time 10% rise time= 4.419n 4.276n = 143ps
Fall time = 90% fall time 10% fall time= 8.51n 8.435n = 75ps
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Calculation of Power Consumption with Parasitic Capacitance:
The output graph after the Simulation comes like this:
Here the period for the selected wave output is 7.973nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is =1.67W.
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Effect of Fan Out for the Inverter with Parasitic Capacitance:
Delays with Effect of Fan Out with Parasitic Capacitance:
10% rise time 4.155ns and 4.383ns, Delay= (227.99ps/2) =113.99ps
90% rise time: 4.415ns and 4.639ns, Delay= (223.97ps/2) =111.98ps
10% fall time: 8.2965ns and 8.5132ns, Delay= (216.6ps/2) =108.3ps
90% fall time: 8.412ns and 8.641ns, Delay= (229.45ps/2) =114.725ps
Total Delay = Sum of all delay/4 = 112.24ps
Rise time = 90% rise time 10% rise time= 4.639n 4.383n = 256ps
Fall time = 90% fall time 10% fall time= 8.641n 8.5132n = 127.8ps
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Summarize Table of the 2-Input NOR:
Comparison Difference in Rise
Time
Difference in Fall
Time Total Delay
Power
Consumption
Without
Parasitic 134ps 62.4ps 63.08ps 4.996W
With Parasitic 143ps 75ps 65.89ps 1.67 W
Fan Out Difference in Rise
Time
Difference in Fall
Time Total Delay
Without
Parasitic 250ps 120ps 104.21ps
With Parasitic 256ps 127ps 112.24ps
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Layout Design of 2-Input XOR Gate
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron
The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
Overall Area of NAND Transistors:14.5 X 7.6 = 110.2 Pico SqM.
Some screenshots, Tables and calculations from the NAND without Parasitic Capacitance:
Layout View
Output
Schematic View and Logic Table
A B Output
0 0 0
0 1 1
1 0 1
1 1 0
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Extracted View
The Output Graph:
The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n Period: 8ns
For logic 10 and 01:
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Calculation of Rise/Fall, Delay times without Parasitic Capacitance:
Total 3 XOR were used after the shown NAND to measure the delay. The input was inand the output
wasout2.
The graphs used for measuring the delay are given below:
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10% rise time: 8.354ns and 8.570ns, Delay= (215.62ps/2) =107.81ps
90% rise time: 8.584ns and 8.8ns, Delay= (215.82ps/2) =107.91ps
10% fall time: 12.178ns and 12.34ns, Delay= (167.33ps/2) =83.665ps
10% fall time: 12.268ns and 12.498ns, Delay= (229.48ps/2) =114.74ps
Total Delay = Sum of all delay/4 = 103.53ps
Rise time = 90% rise time 10% rise time= 8.8n 8.570n = 230ps
Fall time = 90% fall time 10% fall time= 12.498n 12.34n = 158ps
Calculation of Power Consumption without Parasitic Capacitance:
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Final Calculation of Power:
The joule got from the calculator* 1.8V/ The period (here 8.007ns)= 11W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
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Delays with Effect of Fan Out without Parasitic Capacitance:
10% rise time: 8.3655ns and 8.77ns, Delay= (412.28ps/2) =206.14ps
90% rise time: 8.810ns and 9.230ns Delay= (420.15ps/2) =210.075ps
10% fall time: 12.17ns and 12.49ns Delay= (317.04ps/2) =158.57ps
90% fall time: 12.37ns and 12.81ns Delay= (438.59ps/2) =219.295ps
Total Delay = Sum of all delay/4 = 198.52ps
Rise time = 90% rise time 10% rise time= 9.230n 8.77n = 460ps
Fall time = 90% fall time 10% fall time= 12.81n 12.49n = 320ps
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Measurements with Parasitic Capacitance:
Extracted View:
Delay Measurement with Parasitic Capacitance:
Total 3 XOR were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
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10% rise time 8.3699ns and 8.6465ns, Delay= (279.57ps/2) =139.785ps
90% rise time: 8.66ns and 8.9419ns, Delay= (281.48ps/2) =140.74ps
10% fall time: 12.1819ns and 12.3963ns, Delay= (214.352ps/2) =107.176ps
90% fall time: 12.30ns and 12.59ns, Delay= (290.697ps/2) =145.35ps
Total Delay = Sum of all delay/4 = 133.27ps
Rise time = 90% rise time 10% rise time= 8.9419n 8.6465n = 295ps
Fall time = 90% fall time 10% fall time= 12.59n-12.40n = 190ps
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Calculation of Power Consumption with Parasitic Capacitance:
The output graph after the Simulation comes like this:
Here the period for the selected wave output is 7.973nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is =1.42W.
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Effect of Fan Out for the Inverter with Parasitic Capacitance:
Delays with Effect of Fan Out with Parasitic Capacitance:
10% rise time 8.38ns and 8.92ns, Delay= (538.74ps/2) =269.37ps
90% rise time: 8.97ns and 9.52ns, Delay= (547.42ps/2) =273.71ps
10% fall time: 12.20ns and 12.52ns, Delay= (417.94ps/2) =208.97ps
90% fall time: 12.45ns and 13.02ns, Delay= (571.22ps/2) =285.61ps
Total Delay = Sum of all delay/4 = 259.415ps
Rise time = 90% rise time 10% rise time= 9.52n 8.92n = 600ps
Fall time = 90% fall time 10% fall time= 13.02n 12.52n = 500ps
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Summarize Table of the 2-Input XOR:
Comparison Difference in RiseTime
Difference in FallTime
Total Delay PowerConsumption
Without
Parasitic 230ps 158ps 103.53ps 11 W
With Parasitic 295ps 190ps 133.2ps 1.42 W
Fan Out Difference in Rise
Time
Difference in Fall
Time Total Delay
Without
Parasitic 460ps 320ps 198.52ps
With Parasitic 600ps 500ps 259.415ps
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Layout Design of a FULL-ADDER
The size of PMOS: Width/ Length= 1.3 micron/ 0.18 micron
The size of NMOS: Width/ Length= 0.78 micron/ 0.18 micron
The ratio of PMOS to NMOS= 1.68:1.
Overall Area of NAND Transistors:15.30 X 26.70 = 408.51 Pico SqM.
Some screenshots, Tables and calculations from the Full-Adder without Parasitic Capacitance:
Layout View
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Schematic View and Logic Table
In the diagram, there are two AND gates, and one OR gate. But as O implement NAND and NOR gate,
so I have used them instead of AND and OR gate, with the Inverter. So that, it can work as AND andOR gate. So in this modified diagram, total 3 inverters are used.
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Extracted View
The Output Graph:
The delay time, rise time and fall time for the Simulation: 200ps each of them
Pulse Width used: 3.6n Period: 8ns
For logic 111 and 000:
Cout
Sum
Cin
B
A
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For logic 011 and 000:
Sum
Cout
B
A
Cin
For Logic 001 and 100:
Cout
Sum
B
A
Cin
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Calculation of Rise/Fall, Delay times without Parasitic Capacitance:
Total 3 Adder were used after the shown NAND to measure the delay. The input was inand the
output wasout2.
The graphs used for measuring the delay are given below:
10% rise time: 8.52ns and 9.15ns, Delay= (636.36ps/2) =318.18ps
90% rise time: 8.772ns and 9.40ns, Delay= (636.67ps/2) =318.335ps
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10% fall time: 12.29ns and 12.73ns, Delay= (444.80ps/2) =222.4ps
10% fall time: 12.39ns and 12.83ns, Delay= (447.76ps/2) =223.88ps
Total Delay = Sum of all delay/4 = 270.70ps
Rise time = 90% rise time 10% rise time= 9.40n 9.15n = 250ps
Fall time = 90% fall time 10% fall time= 12.83n 12.73n = 100ps
Calculation of Power Consumption without Parasitic Capacitance:
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Final Calculation of Power:
The joule got from the calculator* 1.8V/ The period (here 7.98ns)= 30.72W.
Effect of Fan Out for the Inverter without Parasitic Capacitance:
Circuit Diagram:
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Delays with Effect of Fan Out without Parasitic Capacitance:
10% rise time: 8.54ns and 9.47ns, Delay= (933.88ps/2) =466.94ps
90% rise time: 9.03ns and 9.96ns Delay= (936.18ps/2) =468.09ps
10% fall time: 12.30ns and 12.88ns Delay= (587.74ps/2) =293.87ps
90% fall time: 12.51ns and 13.10ns Delay= (584.20ps/2) =292.1ps
Total Delay = Sum of all delay/4 = 380.25ps
Rise time = 90% rise time 10% rise time= 9.96n 9.47n = 490ps
Fall time = 90% fall time 10% fall time= 13.10n 12.88n = 220ps
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Measurements with Parasitic Capacitance:
Delay Measurement with Parasitic Capacitance:
Total 3 Adder were used after the shown inverter to measure the delay. The input was inand the
output wasout2.
10% rise time 8.57ns and 9.40ns, Delay= (829.05ps/2) =414.525ps
90% rise time: 8.91ns and 9.75ns , Delay= (832.90s/2) =416.45ps
10% fall time: 12.335ns and 12.91ns, Delay= (574.29ps/2) =287.145ps
90% fall time: 12.47ns and 13.05ns, Delay= (572.56ps/2) =286.28ps
Total Delay = Sum of all delay/4 = 351.10ps
Rise time = 90% rise time 10% rise time= 9.75n 9.40n = 350ps
Fall time = 90% fall time 10% fall time= 13.05n 12.91n = 140ps
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Calculation of Power Consumption with Parasitic Capacitance:
Circuit Diagram:
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The output graph after the Simulation comes like the above:
Here the period for the selected wave output is 8.055nS.
After calculating the power by the calculator, I got the value like this:
The consumed power by the Inverter with Parasitic capacitance is =1.4999W.
Effect of Fan Out for the Inverter with Parasitic Capacitance:
Delays with Effect of Fan Out with Parasitic Capacitance:
10% rise time 8.60ns and 9.83ns, Delay= (1.22ns/2) =610ps
90% rise time: 9.28ns and 10.51ns, Delay= (1.21ns/2) =605ps
10% fall time: 12.34ns and 13.13ns, Delay= (785.33ps/2) =392.66ps
90% fall time: 12.64ns and 13.43ns, Delay= (784.57ps/2) =392.285ps
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Total Delay = Sum of all delay/4 = 499.98ps
Rise time = 90% rise time 10% rise time= 10.51n 9.83n = 680ps
Fall time = 90% fall time 10% fall time= 13.43n-13.13n = 300ps
Summarize Table of the FULL-ADDER:
Comparison Difference in Rise
Time
Difference in Fall
Time Total Delay
Power
Consumption
Without
Parasitic 250ps 100ps 270.70ps 30.72 W
With Parasitic 350ps 140ps 351.10ps 1.4999 W
Fan Out Difference in Rise
Time
Difference in Fall
Time Total Delay
Without
Parasitic 490ps 220ps 380.25ps
With Parasitic 680ps 300ps 499.98ps