Lab for Cell-Based IC Design
Tsung-Yi Wu
Design Flow Reference
RTL
GL Netlist
Layout
ATPG
DC
BlastFusionApollo
RTLQA
NCVerilog
PrimeTime
Scan Insertion
MemoryBIST
Layout
>0.18um <=0.18um
VerplexLEC
TurboFault
TestingVerification/ Analysis
FPGAMigration
RTL Work
SIIR DropNautilusDC Start-RC
Power/Timing Analysis
JTAG
Blast
Plan
ExampleVerilog RTL Code (gcd.v)
module gcd(clk,xi,yi,reset,gcd,done);input clk,reset;input [15:0] xi,yi;output done;output [15:0] gcd;reg [15:0] gcd;reg done;always @(posedge clk)begin: gcd_loop reg [15:0] x,y;if (reset) begin x <= xi; y <= yi; done <= 0; endelse if (!done) beginif (x == y) begin gcd <= x; done <= 1; endelse if (x > y) x <= x - y;else y <= y - x;endendendmodule
ExampleTestbench (gcd_tb.v)
module tb;reg clk,reset;reg [15:0] xi,yi;wire [15:0] gcd;wire done;gcd dut(clk,xi,yi,reset,gcd,done);always #5 clk = ~clk;always @(negedge clk) begin$display("gcd=",gcd," done=",done, " x=",dut.gcd_loop.x, " y=",dut.gcd_loop.y);endalways @(posedge clk) if (done) $finish;initial begin clk = 0; reset = 1; xi = 27; yi = 15;#10 reset = 0;endendmodule
RTL SimulationRTL Simulation
Copy 2 Verilog files to your directorysource ~tywua/csh/ncsim.cshverilog gcd_tb.v gcd.v
RTL SimulationSimulation Result
SynthesisSynthesis Steps
Run X-Win32Copy syn.tcl to your directorysource ~/csh/synthesis.cshdesign_vision &In Design Vision command window, enter
source syn.tclQuit Design Vision
SynthesisSynthesis Result
SynthesisOutput Files
timing.log: timing Reportgcd.sdf: SDF filegcd.gt.v: Gate Level Netlist
DebussyTrace Your Gate Level Netlist
source ~tywua/csh/verdi64.cshrcdebussyIn Debussy
FileImport DesignFrom FileClick gcd.gt.vClick AddClick OKClick AND Gate Icon
Gate Level SimulationCopy gt_ gcd_tb1.v to your directoryCopy gt_ gcd_tb2.v to your directorysource gl_sim1.bat source gl_sim2.bat
Gate Level SimulationSimulation
Results
Gate Level SimulationSimulation Results