Ken FoustIntel
A Developer’s Guide to MIPI I3CSM for Sensors and Beyond
©2017MIPIAlliance,Inc.
Outline• IntroductiontoMIPII3CSM• Usagesbeyondsensing
– MIPICameraControlInterface(CCISM)– MIPITouchoverI3CSM– MIPIDebugforI3CSM
• MIPII3CSM featuredescriptions• Implementationguidelines
– LegacyDeviceSupport– HDRModes– VariedTopologies
• Summarizedgooddesignpractices
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©2017MIPIAlliance,Inc.
MIPII3CSM forUbiquitousLowSpeedInterfacing• Anywheresensorsareused,MIPII3CSM belongs• AimedtowardhistoricalI2C,SPIandUARTapplicationsin…
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©2017MIPIAlliance,Inc.
WhatisMIPII3CSM?• Innovativenew2-WireSensorinterface• Keyfeaturesaddresshistoricalpainpoints
– In-bandInterrupt,DynamicAddressing,Multi-Master,StandardizedCommands,TimeControl,Hot-Join,ErrorDetectionandRecovery
– Plus… High Data RatesLow PowerI2C Compatibility
©2017MIPIAlliance,Inc.
AccelerometerMagnetometer
Host
ACCEL_INT
SNS_SYNC
ACCEL_INT2
Accelerometer
GyroGYRO_IRQ_N
ALS/ProximityALS_INT_N
Altimeter(barometric pressure)
CompassCOMPASS_INT
I2C_SDAI2C_CLK
MISO
SPI_ACTIVESCKMOSIDRDY
SLEEP
Grip Sensor (ULPP)ULPP_INT
DRDYENABLE
TS_I2C_SDATS_I2C_CLK
TS_S_DRDYTS_SLEEP
Fingerprint
ADC
Touchscreen
SLEEPNear Field CommNFC_IRQ_N
AccelerometerMagnetometer
Host
Accelerometer
Gyro
ALS/Proximity
Altimeter(barometric pressure)
Compass
SENSOR_DATASENSOR_CLK
Grip Sensor (ULPP)
Fingerprint
ADC
Touchscreen
Near Field Comm
MIPII3CSMVision?TooManyI/Os!
FragmentedInterfaces!
©2017MIPIAlliance,Inc.
UsagesBeyondSensing
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• MIPICCISM (CameraControlInterface)overI3CSM offersfaster,lowerlatencyandmoreefficientcameracontrolwithfutureabilitiestosupportgroupeddatawriteandAONimaging
• Currenttouchscreencontrollerinterfacesarefragmented• Formanytouchscreens,MIPITouchoverI3CSM presentsaconverged
interfaceoptionforprocessedandrawtouchdata,leveragingIBIandHDRmodes
• MIPIDebugforI3CSM offersamorecompleteclosedchassis,scalableandpowerawareplatformdebugcapabilitywithminimumboundarypincount
©2017MIPIAlliance,Inc.
MIPII3CSM Features• I3CSDR– TheBaseInterface
– Upto12.5MHzI2C-likeclockingwithdefinedOpen-Drain/Push-Pull
– SupportsmultipleclassesofDevices• I3CMainMaster
– SDR-onlyMainMaster• I3CSecondaryMaster
– SDR-OnlySecondaryMaster• I3CSlave
– SDR-OnlySlave• I2Cslave
I2CSLAVE
SDA
SCL
I3C MAIN
MASTER
I3C SECONDARY
MASTER
I3CSLAVE
I3C SLAVE
I3CSECONDARY
MASTER
I3C SLAVEI3C SECONDARY MASTER(Slave of Main Master)
I3C MAIN MASTER
LEGEND
I2C SLAVE
I2CSLAVE
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©2017MIPIAlliance,Inc.
MIPII3CSM Features• SDRDynamicAddressAssignment
– Standardizedprocedurefordynamicassignmentof7-bitAddressestoallI3CDevices
• I3CSlaveshavetwostandardizedcharacteristicsregistersandaninternal48-bitProvisionalIDtoaidetheprocedure
– LegacyI2CDevicesstillusetheirstaticI2CAddress
• SDRIn-bandInterrupt– SlavedevicecanissueSTARTRequestwhenin“BusAvailable”state– MasterprovidesInterfaceClockforSlavetodriveit’sMaster-assigned
addressontothebus– LowestassignedaddresswinsarbitrationinOpen-Drainconfiguration– Adatapayload(i.e.MandatoryDataByte)canimmediatelyaccompanythe
In-bandInterrupt
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©2017MIPIAlliance,Inc.
MIPII3CSM Features• ErrorDetectionandRecoveryMethodology
– ForMasterandSlavegeneratederrors(9ErrorTypesidentified,Parity,CRC5)
• CommonCommandCodes– StandardizedcommandmodewithextensiblesetofMIPI-definedcodesthat
canbeBroadcastedand/orDirected,Readand/orWrite
– StandardizedCommandCodes• EventEnable/Disable• ActivityStates• PayloadMgmt• I3CFeatureMgmt (DynamicAddressAssignment,Mastership,HDRModes,
TimingControl)• TestModes• ExtensibleSpace(MIPIandVendor)
SorSr 0x7E/W/ACK CommandCode/T Data(Optional)(BroadcastCCConly)/T Sr orP
*ExampleofBroadcastCCCFrame
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Guidelines- LegacyI2CDeviceSupport• Fm andFm+SpeedsSupported• 50nsSpikeFilter(tSP)Neededfor12.5MHzI3CSM Clocking
• ClockStretchingisNotAllowed– I3CSCLisPush/Pull• 20mAOpenDrainDrivers(IOL)areNotUsed• I2CExtendedAddresses(10bit)areNotUsed
Legacy I2CSDA/SCL PinsAfter Spike FilterSuppressed by50ns filter
Input toSDA/SCL Pins
tDIG_H
0.7 X VDD
0.3 X VDD
0.7 X VDD
0.3 X VDD
tSPIKE tSPIKEtDIG_L
I3C SDA/SCL Pins Without Spike Filter
0.7 X VDD
0.3 X VDD
*UM10204: I2C-bus specification and user manual Rev. 6
tSP: pulse width of spikes that must
be suppressed by the input filter
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©2017MIPIAlliance,Inc.
MIPII3CSM Features• I3CHighDataRate(HDR)Modes
– OptionallysupportedbeyondthebaseSDRmode:12.5MHz,SDA/SCL• HDR-DDR:DoubleDataRate• HDR-TSL/TSP:TernarySymbol
– Offerbitratesover33MbpsatafractionoftheperbitpowerofI2CFastMode– SimpleSlave-sidedigitalimplementations– CoexistentwithlegacyI2CDevices– Leveragerisingandfallingedges– IndividuallyenteredusingbroadcastedMIPI-definedCommonCommandCodes– UniversallyexitedandrestartedviaMIPI-definedtogglingpatterns
• Allowsnon-HDRI3CDevicesto“ignore”HDRtransmissionsI3C Msg1 Msg2 I3C
START Brdcst CCC EnterHDRx HDRCmd HDRDataHDRRestartPattern
HDRCmd HDRDataHDRExitPattern
STOP
SDARestart
SCL
2 2 2 2
Setup (SDA/SCL)(If Needed)
PossibleRestart
NextEdge
Confirms
HDRRestart
HDRExit
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©2017MIPIAlliance,Inc.
MIPII3CSM Features• HDR-DDR:DoubleDataRate
– UsesSCLasaclock,howeverDataandCommandschangeSDAonbothSCLedges.Bycontrast,SDRModechangesSDAonlywhenSCLisLow
– HDR-DDRmovesdatabyWords,whichgenerallycontains2preamblebits,2payloadbytesand2paritybits.4WordTypesdefined:Command,Data,CRC,andReserved
– Simpleprotocol:
From Master to Slave
From Slave to Master
ACK = Acknowledge (SDA Low)NACK = Not Acknowledge (NACK)S = START ConditionSr = RESTART ConditionP = STOP Condition T = Transition Bit Alternative to ACK/NACKTransition Bit
(Parity Bit for CCC)
...S or Sr I3C Reserved byte
(0x7E) (R/W=0) ACK Enter HDR-DDR CCC (ENTHDR0) T HDR-DDR
CommandHDR DDR Data
(1 or more words)HDR DDR
CRCHDR
RESTART
HDR-DDR Command
HDR Data (1 or more words)
HDR DDRCRC HDR Exit P
SDR HDR
HDR SDR
Command, Data, or CRCBased on Preamble (2-bit MSB)
Parity Bits P1: Odd Parity bit P0: Even Parity bit
Preamble BitsDefine the subsequent Word Types
SDAP1 P0 D0.7 D0.6 D0.5 D0.4 D0.3 D0.2 D0.1 D0.0 D1.7 D1.6 D1.5 D1.4 D1.3 D1.2 D1.1 D1.0 P1 P0
SCL
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©2017MIPIAlliance,Inc.
MIPII3CSM Features• HDR-TSL/TSP:TernarySymbolCoding
– Ternarysymbolcodingforpure(TSP)andI2Clegacy-inclusive(TSL)systems– Givenatwo-wireinterfacewith‘simultaneous’transitionsandnotraditionalclock,
thereare3possiblesymbolsavailable– 0,1,2
– Atleastonelinemusttransitioneachperiod– Ideally,thereare3possible“next”transition– TransitionindicesareusedtoefficientlyencodeBinaryintoTernary– Simpleprotocol:
SDA10
SCL
One symbol
11 01010011 00
HDR-TSL/TSPI2C and I3C SDR
vs
I3CSDR Msg1 Msg2 I3C
START Brdcst CCC EnterHDRxHDRCmd
HDRDataHDR
RestartPattern
HDRCmd HDRDataHDRExitPattern
STOP
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©2017MIPIAlliance,Inc.
Guidelines- HDRModes• EnterHDRCommandsSupported
• HDRExitPatterndetectedbyallI3CDevices
• Non-HDRDevicesshallignoreI3CHDRbustrafficuntiltheHDRExitPatternisdetected
I3C Msg1 Msg2 I3C
START Brdcst CCC EnterHDRx HDRCmd HDRDataHDRRestartPattern
HDRCmd HDRDataHDRExitPattern
STOP
HDRExit
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©2017MIPIAlliance,Inc.
Guidelines- VariedTopologies
• Impactsonsignaltransition/transittimes(maximumbusfrequency)– SDA/SCLdrivestrength:“weaker”forlowerpowerandinterferencevs“stronger”forfaster
overlargertopologies/loads– Tracelengthandmaterial:shortvslongandpcb vscable– SCL/SDApadcapacitance– ClocktoDataTurnaroundTime(tSCO)
• LegacyI2CDevicesimpactmaximumbusfrequency(MHz)– MustrunI3Catspeeds/pulsesbeyondSpikeFilterorslowBustothatofslowestI2CDevice
• Impactsonsignalintegrity/reliability– DeviceLocation:closeandfarDevicescancauseinterferencefromreflections
I3C Master
I3C Slave
I3C Slave
I3C Slave
Example
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©2017MIPIAlliance,Inc.
SummarizedGoodDesignPractices• ThoroughlyunderstandcapabilityofcoexistentLegacyI2CDevices
– 50nsSpikeFilter– DisabledClockStretch
• UnderstandbustopologyandperformancetradeoffsMixed(I3CandLegacyI2CDevices)vsPureBus(I3CDevicesOnly)– Tracelengthandmaterial– SDA/SCLpadcapacitance– ClocktoDataTurnaroundTime(tSCO)– Devicelocation
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©2017MIPIAlliance,Inc.
AnyQuestions?
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