Main DC characteristics.

Like BSIM3v3, BSIM4v4 accounts for major physical effects:

• Short-Narrowchanneleffectsonthresholdvoltage• Non-uniformdopingeffects• Mobilityreductionduetoverticalfield• Bulkchargeeffect• Carriervelocitysaturation• Draininducedbarrierlowering• Channellengthmodulation• Source/Drainparasiticresistances• Substratecurrentinducedbodyeffect• Quantummechanicchargethicknessmodel• Unifiedflickernoisemodel

BSIM4v4 has the following major improvements and additionsover BSIM3v3.2:

• Accurate model of the intrinsic input resistance for both RF,high-frequencyanalogandhigh-speeddigitalapplications

Until now, the physical MOSFET device model named BSIM3version 3.2 and developed at UC Berkeley was considered asthe industry standardmodel for deep sub-micron CMOS circuitdesign.ItwasrapidlyadoptedbyICcompaniesandfoundriesforaccuratelymodelingdevicesdownto0.25µm.

Fordevicescalesdownto0.10µm,somephysicalmechanismsneedtobebettercharacterized.Thesemechanismsinclude:

• Velocityovershoot• Bettermodelingofweakinversioncharges• GatebiasdependentsourceanddrainseriesresistanceofLDDMOSFETs

• Morephysicalinvestigationofnarrowwidtheffects• CarrierquantizationofMOSFETinversionlayers

BSIM4v4 isdeveloped toexplicitelyaddress the following issues,forwhichBSIM3v3.2wasfoundlackingandinaccurate:

• Accuratemodelingofsub-0.13micronMOSFETdevices• AccuracyinRF,high-frequencyanalogandhigh-speeddigitalCMOScircuitsimulation

• Modelfunctionality(geometry-dependentparasiticsmodel)

Asapublicdomainmodel,BSIM4v4(likeBSIM3v3)isameansofcom-munication,simplifyingtechnologysharingandimprovingproductivity.

• FlexiblesubstrateresistancenetworkforRFmodeling• Newaccuratechannelthermalnoisemodelandnoisepartitionmodelfortheinducedgatenoise

• Non-quasi-static (NQS)model, consistent with the Rg-basedRFmodel and consistent ACmodel, accounting for the NQSeffectinbothtransconductancesandcapacitances

• Accurategatedirecttunnelingmodel• Comprehensivegeometry-dependentparasiticsmodelforvari-oussource/drainconnectionsandmulti-fingerdevices

• Improvedmodelforsteepverticalretrogradedopingprofiles• Bettermodelforpocket-implanteddevicesinVth,bulkchargeeffect,andRoutequations

• Asymmetrical and bias-dependent source/drain resistance,eitherinternalorexternaltotheintrinsicMOSFET

• Acceptanceofeithertheelectricalorphysicalgate• Oxidethicknessasthemodelinputattheuser’schoice• Quantummechanicalcharge-layer-thicknessmodelforbothIVandCV

• Moreaccuratemobilitymodelforpredictivemodeling• Gate-induceddrainleakage(GIDL)currentmodel,availablein

BSIM for the first time• Improvedunifiedflicker(1/f)noisemodel,smoothoverallbiasregionsandaccountingforthebulkchargeeffect

• Differentdiode IVandCVcharateristics forsourceanddrainjunctions

• Junctiondiodebreakdownwithorwithoutcurrentlimiting• Gatedielectricconstantdefinedasamodelparameter

BSIM4v4Industry Standard Sub-0.13 Micron MOSFET Model

Advanced Model Technology for Sub-0.13 Micron and RF High-Speed CMOS Design

BSIM4v4 Fundamental Improvements Over BSIM3v3

Including:• Anewthresholdvoltagemodelforpocket/retrogradetechnologies• AVgsteffformulation,re-derivedtoachievebetteraccuracyofgm,gm/Idandgm2/Idinthemoderateinversionregion

• Abulkchargemodel,withanewformulationofAbulktoconsideritsstrongeffectondopingprofile

• Three mobility models, MOBMOD=0 and 1 coming fromBSIM3v3.2, and the newMOBMOD=2 corresponding to a uni-versalandmoreaccuratemodel

• A new output resistancemodel, especially suitable for long-channelandpocket-implanteddevices

• AGate-Induced-Drain-Leakage(GIDL)currentmodel• Twobias-dependentRdsmodel,correspondingtotheBSIM3v3.2model(internal)ortoanewasymmetricmodel(external),whichismoreaccurateforRFCMOScircuitsimulation

• A quantum-mechanical inversion-layer thickness and high-kgatedielectricsmodel,accountedforinbothIVandCV

• Trap-assisted tunneling and recombination current model toaccountforhalo-dopingtechnology

• Scalablestresseffectmodelforprocessinducedstress(STI).Device performance varies with active area geometry andlocationofthedeviceintheactivearea

Overview of Advanced Physics-Based Model Equations

Including:• Four options for modeling electrode gate (bias-independent)andintrinsicinput(bias-dependent)resistances,alsoworkingwithmulti-fingerdevices(fig.1)

• Two different switches to turn on and off the charge-deficitNon-Quasi-Static(NQS)modelintransientandinACanalysis,bothACandtransientNQSmodelsbasedonthesamefunda-mental physics

• Aflexiblebuilt-insubstrateresistancenetworkaccountingforthehighfrequencycouplingthroughthesubstrate

• A gate dielectric tunneling current model accounting for acurrent flowing between gate and substrate and a currentflowingbetweengateandchannelregion,whichispartitionedbetweenthesourceandthedrainterminals

BSIM4providesthreeoptionsforselectingintrinsicandoverlap/fringingcapacitancemodels,allcomingfromBSIM3v3.2.Thefol-lowingtablemapsthesemodelsinBSIM4tothoseinBSIM3v3.2:

• Acomprehensiveandversatilegeometry-dependentparasiticsmodel,providingseriesandmulti-fingerdevicelayoutmodelingcapabilities

• Three asymmetrical source/drain junction diode IV models:resistance-free and breakdown-free models coming fromBSIM3v3.2andanewbreakdown-and-resistancemodel

• Flickernoise:asimplifiedmodelandaunifiedphysicalmodelareavailable, both coming from BSIM3v3.2with several improve-mentsintheunifiedformulation

• Thermalnoise:along-channelmodel(comingfromBSIM3v3.2)andanewholisticmodelareavailable

• BSIM4 MOSFET model is part of the ModelLib product-inde-pendentmodel library. It can be accessedwithin SmartSpiceorUtmostIIIaslevel14.Olderversions,0.0,1.0,2.0,2.1and3.0,previouslyreleasedbyUC-BerkeleyarealsosupportedandareaccessibleusingthemodelparameterVERSION

• The implementation is fully compatible with the most recentmodeldescriptionissuedonMarch4,2004byUC-Berkeley

• FurtherspeedimprovementscanbegainedthroughtheVZEROoptionandthemulti-threadingcapabilities

• ThediagnosticsoptionEXPERTissupportedinBSIM4to helpthedesignerfindconvergenceproblems

• ThreeselectableSTImodels:TSMCandBerkeleybeta-versionmodels are available in addition to the latest Berkeleymodel,usingtheSTIMODselector

CAPMODin MatchedIntrinsicCAPMOD MatchedIntrinsicOverlap/fringing BSIM4 inBSIM3v3.2.2 CAPMODinBSIM3v3.2.2

0 0 0

1 2 2

2(default) 3 2

A complete plot of all intrinsic capacitances.

Basic Current-Voltage (IV) Model

Parasitics Modeling

RF and High-Speed Model

Noise Modeling

Charge-Voltage (CV) Model

Silvaco Implementation

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