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7/30/2019 Implementing rate compatible turbo codes

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ASMS 2004

I m p l em en t a t i o n o f B l ock Tu r b o Co d esfo r H igh Speed Com m u n ica t i on Sys t em s

Dig i t a l Broad cast in g Research Div i s ion, ETRISun heu i Ryoo , Sooyo un g K im , and Do Seob Ahn

21 September 2004


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Needs o f h igh speed codec fo r w i r e lessco m m u n i cat io n sy st em s

N ew st a n d a r d f o r w i r e l ess co m m u n i ca t i o n s- Broadcasting and mobile systems converge to seamless network

as well as moving towards closer, mutually beneficial interworking.

- These systems include networks with multimode, multiband, and multimedia

high capacity mobile terminal.

- Such future systems should be able to fulfill the stringent requirements for

quality of service (QoS), mainly in terms of throughput, delay and error rate.

Needs o f h igh speed b lock t u r bo codec- Many current research activates in the field of wireless communication system

are focusing on finding the powerful channel codes

- not only with the excellent error correction capability

- but also with the practical implementation complexity.


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Block t u r bo codes

Tur bo codes- After turbo codes are first introduced, they have been widely studied

for their outstanding performance close to the Shannon limit.

- Soon after, Pyndiah introduced Block Turbo Codes, and there have been

many presentations on H/W implementations.

- Some recent implementation results showed that its speed can cope

with even fiber-optic applications.

Ef f i cien t b lock t u r bo codes im p lem ent ed in FPGA leve l- However their implementations are all based on algebraic decoding algorithms.

- On the other hand, our block turbo codes used trellis decoding algorithms

which have inherent soft input soft output (SISO) decoding capability.

- By using this, we can provide an efficient iterative decoding algorithm

and the high performance.


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i n fo rmat ionrow

par i ty

colum n par i t y

n

k

Blo ck t u r b o co d es - co n st r u ct io n

Encod ing o f m u l t i - d im ensional t u r bo codes- The concept of block turbo codes allows us to construct powerful codes

by using the systematic linear block codes.- An m dimensional block turbo codes are theoretically possible

for m larger than 2.

- We construct an m dimensional block turbo code using the component BCH

codes with parameters (n1, k1), (n2, k2), , and (nm, km)- where ni, and ki stand for codeword length and information word length.

- The parameters of the m dimensional block turbo codes are given

by n = n1n2nm, k= k1k2km, and the code rate R is given by R = R1R2Rm


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So f t ou t pu t decod ing a lgo r i t hm- To compensate for the inferior performance of the SOVA compared to the more

complex MAP algorithm with several performance improvement techniques.- We decoded block turbo codes iteratively on each axis using soft output

information from the decoding on the other axes.

information row parity

column parity

n2

Soft output decodi ng

al gorithm

Soft output decodi ngal gorithm

Bl ock t u r b o co d es - d eco d in g


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1.5 dB0.29(15,10)3C

3.8 dB0.65(63,56)2B

3.5 dB0.79(31,25)2A

SNR@BER1 0 - 6

Coder a t e

Componen tBCH (n, k)

Dimens ionCode

Ex pu r gat ed BCH codes- 2D and 3D block turbo codes is implemented

- Below table shows their component code, code rate, and

bit energy to noise spectral density ratio (Eb/N0) to achieve a bit error rate of 10-6.

- An uncoded BPSK scheme requires about 10 dB to achieve a BER of 10-6

- The block turbo code is able to produce a coding gain of from 6.2 dB up to 8.5 dB

depending on the component codes and the dimension of block turbo codes

Bl ock t u r b o co d es - co m p o n en t co d es


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r

)(rL

dSoft_

)(rLe

Component

decoder

d

M

M

..

.

control signal

Line decoder0

Line decoder1

Line decoderN

Turbo product decoder

M

FSM & Control part

r

)(rL

dSoft_

)(rLe

d

Para l l el decod ing w i th l i ne decode r- Block turbo decoder consist ofm component decoder

- Each component decoder consist of independent line decoder

- Parallel line decoding can be executed simultaneously.

Deco d er - co m p o n en t d eco d er


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Sub block of line decoder and parameter bit precision

M

M

FSM & Control part

scale

TruncM

ACS CRU

Line decoder

6 bit10 bit

8 bit8 bit

1 bit

r

)(rL

dSoft_

)(rLe

d

1 bitHard decision result of decodingd

10 bitSoft decision result of decodingSoft_d

8 bitExtrinsic informationLe(r)

6 bitInformation received from the channelr

PrecisionSignal

Decod er - l in e d ecod er


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Component

decoder

Reliability

Pipe

0 0 0

Block

memory1

Block

memory2

Reliability

Pipe

ReliabilityPipe

Channel

reliability

x-axis

decoding

Converting

to

y-axis

y-axis

decoding

z-axis

decoding

Component

decoder

Component

decoder

Converting

to

z-axis

Converting

to

x-axis

2 , 3 D m em o r y- Using the block memory core in Xilinx chip

- Repeating the writing and reading operation

Mem o r y s t r u ct u r e


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I m p lem en t at io n Resu l t s

Opera t ion speed on t he HES boar d

- We implemented block turbo codes using FPGA chip of HES Xilinx XC2V6000.

- The shaded cells present a single chip implementation.- The parallel line decoding reduces the total decoding time

- Block memory architecture accelerates the clock speed.

480 Mbps111 clk137 clk54 MHz19 ns255

32 Mbps1,665 clk1537 clk53 MHz19 ns15

15 Mbps3,330 clk3037 clk49 MHz20 ns8C (3D)


84 Mbps2,128 clk8133 clk57 MHz18 ns8B (2D)


73 Mbps552 clk469 clk65 MHz16 ns8A (2D)

Data Rate/iteration

Totalclk

Decode/plane

clk/linedecoder

clkfrequency

CriticalPath

# ofLine

decoder

Blockturbo code


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Conclus ion

I m p l em en t at i on o f h i g h s p eed b l o ck t u r b o c od ec- This paper introduces our efficient implementation method of

block turbo codes and shows the emulation results.- We used a trellis based decoding algorithm for block turbo codes,

and implemented 2D and 3D block codes in FPGA level.

- We applied various efficient algorithms to enhance the performance.

- The implementation of line decoders in parallel improvesthe decoding speed with N times.

- The block memory structure remarkably reduces the critical path

and thus achieves high speed decoding .