Implementing multicore system using OpenRISC
Advisor: Mony Orbach
By: Jehad Ghanayem Ahmad Kiswani
ContentBackground.Working environment.minSoC vs. orpSoC.System configuration:
openRisc.minSoC.
Simulation and synthesis.Work schedule.
BackgroundProject Goal: building a SoC based on a multicore implementation of the OpenRISC CPU.Term A Goal: building a SoC based on an OpenRISC
CPU.
The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores.
The OR1200 design is an open source (under LGPL GNU) implementation of the OpenRISC 1000 RISC architecture.
Term APrimary Goal: building an OpenRISC based system on FPGA.
Configuring the CPU.Building a SoC.Simulation and Synthesis.Implementation.Debugging.Benchmarking for future reference.
Working EnvironmentWindows
PlaneAhead (synthesis).iMPACT (transferring design to FPGA).
UbuntuIcarus & or1ksim (simulation).GTKwave (viewing waves created by Icarus).GNU OpenRisc toolchain (or32-elf):
binutils, GCC and GDB (compilation and debugging).
newlib and uclibc (minimal C libraries). And others …
FPGA usedXUPV5 Board
Choosing the SoCorpSoC minSoCDeveloped by
openCores.More IP cores:
UART. Ethernet. VGA. AC97…
Suitable for running linux.
More of a ready-design.
Developed by Raul Fajardo.
Minimal implementation:UART Ethernet, and that’s it.
Only the basics, meant to be configured.
simpler, but more advanced RAM model.
Easier to implement – at least on a virtex5 board.
Configuring minSoC
Configuring the OpenRisc CPU1-way set
associative 4KB instruction and data cache.
No divide implementation (done by software).
Disabled DSP unit.
Simulation – workflowThe code is compiled with or32-elf-gcc.The binary file is converted to a hex file.The hex file is written into the memory HDL
file.The system is simulated using Icarus.UART output is redirected to the terminal.
Simulation – the code#include <board.h> #include <support.h> #include <or1200.h> #include <int.h> #include <uart.h> int main() { uart_init(); int_init(); int_add(UART_IRQ, &uart_interrupt, NULL); /* We can't use printf because in this simple example we don't link C library. */ uart_print_str("16/06/2013 Hello World.\n"); report(0xdeaddead); or32_exit(0); }
Simulation - results
Synthesis
Plenty of room for a multicore design.
Schematic
What’s NextExporting the design to the FPGA (2 weeks).Testing the SoC (1 week).Benchmarking (1 week).Submitting a report (1 week).
Writing a script to automatically configure the system for XUPV5 board.
Writing the final report.
VirtualBox – again.Linux operating system is essential to the project.
Root access is required.VirtualBox: open source software under GNU GPL.
allows the guest OS to run on virtual environment within the host OS.
VirtualBox Extension pack: allows the guest OS access to the USB.
Extra HD space: 10GB in total.Virtualbox base image = 5GBVirtualbox image with development tools = 8GB15% extra space
Thank you.