Extraction Solutions for 3D Stacks
Dusan Petranovic Interconnect Modeling Technologist Design2Silicon Division
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MG Stack Verification Flow
Calibre 3DSTACK Verify with micro-bumps are physically aligned Verify proper electrical connectivity through
die2die and die2interposer interfaces
Calibre xRC/xACT3D Extract parasitics of the Dies and Interposer interconnects Insert provided TSV circuit into integrated parasitics/TSV netlists, or extract TSV
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
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TSV Modeling Approaches
Stand Alone TSV models — Provided by foundries — Advantage: Easy to integrate into a flow ; Sufficient in many situations — Challenges: Not adequate for high density, high frequency applications
Compact parametrized models
— TSV and coupling models provided by foundries — Advantage: Can account for some interactions; Faster than FS — Challenges: Hard to account for all situations, to parameterize for all
important variables
Field solver based TSV extraction — TSV parasitics and their interactions extracted — Advantage: Most accurate — Challenges: Performance; Integration
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
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Stand Alone TSV based Flows and Models
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
Analog flow Requires more accurate TSV model
Treat TSV as a LVS device
LVS device described by Spice subcircuit
Spice simulation
Digital flow Lower accuracy requirements
Treat TSV as a via
Extraction tool generates R(C) model Can be replaced by provided model
Static timing analysis
• TSV as LVS device or as a VIA Circuit for TSV provided • TSV model typically obtained
by S-parameter measurements and circuit parameter extraction
• Model of arbitrary complexity supported for TSV in analog simulation
• Simpler RC model for digital flow; inductors ignored
• Double-sided die front and back
metal parasitic extraction
• Sufficiently good for some applications (regular layout, no RDL, low density TSVs)
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Issues in Stand Alone TSV Model based Approach Not adequate for high density, high frequency designs and non-uniform environment around TSVs Interactions between the TSVs
— Capacitive and Inductive couplings
Interaction between TSV and interconnect — Interactions with RDL
Impact of TSVs on device performance — Proper substrate description and modeling is needed
TSV
Devices
Back Metal
Front Metal
Substrate
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
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Mentor support for parametrized models TSMC Reference Flows
— 3DIC Vertical stacking 3DIC --TTS — 2.5D Interposer based stacking CoWoS --TIS Chip on Wafer on Substrate
TSV stand alone model together with
— Parametrized TSV coupling model — Models for analog and digital flows
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
• Ceff needed for STA • Coupling parasitics dependent on
spacing and frequency
Source: TSMC
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Limitations of Compact Parametrized Models
Calculated the mutual capacitance between TSV 1 and TSV 2:
— Case 1: TSV 3 and TSV 4 are not present in layout — Case 2: TSV 4 is not present in layout — Case 3: All 4 of the TSV’s are present
Very strong dependence of capacitance on the environment
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
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Mentor FS Based Solution For 3D-IC Extraction
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
Quasi-static Field Solver
Input
Generation of Frequency Points
Generation of Netlist
Update the Parasitic DB
The FS is run for all the frequency points QS capacitance/ conductance solver and QS inductance/ impedance solver
The netlist mimics the behavior of the frequency dependent data generated by the FS
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Produced Circuit
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
Output: Netlist of frequency-independent linear elements. Values of those elements are computed by fitting the frequency dependent results of the field solver
TSV_top TSV_top
TSV_top TSV_top
TSV_bot TSV_bot
TSV_bot TSV_bot
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Accuracy Results
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
Engaged with major foundries and customers Working on interposers-based (2.5D) and true 3D stacks Test chips and real designs Accuracy results (compared with full wave solvers) Performance very good; To be further improved
w/parallelization and pattern matching
Total C Self L Coupling C Mutual L
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Inter-die interactions
Interface extraction — Micro bump and pillar description and extraction
Inter die Capacitive coupling — might not be negligible between the dies, especially in Face-to-Face connection
Magnetic coupling between the dies — The dies are getting closer together — Overlapping loops between the dies
Devices
Devices
Devices
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
Source: Qualcomm
Source: RPI
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In Context Die Calibration/Extraction
Die
Die
Die
Interface
Interface
Interface
- Each die would be calibrated and extracted “in-context” - Calibration can be done incrementally, calibrating the layers from the neigbors dies separately (existing single chip rule files can be reused
- Coupling capacitances would be folded in the victim die parasitics - Interfaces will be owned by the specified dies
Die/Interposer/Package
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014
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w w w . m e n t o r . c o m
D. Petranovic: TSV Extraction, 3DIC Workshop July 2014