S. Delage
CAPABILITIES AND APPLICATIONS OF GaN DEVICES
Microwave and RF 2015
GaN Technology for Microwave Applications in Ka and Q bands
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► R. Aubry, S. Bernard, M. Magis N. Michel, O. Patard, O. Drisse, E. Derouin, L. Trinh Xuan
► M.-A. DiForte-Poisson, P. Gamarra, C. Lacam, M.Tordjman
► C. Dua, M.Oualli, L. Teisseire
► S.Piotrowicz, S. Bohbot, E. Chartier, J.-C. Jacquet, O. Jardel, D.Lancereau, C. Potier, J. Godin, B.
► B. Carnez, and J. Obregon
► MITIC-XLim Common Lab: M. Prigent, R. Quéré, J.-C. Nallatamby, R. Sommet...
► LETI: A. Torres, D. Lafond
► UMS: D. Floriot, H. Blanck, J. Gruenenputt, B. Lambert, J.-P. Viaud...
► ILV : M. Bouttemy, A. Etcheberry
► LAAS: J.-G. Tartarin, S. D. Nsele LAAS
► Thales Alenia Space: J.-L. Muraro, S. Rochette, J.-L. Cazaux...
► Thales Com: J.Y. Daden, C. Voillequin
Acknowledgement Main contributors
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Frequency Rise
► III-V Lab develops InAlN HEMT for wireless data transmission and high frequency power amplification: Ka, Q et E (30->86 GHz) Band. Civil and military communication (SATCOM)
Radars and altimeters
Data backhauling
► The applications are dual and are interesting both Alcatel-Lucent and Thales
mother companies.
► Fierce competition is observed for these markets.
► Challenges :
To increase power gain, efficiency and output power
To achieve a sufficient level of maturity
To transfer to manufacturing partners including UMS.
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Why did we believe in InAlN/GaN Heterostructure for Ultra High Power Microwave Applications ?
In0.18Al0.82N is lattice-matched to GaN ■ Strong spontaneous polarisation allowing high density 2-D gas without
mechanical stress,
■ Improved reliability expected
■ Flexibility for choosing barrier layer thickness (gate length – WBG thickness ratio), i.e. higher frequency achievable
■ Possible higher 2D gas density ( 3A/mm for 0.25µm gate length)
3.0 3.1 3.2 3.3 3.4 3.5 3.6 -0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
In 0.17
Al 0.83
N
InN
AlN
GaN
Sp
on
tan
eo
us
po
lari
za
tio
n
( C/m
2 )
Lattice constant a (A)
BACKGROUND
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Why SiC substrates ?
► 3D-Thermal simulation at transistor and MMIC level
Material Thermal conductivity (W/K.m) *
GaN 160
SiC 414
Si 155
* : at room temperature
► Rth GaN_Si/GaN_SiC ~ 1.7 -> Much lower maximum junction temperatures achieved with SiC substrates compared to Si ones
Ps 3W/mm 4W/mm 3W/mm 4W/mm
PAE 40% 40% 30% 30%
Pdiss 4 W/mm 5.4 W/mm 6.3 W/mm 8.4 W/mm
Rth Si/SiC
Tj (GaN/SiC) 105 125 140 170
Tj (GaN/Si) 145 180 210 280
Ts=50°C sous la puce 100µm - etage de puissance HPA 1.92 mm (8x4x60)
1.7
Performances at transistor level
Example of 100µm thick MMIC output power stage 1.92 mm CW – Ts=50°C
GaN 1,5 µm
SiC 100 µm
Dissipative Area
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Technology NH15-10 0.15µm InAlN/GaN HEMT
Technological steps III-V Lab UMS
Wafer cleaning and surface preparation
Alignment marks for UMS stepper
Alignment marks for III-V lab : active device process (ohmics, isolation, gate, passivation, numbering)
Resistances, inter-connection, capacitor dielectric, pillars, bridge, back-side
Measurements
Canon
stepper
Leica
e-beam Karl-Suss
Contact lithography
ASML stepper
SiC substrate lapping down to 100µm by UMS
For both InAlN or AlGaN heterostructures
and air-bridge
Realization of microstrip MMIC process and multifinger devices
shared between III-V Lab and UMS
Spiral inductors
Thin film resistors
MIM capacitance
8x125µm
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► InAlN/GaN 0.15µm HEMT III-VLab Technology
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Improvement of pinch-off and gate leakage current
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
0 5 10 15 20 25 30
Id (
A)
Vds (V)
TS288W1_2x75_ARB
Vgs = 1 V (0;0)Vgs = 0 V (0;0)Vgs = -1 V (0;0)Vgs = -2 V (0;0)Vgs = -3 V (0;0)Vgs = -4 V (0;0)Vgs = -5 V (0;0)Vgs = -6 V (0;0)Vgs = -7 V (0;0)Vgs = -8 V (0;0)Vgs = -9 V (0;0)Vgs = -10 V (0;0)Vgs = -11 V (0;0)Vgs = -12 V (0;0)Vgs = -13 V (0;0)Vgs = -14 V (0;0)
Poor pinch - off
-0.012
-0.01
-0.008
-0.006
-0.004
-0.002
0
0.002
0 5 10 15 20 25 30
Ig (
A)
Vds (V)
TS288W1 TS288W1_2x75_ARB
Vgs = 1 V Vgs = 0 V Vgs = -1 V Vgs = -2 V Vgs = -3 V Vgs = -4 V Vgs = -5 V Vgs = -6 V Vgs = -7 V Vgs = -8 V Vgs = -9 V Vgs = -10 V Vgs = -11 V Vgs = -12 V Vgs = -13 V Vgs = -14 V
Gate leakage
current
> 10mA/mm
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0 5 10 15 20 25 30 35 40 45
Ig (
A)
Vds (V)
TS502 2x50_Lg0v15_ret109
Vgs = 1 V
Vgs = 0 V
Vgs = -1 V
Vgs = -2 V
Vgs = -3 V
Vgs = -4 V
Vgs = -5 V
Vgs = -6 V
Vgs = -7 V
Low gate leakage
current < 0.5mA/mm Ig
(A)
0 5 10 15 20 25 30 35 40 45
Vds(V)
0.001
0
-0.001
-0.002
-0.003
-0.004
-0.005
Improved buffer layer
and passivation 2
Good pinch-off 2x75µm 2x50µm
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InAlN/GaN small signal power gains 2x50µm x 0.15µm (CPW) 20V-200mA/mm
InAlN/GaN
AlGaN/GaN
MSG (dB)
12.8dB @ 20 GHz
10.8dB @ 30 GHz
9.5dB @ 40 GHz
MSG (dB)
13.5dB @ 20 GHz
11.5dB @ 30 GHz
10.3dB @ 40 GHz
AlGaN
InAlN
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Ka-Band III-V Lab Hybrid Power Load-Pull
■ New equipment has been received in September 2014. ■ Much faster than older bench
limited to 18GHz,
■ Capabilities to explore large topology variation thanks to active impedance matching,
■ CW and pulses modes possible,
■ Excellent reproducibility and precision.
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■ Output power depends linearly with Vds
■ Vds < 20V
■ 4W/mm - 40% PAE - Vds=17.5V
■ Peak output power 5.12W/mm (34% PAE) at Vds=20V
InAlN/GaN Power Load-Pull Characterisation 2x50µmx0.15µm -DC-CW, f0=30 GHz, Ids=200mA/mm (classe
AB)
Vds=17,5V
Ps=4,0W/mm,
PAE=40%,
Gp=7,2 dB
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
12.5 15 17.5 20 22.5 25
PA
E (%
)
Ps
(W/m
m),
Gp
(dB
)
Vds ( V)
Ps (W/mm)
Gain (dB)
PAE (%)
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
12.5 15 17.5 20 22.5 25
PA
E (%
)
Ps
(W/m
m),
Gp
(dB
)
Vds ( V)
Ps (W/mm)
Gain (dB)
PAE (%)
Vds=15…
22,5V
Pe (dBm)
Ig (
A)
Ps
(m
W)
Pe (dBm)
Ga
in (
dB
), P
AE
(%
) , η
dra
in (
%)
2x50x0.15µm, 30GHz dc/cw
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InAlN/GaN Power Load-Pull DC-CW, f0=30 GHz, Ids=200mA/mm (class AB)
►6x50µm Lg = 0.15µm (coplanar)
■ Max Ps et PAE close, |Γopt|≈0.6
■ Vds=15V: Ps=1045mW (3.5W/mm), PAE=40% PAE, Gp=8.05dB
■ Vds=17.5V: 1270mW (4.25W/mm), PAE=36%, Gp=7.2dB
VDS =15V
Zopt Ps=|0,6|, 145°
Zopt PAE=|0,63|, 137°
Vds=15V
Ps=3,5W/mm,
PAE=40%,
Gp=8,05dB
Ps (
mW
) Pe (dBm)
Ga
in (
dB
), P
AE
(%
) , η
dra
in (
%)
6x50x0,15µm 30GHz dc/cw
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►20GHz Hybrid Power Amplifier with flip-chipped HEMT mounting
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20GHz CW Amplifier CNES project
►Vds1= 18 V, Vds2= 25V, classe AB
►@Max PAE :
►Pout=4.4W, PAE=31%, Gain=13.7dB
0
100
200
300
400
500
-10 0 10 20 30
Ids1,Id
s2 (m
A)
Pin (dBm)
Ids1
Ids2
10
12
14
16
18
20
22
-10 0 10 20 30
Gain
(dB
)
Pin (dBm)
0
1000
2000
3000
4000
5000
6000
0 100 200 300
Po
ut(
mW
)
Pin (mW)
0
5
10
15
20
25
30
35
40
-10 0 10 20 30
PA
E(%
)
Pin (dBm)
-40
-35
-30
-25
-20
-15
-10
-5
0
-10 0 10 20 30
Retu
rn L
osses (d
B)
Pin (dBm)
0
100
200
300
400
500
-10 0 10 20 30
Ids1,Id
s2 (m
A)
Pin (dBm)
Ids1
Ids2
10
12
14
16
18
20
22
-10 0 10 20 30
Gain
(dB
)
Pin (dBm)
0
1000
2000
3000
4000
5000
6000
0 100 200 300
Po
ut(
mW
)
Pin (mW)
0
5
10
15
20
25
30
35
40
-10 0 10 20 30
PA
E(%
)
Pin (dBm)
-40
-35
-30
-25
-20
-15
-10
-5
0
-10 0 10 20 30
Retu
rn L
osses (d
B)
Pin (dBm)
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► Ka Band Low Noise and High Power Amplifiers
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GENGHIS KhAN Project (ANR VERSO 2010)
Chemical Analysis of GaN
devices (Institut Lavoisier)
3’’ InAlN/GaN/SiC processed wafer
(III-V Lab / UMS)
Ka Band amplifiers
(LAAS, III-V Lab)
Ka Band package
(EGIDE, UMS, TCS)
Start :01.01.2011
End : 30.09.2014
III-V Lab contribution
- Project Management
- InAlN/GaN HEMT development
- Hybrid Ka-Band LNA (LAAS design)
- Ka Band HPA Design
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Noise parameters of InAlN/GaN transistors (0,15 µm state of the art)
NFmin=1.3 dB et Ga = 10.2 dB @20 GHz
Technology performances (LAAS measurements)
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LNA @ 30 GHz
30 GHz LNA
NF = 3.2dB @ 29.5 GHz
Gain = 5.6dB
2x75µm
Vds=6V
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► Compact NL model : 6x50µm : AlGaN/GaN (March 2014)
► 3.8W/mm – 33% PAE
► Different designs studied: ■ 2 or 3 stages
■ Balanced architectures
■ [27.5-34.5 GHz] Bandwidth and divided in 2 subbands
HPA MMIC Design
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2-stage coupled amplifier
► @Pin=31dBm, [28.5-34.5]GHz
► Pout>7.8W
► PAE~20-22%
► Gp>8dB (0.7dB ripple)
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► InAlN/GaN HEMT technology allows high frequency operation,
► Important work was carried out during the recent years to reach larger frequencies (heterostructure, gate length, passivation, topology, etc.) supported by experimental and simulations.
►Future ■ Continue effort to mature 0.15µm technology (coming EuGaNiC project),
■ Demonstrate MMIC for Ka and Q Bands (VEGaN-2 project),
■ Push further the gate length reduction (~0.08µm) and optimisation of relevant device modules to address Q-Band and above frequencies.
■ Explore MMIC functionalities enrichment by adding Normally-off device cells.
Conclusions
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Financial support by Thales, Alcatel-Lucent and CEA-LETI
acknowledged.
French Ministry of Defence, ANR, CNES and EU support is also
thanked in the frame of the following projects :
• EDA MANGA
• ANR VERSO Genghis Khan
• EU SPACE AlinWon
• CNES 20 GHz