1FEATURES APPLICATIONS
DESCRIPTION
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHzSTEREO A/D CONVERTER
• AV Amplifier23• 24-Bit Delta-Sigma Stereo A/D Converter• MD Player• High Performance:• Digital VTR– Dynamic Range: 112 dB (Typical)• Digital Mixer– SNR: 111 dB (Typical)• Digital Recorder– THD+N: –102 dB (Typical)
• High-Performance Linear Phase AntialiasDigital Filter:
The PCM1804 is a high-performance, single-chip– Pass-Band Ripple: ±0.005 dB stereo A/D converter with fully differential analog– Stop-Band Attenuation: –100 dB voltage input. The PCM1804 uses a precision
delta-sigma modulator and includes a linear phase• Fully Differential Analog Input: ±2.5 Vantialias digital filter and high-pass filter (HPF) that• Audio Interface: Master- or Slave-Moderemoves dc offset from the input signal. TheSelectable PCM1804 is suitable for a wide variety of mid- to
• Data Formats: Left-Justified, I2S, Standard high-grade consumer and professional applications,24-Bit, and DSD where excellent performance and 5-V analog supply
and 3.3-V digital power-supply operation are required.• Function:The PCM1804 can achieve both PCM audio and– Peak Detection DSD format due to the precision delta-sigma
– High-Pass Filter (HPF): –3 dB at 1 Hz, modulator. The PCM1804 is fabricated using anfS = 48 kHz advanced CMOS process and is available in a small
28-pin SSOP package.• Sampling Rate up to 192 kHz• System Clock: 128 fS, 256 fS, 384 fS,
512 fS, or 768 fS
• Dual Power Supplies:– 5 V for Analog– 3.3 V for Digital
• Power Dissipation: 225 mW• Small 28-Pin SSOP• DSD Output: 1 Bit, 64 fS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2System Two, Audio Precision are trademarks of Audio Precision, Inc.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PIN ASSIGNMENTS
123
456789
1011121314
282726
252423222120
1918171615
VREFLAGNDLVCOMLVINL+VINL−FMT0FMT1
S/MOSR0OSR1OSR2
BYPASDGND
VDD
VREFRAGNDRVCOMRVINR+VINR−AGNDVCCOVFLOVFRRSTSCKILRCK/DSDBCKBCK/DSDLDATA/DSDR
PCM1804 PACKAGE(TOP VIEW)
P0007-02
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according toMIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher thanmaximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted togetheror the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logicvoltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publicationElectrostatic Discharge (ESD) (SSYA008), available from Texas Instruments.
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HPF
HPF
Power Supply
CLKControl
Delta-SigmaModulator (L)
VREFL
VREFR
Delta-SigmaModulator (R)
DecimationFilter (L)
DecimationFilter (R)
SerialOutput
Interface
SCKI
VINL+
VINL−
VCOML
AGNDL
VREFL
VREFR
AGNDR
VCOMR
VINR+
VINR−
VCC AGND DGND VDD
OSR0
OSR1
OSR2
S/M
FMT0
FMT1
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
OVFL
OVFR
BYPAS
RST
B0029-01
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
FUNCTIONAL BLOCK DIAGRAM
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PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Terminal FunctionsTERMINAL
I/O DESCRIPTIONSNAME PINAGND 23 – Analog groundAGNDL 2 – Analog ground for VREFLAGNDR 27 – Analog ground for VREFRBCK/DSDL 16 I/O Bit clock input/output in PCM mode. L-channel audio data output in DSD mode. (1)
BYPAS 12 I HPF bypass control. High: HPF disabled, Low: HPF enabled (1)
DATA/DSDR 15 O L-channel and R-channel audio data output in PCM mode. R-channel audio data output in DSD mode. (DSDoutput, when in DSD mode)
DGND 13 – Digital groundFMT0 6 I Audio data format 0. See Table 5. (2)
FMT1 7 I Audio data format 1. See Table 5. (2)
LRCK/DSDBCK 17 I/O Sampling clock input/output in PCM and DSD modes. (1)
OSR0 9 I Oversampling ratio 0. See Table 1 and Table 2. (2)
OSR1 10 I Oversampling ratio 1. See Table 1 and Table 2. (2)
OSR2 11 I Oversampling ratio 2. See Table 1 and Table 2. (2)
OVFL 21 O Overflow signal of L-channel in PCM mode. This is available in PCM mode only.OVFR 20 O Overflow signal of R-channel in PCM mode. This is available in PCM mode only.RST 19 I Reset, power-down input, active-low (2)
SCKI 18 I System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS. (3)
S/M 8 I Slave/master mode selection. See Table 4. (2)
VCC 22 – Analog power supplyVCOML 3 – L-channel analog common-mode voltage (2.5 V)VCOMR 26 – R-channel analog common-mode voltage (2.5 V)VDD 14 – Digital power supplyVINL– 5 I L-channel analog input, negative pinVINL+ 4 I L-channel analog input, positive pinVINR– 24 I R-channel analog input, negative pinVINR+ 25 I R-channel analog input, positive pinVREFL 1 – L-channel voltage reference output, requires capacitors for decoupling to AGNDVREFR 28 – R-channel voltage reference output, requires capacitors for decoupling to AGND
(1) Schmitt-trigger input(2) Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant.(3) Schmitt-trigger input, 5-V tolerant.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
over operating free-air temperature range (unless otherwise noted) (1)
VCC –0.3 V to 6.5 VSupply voltage
VDD –0.3 V to 4 VGround voltage differences AGND, AGNDL, AGNDR, DGND ±0.1 VSupply voltage difference VCC, VDD VCC – VDD < 3 V
FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST –0.3 V to 6.5 VDigital input voltage
BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK, OVFL, OVFR –0.3 V to (VDD + 0.3 V)Analog input voltage VREFL, VREFR, VCOML, VCOMR, VINL+, VINR+, VINL–, VINR– –0.3 V to (VCC + 0.3 V)Input current (any pins except supplies) ±10 mA
TA Ambient temperature under bias –40°C to 125°CTstg Storage temperature –55°C to 150°CTJ Junction temperature 150°C
Lead temperature (soldering) 260°C, 5 sPackage temperature (IR reflow, peak) 260°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range
MIN NOM MAX UNITAnalog supply voltage, VCC 4.75 5 5.25 VDigital supply voltage, VDD 3 3.3 3.6 VAnalog input voltage, full-scale (–0 dB), differential input 5 Vp-pDigital input logic family TTL compatible
System clock 8.192 36.864 MHzDigital input clock frequency
Sampling clock 32 192 kHzDigital output load capacitance 10 pFOperating free-air temperature, TA –10 70 °C
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ELECTRICAL CHARACTERISTICS
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,24-bit data, unless otherwise noted.
PCM1804DBPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXResolution 24 Bits
DATA FORMATAudio data interface format Standard, I2S, left-justifiedAudio data bit length 24 Bits
MSB first,Audio data format 2s complement, DSDDIGITAL INPUT/OUTPUT
Logic family TTL compatible(1) (2) 2 5.5
VIH High-level input voltage Vdc(3) 2 VDD
VIL Low-level input voltage (1) (2) (3) 0.8 VdcVIN = VDD
(1) 65 100IIH High-level input current VIN = VDD
(2) ±10 μAVIN = VDD
(3) ±100VIN = 0 V (1) (2) ±10
IIL Low-level input current μAVIN = 0 V (3) ±50
VOH High-level output voltage IOH = –1 mA (4) 2.4 VdcVOL Low-level output voltage IOL = 1 mA (4) 0.4 VdcCLOCK FREQUENCYfS Sampling frequency 32 192 kHz
256 fS, single rate (5) 12.288384 fS, single rate (5) 18.432512 fS, single rate (5) 24.576768 fS, single rate (5) 36.864
System clock frequency MHz256 fS, dual rate (6) 24.576384 fS, dual rate (6) 36.864128 fS, quad rate (7) 24.576192 fS, quad rate (7) 36.864
DC ACCURACYGain mismatch, channel- ±3 % of FSRto-channelGain error (VIN = –0.5 dB) ±4 % of FSRBipolar zero error HPF bypass ±0.2 % of FSR
(1) Pins 6–11, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST [Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant](2) Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant)(3) Pins 12, 16–17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)(4) Pins 15–17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL(5) Single rate, fS = 48 kHz(6) Dual rate, fS = 96 kHz(7) Quad rate, fS = 192 kHz
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PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,24-bit data, unless otherwise noted.
PCM1804DBPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXDYNAMIC PERFORMANCE (8)
VIN = –0.5 dB –102 –95fS = 48 kHz, system clock = 256 fSVIN = –60 dB –49
VIN = –0.5 dB –101fS = 96 kHz, system clock = 256 fSTotal harmonic distortionTHD+N VIN = –60 dB –47 dBplus noise
VIN = –0.5 dB –101fS = 192 kHz, system clock = 128 fSVIN = –60 dB –47
VIN = –0.5 dB DSD mode –100fS = 48 kHz, system clock = 256 fS 106 112
VIN = –60 dB fS = 96 kHz, system clock = 256 fS 112Dynamic range dB(A-weighted) fS = 192 kHz, system clock = 128 fS 112DSD mode 112fS = 48 kHz, system clock = 256 fS 105 111fS = 96 kHz, system clock = 256 fS 111
SNR (A-weighted) dBfS = 192 kHz, system clock = 128 fS 111DSD mode 111fS = 48 kHz, system clock = 256 fS 97 109
Channel separation fS = 96 kHz, system clock = 256 fS 107 dBfS = 192 kHz, system clock = 128 fS 107
ANALOG INPUTInput voltage Differential input ±2.5 VCenter voltage 2.5 VdcInput impedance Single-ended 10 kμ
DIGITAL FILTER PERFORMANCEPass-band edge Single rate, dual rate 0.453 fS HzStop-band edge Single rate, dual rate 0.547 fS HzPass-band ripple Single rate, dual rate ±0.005 dBStop-band attenuation Single rate, dual rate –100 dBPass-band edge (–0.005 Quad rate 0.375 fS HzdB)Pass-band edge (–3 dB) Quad rate 0.49 fS HzStop-band edge Quad rate 0.77 fS HzPass-band ripple Quad rate ±0.005 dBStop-band attenuation Quad rate –135 dBGroup delay Single rate, dual rate 37/fS sGroup delay Quad rate 9.5/fS sHPF frequency response –3 dB fS/48000 Hz
(8) fIN = 1 kHz, using System Two™ audio measurement system by Audio Precision™ in RMS mode, with 20-kHz LPF and 400-Hz HPF incalculation for single rate, or with 40-kHz LPF in calculation for dual and quad rates.
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PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,24-bit data, unless otherwise noted.
PCM1804DBPARAMETER TEST CONDITIONS UNIT
MIN TYP MAXPOWER SUPPLY REQUIREMENTSVCC 4.75 5 5.25
Supply voltage range VdcVDD 3 3.3 3.6ICC VCC = 5 V (9) (10) (11) 35 45
VDD = 3.3 V (9) (12) 15 20Supply current mA
IDD VDD = 3.3 V (10) (12) 27VDD = 3.3 V (11) (12) 18Operation, VCC = 5 V, VDD = 3.3 V (9) (12) 225 290Operation, VCC = 5 V, VDD = 3.3 V (10) (12) 265
PD Power dissipation mWOperation, VCC = 5 V, VDD = 3.3 V (11) (12) 235Power down, VCC = 5 V, VDD = 3.3 V 5
TEMPERATURE RANGEOperation temperature –10 70 °C
θJA Thermal resistance 100 °C/W
(9) Single rate, fS = 48 kHz(10) Dual rate, fS = 96 kHz(11) Quad rate, fS = 192 kHz(12) Minimum load on DATA/DSDR (pin 15)
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TYPICAL PERFORMANCE CURVES - SINGLE RATE
−55
−50
−45
−40
−35
T − Temperature − °C
−110
−105
−100
−95
−90
−20 0 20 40 60 80TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
0.5
dB)
TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
60 d
B)
−60 dB
−0.5 dB
G001
T − Temperature − °C
100
105
110
115
120
−20 0 20 40 60 80
Dyn
amic
Ran
ge a
nd S
NR
− d
B
G002
Dynamic Range
SNR
−55
−50
−45
−40
−35
VCC − Supply V oltage − V
−110
−105
−100
−95
−90
4.50 4.75 5.00 5.25 5.50TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
0.5
dB)
TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
60 d
B)
G003
−60 dB
−0.5 dB
VCC − Supply V oltage − V
100
105
110
115
120
4.50 4.75 5.00 5.25 5.50
Dyn
amic
Ran
ge a
nd S
NR
− d
B
G004
Dynamic Range
SNR
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unlessotherwise noted.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vs
TEMPERATURE TEMPERATURE
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 3. Figure 4.
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−55
−50
−45
−40
−35
fS − Sampling Frequency − kHz
−110
−105
−100
−95
−90
TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
0.5
dB)
TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B (−
60 d
B)
G005
−60 dB
−0.5 dB
44.132 48 100
105
110
115
120
Dyn
amic
Ran
ge a
nd S
NR
− d
B
G006
Dynamic Range
SNR
fS − Sampling Frequency − kHz
44.132 48
−120
−100
−80
−60
−40
−20
0
−100 −80 −60 −40 −20 0
TH
D+N
− T
otal
Har
mon
ic D
isto
rtion
+ N
oise
− d
B
G009Signal Level − dB
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unlessotherwise noted.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SNRvs vs
SAMPLING FREQUENCY SAMPLING FREQUENCY
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISEvs
SIGNAL LEVEL
Figure 7.
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f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 12000 24000
Am
plitu
de −
dB
G008
Output Spectrum:−60 dB,N = 8192
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 12000 24000
Am
plitu
de −
dB
G007
Output Spectrum:−0.5 dB,N = 8192
TYPICAL PERFORMANCE CURVES - DUAL RATE
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 24000 48000
Am
plitu
de −
dB
G010
fS = 96 kHz,System Clock = 256 f S
Output Spectrum:−0.5 dB,N = 8192
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 24000 48000
Am
plitu
de −
dB
G011
fS = 96 kHz,System Clock = 256 f S
Output Spectrum:−60 dB,N = 8192
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unlessotherwise noted.
AMPLITUDE AMPLITUDEvs vs
FREQUENCY FREQUENCY
Figure 8. Figure 9.
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, and 24-bit data, unless otherwise noted.
AMPLITUDE AMPLITUDEvs vs
FREQUENCY FREQUENCY
Figure 10. Figure 11.
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TYPICAL PERFORMANCE CURVES - QUAD RATE
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 48000 96000
Am
plitu
de −
dB
G012
fS = 192 kHz,System Clock = 128 f S
Output Spectrum:−0.5 dB,N = 8192
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 48000 96000
Am
plitu
de −
dB
G013
fS = 192 kHz,System Clock = 128 f S
Output Spectrum:−60 dB,N = 8192
TYPICAL PERFORMANCE CURVES - DSD MODE
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 11025 22050
Am
plitu
de −
dB
G014
Output Spectrum:−0.5 dB,N = 8192
f − Frequency − Hz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 11025 22050
Am
plitu
de −
dB
G015
Output Spectrum:−60 dB,N = 8192
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted.
AMPLITUDE AMPLITUDEvs vs
FREQUENCY FREQUENCY
Figure 12. Figure 13.
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 44.1 kHz, system clock = 16.9344 MHz, unlessotherwise noted.
AMPLITUDE AMPLITUDEvs vs
FREQUENCY FREQUENCY
Figure 14. Figure 15.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single-Rate
Normalized Frequency − fS
−200
−150
−100
−50
0
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Am
plitu
de −
dB
G016
fS = 48 kHz
Normalized Frequency − fS
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Am
plitu
de −
dB
G017
fS = 48 kHz
Normalized Frequency − fS
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
0.02
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Am
plitu
de −
dB
G018
fS = 48 kHz
Normalized Frequency − fS
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Am
plitu
de −
dB
G019
fS = 48 kHz
−6.04 dB at 0.5 f S
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICSFOR SINGLE-RATE FILTER FOR SINGLE-RATE FILTER
Figure 16. Figure 17.
PASS-BAND RIPPLE CHARACTERISTICS TRANSIENT BAND CHARACTERISTICSFOR SINGLE-RATE FILTER FOR SINGLE-RATE FILTER
Figure 18. Figure 19.
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LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual-Rate
Normalized Frequency − fS
−200
−150
−100
−50
0
50
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Am
plitu
de −
dB
G020
fS = 96 kHz
Normalized Frequency − fS
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Am
plitu
de −
dB
G021
fS = 96 kHz
Normalized Frequency − fS
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
0.02
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Am
plitu
de −
dB
G022
fS = 96 kHz
Normalized Frequency − fS
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Am
plitu
de −
dB
G023
fS = 96 kHz
−6.02 dB at 0.5 f S
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICSFOR DUAL-RATE FILTER FOR DUAL-RATE FILTER
Figure 20. Figure 21.
PASS-BAND RIPPLE CHARACTERISTICS TRANSIENT BAND CHARACTERISTICSFOR DUAL-RATE FILTER FOR DUAL-RATE FILTER
Figure 22. Figure 23.
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LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad-Rate
Normalized Frequency − fS
−200
−150
−100
−50
0
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Am
plitu
de −
dB
G024
fS = 192 kHz
Normalized Frequency − fS
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.25 0.50 0.75 1.00
Am
plitu
de −
dB
G025
fS = 192 kHz
Normalized Frequency − fS
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
0.02
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Am
plitu
de −
dB
G026
fS = 192 kHz
Normalized Frequency − fS
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Am
plitu
de −
dB
G027
fS = 192 kHz
−3.9 dB at 0.5 f S
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICSFOR QUAD-RATE FILTER FOR QUAD-RATE FILTER
Figure 24. Figure 25.
PASS-BAND RIPPLE CHARACTERISTICS TRANSIENT BAND CHARACTERISTICSFOR QUAD-RATE FILTER FOR QUAD-RATE FILTER
Figure 26. Figure 27.
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HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE
Normalized Frequency − fS/1000
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4
Am
plitu
de −
dB
G028Normalized Frequency − fS/1000
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Am
plitu
de −
dB
G029
PRINCIPLES OF OPERATION
THEORY OF OPERATION
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
STOP-BAND CHARACTERISTICS PASS-BAND CHARACTERISTICS
Figure 28. Figure 29.
The PCM1804 consists of a band-gap reference, a delta-sigma modulator with full-differential architecture forL-channel and R-channel, a decimation filter with a high-pass filter, and a serial interface circuit. Figure 30illustrates the total architecture of the PCM1804. An on-chip, high-precision reference with 10-μF externalcapacitor(s) provides all the reference voltage needed in the PCM1804, and it defines the full-scale voltage rangeof both channels. Full-differential architecture provides a wide dynamic range and excellent power-supplyrejection performance. The input signal is sampled at ×128, ×64, and ×32 oversampling rates according to theoverasmpling ratio control, OSR[0:2]. The single rate, dual rate, and quad rate eliminate the external sample-holdamplifier. Figure 31 illustrates how for each oversampling ratio the PCM1804 decimates the modulator outputdown to PCM data when the modulator is running at 6.144 MHz. The delta-sigma modulation randomizes themodulator outputs and reduces the idle tone level. The oversampled data stream from the delta-sigma modulatoris converted to a 1-fS, 24-bit digital signal, while removing high-frequency noise components using a decimationfilter. The dc components of the signal are removed by the HPF, and the HPF output is converted to atime-multiplexed serial signal through the serial interface, which provides flexible serial formats and master/slavemodes. The PCM1804 also has a DSD output mode. The PCM1804 can output the signal directly from themodulators to DSDL (pin 16) and DSDR (pin 15).
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HPF
HPF
Power Supply
CLKControl
Delta-SigmaModulator (L)
VREFL
VREFR
Delta-SigmaModulator (R)
DecimationFilter (L)
DecimationFilter (R)
SerialOutput
Interface
SCKI
VINL+
VINL−
VCOML
AGNDL
VREFL
VREFR
AGNDR
VCOMR
VINR+
VINR−
VCC AGND DGND VDD
OSR0
OSR1
OSR2
S/M
FMT0
FMT1
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
OVFL
OVFR
BYPAS
RST
B0029-01
f − Frequency − kHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 48 96 144 192
Am
plitu
de −
dB
G030
Dual-Rate Filter
Quad-Rate Filter
ModulatorSingle-Rate
Filter
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
PRINCIPLES OF OPERATION (continued)
Figure 30. Total Block Diagram of PCM1804
Figure 31. Spectrum of Modulator Output and Decimation Filter
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SYSTEM CLOCK INPUT
SCKI0.8 V
SCKI
2 V
tw(SCKL)tw(SCKH)
T0005B07
POWER-ON AND RESET FUNCTIONS
POWER-DOWN FUNCTION
OVERSAMPLING RATIO
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
PRINCIPLES OF OPERATION (continued)
The PCM1804 supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as asystem clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18).Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10),and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSDmode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown inTable 1 and Table 3.
PARAMETER MIN UNITtw(SCKH) System clock pulse duration, HIGH 11 nstw(SCKL) System clock pulse duration, LOW 11 ns
Figure 32. System Clock Input Timing
The PCM1804 has both an internal power-on-reset circuit and RST (pin 19). For internal power-on reset,initialization (reset) is performed automatically at the time when the power supply VDD exceeds 2 V (typical) andVCC exceeds 4 V (typical). RST accepts external forced reset, and a low level on RST initiates the resetsequence. Because an internal pulldown resistor terminates RST, no connection of RST is equivalent to alow-level input. Because the system clock is used as a clock signal for the reset circuit, the system clock must besupplied as soon as power is supplied; more specifically, at least three system clocks are required prior to VDD >2 V, VCC > 4 V, and RST = high. While VDD < 2 V (typical), VCC < 4 V (typical), or RST = low, and 1/fS (maximum)count after VDD > 2 V (typical),VCC > 4 V (typical) and RST = high, the PCM1804 stays in the reset state and thedigital output is forced to zero. The digital output is valid after the reset state is released and the time of 1116/fShas passed. Figure 33 and Figure 34 illustrate the internal power-on-reset and external-reset timing, respectively.Figure 35 illustrates the digital output for power-on reset and RST control. The PCM1804 needs RST = low whencontrol pins are changed or in slave mode when SCKI, LRCK, and BCK are changed.
The PCM1804 has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode isdone by keeping the RST input level low for more than 65536/fS. In the master mode, the SCKI (pin 18) is usedas the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) areused as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon asRST goes high, the PCM1804 starts the reset-release sequence described in the Power-On and Reset Functionssection.
The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 andTable 2. The PCM1804 needs RST = low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.
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PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Table 1. Oversampling Ratio in Master ModeOSR2 OSR1 OSR0 OVERSAMPLING RATIO SYSTEM CLOCK RATELow Low Low Single rate (× 128 fS) 768 fSLow Low High Single rate (× 128 fS) 512 fSLow High Low Single rate (× 128 fS) 384 fSLow High High Single rate (× 128 fS) 256 fSHigh Low Low Dual rate (× 64 fS) 384 fSHigh Low High Dual rate (× 64 fS) 256 fSHigh High Low Quad rate (× 32 fS) 192 fSHigh High High Quad rate (× 32 fS) 128 fSHigh Low Low DSD mode (× 64 fS) 384 fSHigh Low High DSD mode (× 64 fS) 256 fS
Table 2. Oversampling Ratio in Slave ModeOSR2 OSR1 OSR0 OVERSAMPLING RATIO SYSTEM CLOCK RATELow Low Low Single rate (× 128 fS) Automatically detectedLow Low High Dual rate (× 64 fS) Automatically detectedLow High Low Quad rate (× 32 fS) (1) Automatically detectedLow High High Reserved –High Low Low Reserved –High Low High Reserved –High High Low Reserved –High High High Reserved –
(1) Only at the 128-fS system clock rate
Table 3. Sampling Frequency and System Clock FrequencySYSTEM CLOCK FREQUENCY (MHz)SAMPLINGOVERSAMPLING RATIO FREQUENCY (kHz) 128 fS 192 fS
(1) 256 fS 384 fS 512 fS 768 fS
32 – – 8.192 12.288 16.384 24.576Single rate (2) 44.1 – – 11.2896 16.9344 22.5792 33.8688
48 – – 12.288 18.432 24.576 36.86488.2 – – 22.5792 33.8688 – –
Dual rate (3)96 – – 24.576 36.864 – –
176.4 22.5792 33.8688 – – – –Quad rate (4)
192 24.576 36.864 – – – –DSD mode (3) 44.1 – – 11. 2896 16.9344 – –
(1) Only available in master mode at the quad rate(2) Modulator is running at 128 fS.(3) Modulator is running at 64 fS.(4) Modulator is running at 32 fS.
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1024 System Clock + 1/fS (Max)
Reset Reset Removal
4.4 V / 2.2 V4 V / 2 V
3.6 V / 1.8 VVCC, VDD
Internal Reset
System Clock
T0014-07
t(RST)
Reset Removal
1/fS (Max)
RST
Internal Reset
System Clock
RST Pulse Duration (t(RST)) = 40 ns (Min)
Reset
T0015-05
Ready / Operation
Power ONRST ON Reset Removal
Reset
1116/fS
Zero Data Converted Data(2)
Internal Reset
Data(1)
T0051-01
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Figure 33. Internal Power-On-Reset Timing
Figure 34. External Reset Timing
(1) In the DSD mode, DSDL is also controlled like DSDR.(2) The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On Reset and RST Control
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AUDIO DATA INTERFACE
INTERFACE MODE
DATA FORMAT
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
The PCM1804 interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), andDATA/DSDR (pin 15). The PCM1804 needs RST = low when in the interface mode and/or the data format arechanged.
The PCM1804 supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) asshown in Table 4. In master mode, the PCM1804 provides the timing of the serial audio data communicationsbetween the PCM1804 and the digital audio processor or external circuit. While in slave mode, the PCM1804receives the timing for data transfer from an external controller. Slave mode is not available for DSD.
Table 4. Interface ModeS/M MODELow Master modeHigh Slave mode
The PCM1804 supports four audio data formats in both master and slave modes, and these data formats areselected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5.
Table 5. Data FormatFMT1 FMT0 FORMAT MASTER SLAVELow Low PCM, left-justified, 24-bit Yes YesLow High PCM, I2S, 24-bit Yes YesHigh Low PCM, standard, 24-bit Yes YesHigh High DSD Yes –
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INTERFACE TIMING FOR PCM
1 2 23 243 22
L-Channel R-Channel
1/fS
LRCK
BCK
DATA
L-Channel R-Channel
1/fS
LRCK
BCK
DATA
L-Channel R-Channel
1/fS
LRCK
BCK
DATA
(1) Left-Justified Data Format; L-Channel = High, R-Channel = Low
(2) I2S Data Format; L-Channel = Low , R-Channel = High
(3) Standard Data Format; L-Channel = High, R-Channel = Low
T0009-03
1 2 3 1 223 2422
1 2 3 1 2 3 1 223 242223 2422
1 2 3 1 2 323 2422 23 2422 23 2422
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Figure 36 through Figure 38 illustrate the interface timing for PCM.
NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode.
Figure 36. Audio Data Format for PCM
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BCK
LRCK
DATA
tw(BCKH)
tw(BCKL)t(CKLR)
t(LRCP)
t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
0.5 VDD
0.5 VDD
T0018-03
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
PARAMETERS MIN TYP MAX UNITt(BCKP) BCK period 1/(64 fS)(3)
tw(BCKH) BCK pulse duration, HIGH 32 nstw(BCKL) BCK pulse duration, LOW 32 nst(CKLR) Delay time, BCK falling edge to LRCK valid –5 15 nst(LRCP) LRCK period 1/fSt(CKDO) Delay time, BCK falling edge to DATA valid –5 15 nst(LRDO) Delay time, LRCK edge to DATA valid –5 15 nstr Rising time of all signals(1)(2) 10 nstf Falling time of all signals(1)(2) 10 ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.(2) Load capacitance of all signals is 10 pF.(3) t(BCKP) is fixed at 1/(64 fS) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
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BCK
LRCK
DATA
tw(BCKH)
tw(BCKL)
t(LRHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
0.5 VDD
T0017-03
INTERFACE TIMING FOR DSD
Dn−3 Dn−2 Dn−1 Dn Dn+1 Dn+2 Dn+3
Dn−3 Dn−2 Dn−1 Dn Dn+1 Dn+2 Dn+3
DSDBCK
DSDL
DSDR
T0052−01
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
PARAMETERS MIN TYP MAX UNITt(BCKP) BCK period 1/(64 fS) 1/(48 fS)tw(BCKH) BCK pulse duration, HIGH 32 nstw(BCKL) BCK pulse duration, LOW 32 nst(LRSU) LRCK setup time to BCK rising edge 12 nst(LRHD) LRCK hold time to BCK rising edge 12 nst(LRCP) LRCK period 1/fSt(CKDO) Delay time, BCK falling edge to DATA valid 5 25 nst(LRDO) Delay time, LRCK edge to DATA valid 5 25 nstr Rising time of all signals(1)(2) 10 nstf Falling time of all signals(1)(2) 10 ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.(2) Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
Figure 39 and Figure 40 illustrate the interface timing for DSD.
Figure 39. Audio Data Format
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tw(BCKH) tw(BCKL)t(CKDO)
t(BCKP)
0.5 VDD
0.5 VDD
DSDBCK
DSDLDSDR
T0053−01
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM
HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
PARAMETERS MIN TYP MAX UNITt(BCKP) DSDBCK period 354 nstw(BCKH) DSDBCK pulse duration, HIGH 177 nstw(BCKL) DSDBCK pulse duration, LOW 177 nst(CKDO) Delay time DSDBCK falling edge to DSDL, DSDR valid –5 15 nstr Rising time of all signals(1)(2) 10 nstf Falling time of all signals(1)(2) 10 ns
(1) Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.(2) Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.
Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)
In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization ofLRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCKor SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code untilresynchronization between LRCK and SCKI is completed.
In case of changes less than ±5 BCK, resynchronization does not occur and the previously described digitaloutput control and discontinuity do not occur.
Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined data,the PCM1804 may generate some noise in the audio signal. Also, the transitions of normal to undefined data andundefined or zero data to normal cause a discontinuity of data on the digital output. This can generate noise inthe audio signal. In master mode, synchronization loss never occurs.
The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,the dc component of the input analog signal and the internal dc offset are also converted and output in the digitaloutput data.
HPF Bypass ControlBYPAS PIN HPF MODE
Low Normal (high-pass) modeHigh Bypass (through) mode
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OVERFLOW FLAG FOR PCM
1/fS 90/fS
Converted Data(2)Zero DataUndefined
DataNormal Data
SynchronousAsynchronousSynchronous
ResynchronizationSynchronization Lost
DATA(1)
State of Synchronization
T0020-06
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
The PCM1804 has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as theanalog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns to low ifthe analog input does not go across the full-scale range for the period.
(1) Applies only for slave mode; the loss of synchronization never occurs in master mode.(2) The HPF transient response appears initially.
Figure 41. ADC Digital Output for Loss of Synchronization and Resynchronization
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TYPICAL CIRCUIT CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28VREFL
AGNDL
VCOML
VINL+
VINL−
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
VDD
VREFR
AGNDR
VCOMR
VINR+
VINR−
AGND
VCC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
27
26
25
24
23
22
21
20
19
18
17
16
15
+C1
+C3
+C5
+
−
L-Channel In
Format [1:0]
Master/Slave
OversamplingRatio [2:0]
HPF Bypass
3.3 V
C2
C4
+
+
+
C6 5 V
Control
+
−
R-Channel In
Overflow
Reset
System Clock
L/R Clock
Data Clock
Data Out
Audio DataProcessor
PCM1804
S0058-01
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Figure 42 illustrates a typical circuit connection diagram in the PCM data format operation.
A. C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supplyB. C3, C4: Bypass capacitor, 0.1-μF tantalum, depending on layout and power supply
Figure 42. Typical Circuit Connection Diagram for PCM
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+C1
+C3
+C5
+
−
L-Channel In
Format [1:0]
Master/Slave
OversamplingRatio [2:0]
HPF Bypass
3.3 V
C2
C4
+
+
+
C6 5 V
Control
+
−
R-Channel In
Overflow
Reset
System Clock
Data Clock
L-Channel Data Out
Audio DataProcessor
PCM1804
R-Channel Data Out
S0058-02
VREFL
AGNDL
VCOML
VINL+
VINL−
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
VDD
VREFR
AGNDR
VCOMR
VINR+
VINR−
AGND
VCC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation.
A. C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supplyB. C3 and C4: Bypass capacitors, 0.1-μF tantalum, depending on layout and power supply
Figure 43. Typical Circuit Connection Diagram for DSD
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APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD Pins
VIN Pins
VREFX, VCOMX Inputs
DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK Pins
System Clock
Reset Control
APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground pinswith 0.1-μF ceramic and 10-μF tantalum capacitors placed as close to the pins as possible to maximize thedynamic performance of the ADC. Although the PCM1804 has two power lines to maximize the potential ofdynamic performance, using one common power supply is recommended to avoid unexpected power-supplytrouble like latch-up or power-supply sequence.
Use of 0.01-μF film capacitors between VINL+ and VINL– and between VINR+ and VINR– is stronglyrecommended to remove higher-frequency noise from the delta-sigma input section.
Use 0.1-μF ceramic and 10-μF tantalum capacitors between VREFL, VREFR, and corresponding AGNDx, to ensurelow-source impedance at ADC references. Use 0.1-μF tantalum capacitors between VCOML, VCOMR andcorresponding AGNDx to ensure low source impedance of common voltage. These capacitors should be locatedas close as possible to the VREFL, VREFR, VCOML, and VCOMR pins to reduce dynamic errors on references andcommon voltage. The dc voltage level of these pins is 2.5 V.
The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability.Locating the buffer near the PCM1804 and minimizing the load capacitance, minimizes the digital-analogcrosstalk and maximizes the dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1804 operates based on asystem clock. Therefore, it might be necessary to consider the system clock duty, jitter, and the time differencebetween system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.
If capacitors larger than 10 μF are used on VREFL and VREFR, an external reset control with a delay timecorresponding to the VREFL and VREFR response is required. Also, it works as a power-down control.
An application diagram for a single-ended input circuit is shown in Figure 44. The maximum signal input voltageand differential gain of this circuit is designed as Vinmax = 8.28 Vpp, Ad = 0.3. Differential gain (Ad) is given byR3/R1(R4/R2) in a circuit configured as a normal inverted-gain amplifier. Resistor R5(R6) in the feedback loopgives low-impedance drive operation and noise filtering for the analog input of the PCM1804. The circuittechnique using R5(R6) is recommended.
Copyright © 2001–2007, Texas Instruments Incorporated Submit Documentation Feedback 29
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_
+
4.7 kΩ
4.7 kΩ
OPA2134 1/2
+
10 µFR1 = 3.3 kΩ
_
+
C(1)
R5 = 47 Ω
R3 = 1 kΩ
VIN−
_
+
R4 = 1 kΩ
R6 = 47 Ω
0.1 µF
+
R2 = 3.3 kΩ
OPA2134 1/2
VIN+
VCOM
0.01 µF
PCM1804
Analog In
OPA2134 1/2
S0059-01
C(1)
10 µF
_
+
_
+
VCOM VREF
VIN+
VIN−
BGR
∆Σ Modulator
S0060-01
PCM1804
SLES022C–DECEMBER 2001–REVISED OCTOBER 2007
(1) A capacitor value of 1800 pF is recommended, unless an input signal greater than –6 dBFS at 100 kHz or higher isapplied in the DSD mode. In that case, 3300 pF is recommended.
Figure 44. Application Circuit for Single-Ended Input Circuit (PCM)
Figure 45. Equivalent Circuit of Internal Reference (VCOM, VREF)
30 Submit Documentation Feedback Copyright © 2001–2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish MSL Peak Temp(3)
Op Temp (°C) Top-Side Markings(4)
Samples
PCM1804DB ACTIVE SSOP DB 28 47 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -10 to 70 PCM1804
PCM1804DBG4 ACTIVE SSOP DB 28 47 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -10 to 70 PCM1804
PCM1804DBR ACTIVE SSOP DB 28 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -10 to 70 PCM1804
PCM1804DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -10 to 70 PCM1804
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF PCM1804 :
• Automotive: PCM1804-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1(mm)
W(mm)
Pin1Quadrant
PCM1804DBR SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Nov-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1804DBR SSOP DB 28 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Nov-2008
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
26X 0.65
2X8.45
28X 0.380.22
8.27.4 TYP
SEATINGPLANE
0.05 MIN
0.25GAGE PLANE
0 -8
2 MAX
B 5.65.0
NOTE 4
A
10.59.9
NOTE 3
0.950.55
(0.15) TYP
SSOP - 2 mm max heightDB0028ASMALL OUTLINE PACKAGE
4214853/B 03/2018
1
1415
28
0.15 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-150.
A 15DETAIL ATYPICAL
SCALE 1.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAXALL AROUND
0.07 MINALL AROUND
28X (1.85)
28X (0.45)
26X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0028ASMALL OUTLINE PACKAGE
4214853/B 03/2018
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
14 15
28
15.000
METALSOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKOPENING
EXPOSED METALEXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASKDEFINED
(PREFERRED)
SOLDER MASKDEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
28X (1.85)
28X (0.45)
26X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0028ASMALL OUTLINE PACKAGE
4214853/B 03/2018
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
14 15
28
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