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ELECTRONIC PROGNOSTICS FOR DC to DC CONVERTERS
Ridgetop Group, Inc. Tucson, Arizona
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Acknowledgements
• Work was funded by JSF Program Office and the associated SBIR.
• Lockheed Martin/Ft. Worth
• C & D Technologies/Tucson
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Ridgetop Background• Tucson-based firm, five
years of growth!• Government customers
include DARPA, Navy, DOE, NASA, Missile Defense
• Strong in Analog/Mixed-Signal design and test.
• Staff backgrounds from Tektronix, Hughes, Credence, Honeywell
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Joint Strike Fighter (JSF)• 75% of the Fighters
by 2020• Employs advanced
Prognostics/Health Management (PHM)
• Use of Commercial Off the shelf (COTS) Products
• Lockheed Martin is the Prime Contractor
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JSF PHM Vision
Source: A. Hess, JSF Program Office
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Ridgetop’s JSF-Funded Project
• Develop Electronics PHM to a widely used module within Mil/Aero Systems
• Test bed is a Commercial High Efficiency DC to DC Converter (Forward Converter)
• Develop techniques and modular, reusable, methodologies that can be widely applied in EW Systems.
• Snap on to existing diagnostics backbone
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Ridgetop’s Project - PHM• Navy has determined significant
problems with Power converter modules’ reliability.
• To examine electronics-module PHM, a simple DC-DC power converter was selected.
• SBIR introduces a new PHM approach and applies the efficacy on Forward Topology, a variation of the buck, ( 80% of Navy’s converters).
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Features of C&D WPA50 Supply
• 50W, 5V output• Vin range = 36V-
75Vdc• Under voltage and
high Temperature protection
• 400 kHz switching• 200ms turn-on time
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Lifetime Model
“Bathtub Curve”
Failure Rate
Time
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Failure Rate Mapping
Reliability
“Bathtub Curve”
Cumulative Probability of Failure
Prognostic “distance”
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Electronics Prognostics Approach
SMPS Key Failure Modes
Pareto Ranking
Gate Oxide Hot Carrier Radiation
Step 2: Extract Precursors to Failure
Step 3: Calculate Remaining Lifetime (using CPU)
Ripple Current (Cap) Semi Faults
End of Life
Step 1: Characterize SMPS Power System Failures
Degradation
Lifetime of SMPS Power System
Failure Rate
Advanced Warning Point
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Prioritize Precursor Observations
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Pareto Analysis
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CRITICAL COMPONENTS• Primary MOS• Secondary Sync.
Forward and catch rectifier
• Opto Isolator• PWM controller• Input capacitor• Output CapacitorForward Converter
Input= 48Vdc
Output= 5V, 10A max
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Precursor MethodologyCan pre-cursors be measured during normal operating
conditions?
Measure pre-cursor voltage or currents to predict failure during normal operating conditions
Can pre-cursors be measured under different
operating conditions?Apply new operating conditions to measure pre-cursors to failure
Can Statistics predict the failure of the component?
Apply physics of failure model, using known statistics to predict failure of component
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Physics of Failure
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Power MOSFET failure• High dv/dt variations
due to fast switching• Slow reverse
recovery of body diode parasitic bipolar turn on
• Higher on-resistance at high T. Thermal runaway possible
BREAKDOWNRepresented by a low but finite impedance of the short-circuit path
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Power MOS failure (Contd.)FAILURE MECHANISMS
• Short-circuit induced over-currents
• Over-Voltage induced over-currents
CONCLUSION• Failure probability depends
on the distance of the operating point from the SOA Boundary
Source: Hower P.L., “Safe Operating Area – a new frontier in LDMOS design”
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Power MOS failure (Contd.)Prognostic Technique
• Formulate mathematical model incorporating the time-to-breakdown based on the Physics-of-Failure approach
• Add Sacrificial MOS Prognostic Cell, subjected to higher stress conditions, so that it’s operating point is closer to the SOA boundary
Increased StressConditions
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Failure DistributionsPrognostic Cell Approach
Prognostic Cell Host MOSFET
Time
Prognostic Distance
Techniques previously applied to CMOS IC’s:
• Hot carrier damage
• TDDB Gate Oxide Failure
• Metal Migration
• Radiation Effects
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Opto-Isolator failure
A degradation of 50% in the CTR is usually considered the failure point of the opto-isolator
Source: Fairchild Application note AN3001 “Optocoupler Input Drive circuits”
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Opto-Isolator Prognostic Solution
Prognostic technique
• Monitor the fall in output current due to CTR degradation
• Solution: Current monitor (QT-1410)
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Capacitors
• Electrolytics – Large capacity, but prone to problems in aging. – Aluminum – Reform dielectric problem; fail
shorts– Tantulum – aging of electrolyte; heating
• Ceramic (this SMPS)– Capacities have grown in recent years– Difficult to extract in-situ precursors
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Ceramic Capacitor failure
Degradation of Insulation Resistance (IR)
• High temperature and high voltage stresses
• Power dissipation due to current through ESR
• Pre-cursor – Capacitor displays an equivalent parallel resistance of about 1 MΩ.Source: Munikoti, Dhar, “Low voltage failures in MLCC: A
New accelerated test screen”
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Capacitor Prognostics Soln.
Disconnect load and ground gate of primary and secondary MOS switch, apply a small DC current to the capacitor and observe voltage at this node.
Φ1
Φ2
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Simulated results of Prognostics Solution
Simulated output voltage as the insulation resistance of thecapacitor degrades. The applied current to the capacitor is 1 µA.
0
1
2
3
4
5
6
100000 1000000 10000000 1E+08
IR (Ohms)
V(ou
t)
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PWM controller
• Breakdown of the discharging transistor inside the oscillator due to rapid charge-discharge
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PWM controller (Contd.)
Precursor• Increase in IDDT from
the supply
Solution• Current monitor
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QT-1410 (Current Monitor)High speed (5 MHz), High resolution (5µA)measurementPeak (IDDT) and/or charge (IDDQ) measurementSerial / Parallel measurement50 MHz Data sampling rate
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Voltage Monitor
• Isolation Amplifier– Optical isolation– Capacitive isolation
• ADC of QT-1410 is utilized
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Prognostic processing schemeWeighting fusion
(Implemented in software)• Weights based on
accuracy of prognostic technique.
• Determines how reliable the sensor is, in the range of measurement
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Data Extraction
P C R R e g is te rT A P C o ntro lle r
T D I
T D O
T C K
T M S
T A P – T e s t A c c e s s P o rtT D I – T e s t D a ta InT D O – T e s t D a ta O utT C K – T e s t C lo c kT M S – T e s t M o d e S e le c tP C R – P ro g no s t ic C e ll R e g is te r
P r in te d C irc u it B o a rd w ith IC ’sa nd E m b e d d e d P ro g no s t ic s
P ro g n o s tic C e lls
JTAG
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Possible Software Framework• Flexibility of adjusting
prognostic distance • Automatic/Manual
weight selection option
• Investigate ability to detect false alarms
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Phase I Items DeliveredAnalyzed components susceptible to failureDeveloped physics of failure models for those componentsDetermined precursors to failureDeveloped prognostic designs for the deviceThe proposed solution covers >80% of failures at low cost
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Phase II Objectives• Implement Phase I Electronic Prognostics Design using a COTS
DC to DC power converter
– Extract the necessary sensor information from the DC to DC Converter using a COTS backbone. Process the sensor information using a prototype software program
– Validate system performance of Electronic Prognostics via HALT tests on the DC to DC Converter
• Showcase concept of Electronic Prognostics for the JSF Aircraft and potential extensions to other electronic modules.
• Evaluation of weight reduction of JSF using prognostics to augment TMR Redundancy.
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Next Steps
• Invitation for SBIR Phase II Proposal is pending from JSF Program Office.
• Continuing work in semiconductor faults and prognostics with NASA and NAVY/Crane.
• Proposal pending for extensions to handle FPGA Failures with Raytheon Missile Systems and Honeywell.
• Have additional concepts and ideas to apply for other funded activities, for example:
– Continuous readout of remaining useful life using “Picket Fence” approach.– More work on FPGA and Memories Physics of Failure and precursor extraction– More work in mechanical faults (connectors and solder joints via partners)– Apply prognostic techniques to additional types of Avionics or EW modules.
• Ridgetop is looking for Development Partners !