Eye Know How
Signal Integrity Consulting
Services and KnowHow
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Company Facts
Founder:Dipl. Ing. (FH) Hermann Ruckerbauer
Founded:March 2009
Location:Office in Moos (Bavaria), GermanyNetwork partners in:
Munich (Design, Layout, CAD)Straubing (EMV)Deggendorf (Lab)China (Shandong und Shaanxi): Oulong Consulting
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Hermann RuckerbauerBackground
Study of Micro System Technology at University of Applied Sciences in Regensburg
Dipl. Ing. (FH) Micro System Technology
15 Years experience in Memory Development and High Speed Signaling
Siemens: Bench and Production testInfineon / Qimonda:
High Speed SignalingApplication test Interface standard definition
Holder of many patents EEE Publication:
Cascading Techniques for a High-Speed Memory Interface
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EKH - Services
Consulting for High Speed Signaling Consulting for memory implementation High speed simulation and measurement Power delivery simulation Model generation Logic Analyzer measurements Failure analysis (esp. on memory interfaces) PCB Design and Layout
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EKH - Cooperation partners
DKH – DesignKnowHow: Dr. Abdallah BachaPCB Design and LayoutRF Topics
ESFODA: Michael Vogl (www.esfoda.de)CAD customization and automation
SinePulse: Md Sayfullah (www.sinepulse.com)IT services (India)Hardware development (e. g. FPGA)
FH Deggendorf (www.fh-deggendorf.de)Measurement LabPCB X-section
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EKH - Cooperation partners
EMV – Testhaus (www.emv-testhaus.de)EMI / EMC compliance test
PCB ManufacturingEnzmann (www.enzmann.de)Ilfa (www.ilfa.de)
AssemblyMair Electronics (www.mair-elektronik.de)
China Business (Peter Poechmueller)Oulong Consulting (www.oulongconsulting.com)
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EKH - Customer examples
Happy CustomersTQ – SystemsKontronCongatecNumonyx3D-Plus
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Software Tools
Agilent ADSTime and Frequency domain simulationAnalog and Digital Simulation2.5D and 3D field solverData evaluation (measurement and simulation)
Power DeliverySigrity Power SI
Design and LayoutCadence AllegroMentor Hyperlinx/Pads
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1) Memory System Know How
2) DRAM device Know How
5) 2.5D Modeling: PCB Layout
6) 3D Modeling: Package and Connectors
3) Analog Simulation
7) Measurement Based Modeling
8) Signal Integrity Correlation Measurement
9) Logic Analyzer Memory Command Trace Evaluation
Services fromEyeKnowHow
10) Failure Analysis
11) Design and Layout Services
12) EMC / EMI Measurement and Consulting
4) Power Delivery Simulation
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1) Memory System Know How
Worked in the development of DDR1 / DDR2 / DDR3 / DDR4 Data and Command/Address bus architecture developmentMemory Device Specification
Consumer, Mobile, Desktop and Server system understandingDifferences in requirements and boundary conditions
System requirementsCache line size limitationsTurnaround times, Bandwidth and latencyPower limitations
ClockingSSC, Random and Deterministic Jitter
Controller functionalityController PCI register features (e. g. Delay shift, Driver strength, digital timings)
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DDR1 Motherboard example
Bus EndTerminationController
Slot/Connector
2
1
System CLK buffer
DIMMDRAM
Register/PLLMemory BUS
1) Memory System Know How
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DDR2 Testboard Example
Controller Emulator
Clock Buffer
DIMMs
DDR2 ODT
DDR1 MBT
1) Memory System Know How
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DD
DD
DD
DD
DD
DD
DD
DDT
D D D D D D DD D D D D D DDDT
CPU
1) Memory System Know How
DDR3 System example
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1) Memory System Know How
Close interaction between system Architecture and DRAM features IO specification (e. g. Input capacitance, driver and termination linearity)DLL functionalityMemory Device Specification
DRAM Core / architecture / process limitationSource for Latency ODOC package and impact on ArchitectureDRAM process and impact on speed and parasitics
DRAM packagingPlanar and stacked DRAM parasiticsWirebond and FCIP packaging
Single Die DRAM package
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3) Analog Simulation
Time Domain simulationSpice models (Lumped elements and BSIM Transistor based)S-ParameterIBIS
Frequency Domain simulationS-Parameter model generationModel comparison
Statistical Data evaluationAdding Random and deterministic JitterChannel characterization by Step Response
Data Eye evaluation Setup/HoldTiming budget calculation
Data eye generated out of Channel Step response
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Schematic example: 10 coupled lines on a Desktop PC Motherboard
Controller Driver
Controller Package
10 Coupled Via
Motherboard Lead In
T-Branch onMotherboard
DIMM socket
DIMM
3) Analog Simulation
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Simulation schematic example: 10 Coupled lines
Stub Resistor
DIMM Lead In
PackageDRAM load
3) Analog Simulation
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4) Power Delivery Simulation
PowerSI Simulation: PDN impedance over frequency
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Cadence and Mentor to ADS Layout transferSimulation in Momentum
Result: S-Parameter ModelCo-Simulation with ADS time/frequency domain simulationSignals and Power Supply IntegrityLayout accurate simulation
X-talk (intera- and inter layer)ReflectionsLosses
3 coupled lines of a CA bus on a DIMM
Large Logic package
5) 2.5D Modeling PCB Layout
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Package and Connector ModelingADS 3D Fieldsolver EMDS
Substrate routingBondwiresFBGA Package ballsSignal tracesPower planes
16 Coupled Bondwires: Signal and Power
6) 3D Modeling:Package / Connector
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Characterization of existing boardsMeasurement with VNATDR/TDT Characterization up to 20 GHz BW
TDR of Memory Riser Card
7) Measurement based Modeling
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Definition, Design and Layout of Characterization boardsLumped model fitting
FEXT
NEXT
Insertion LossBlue: ModelRed: Measurement
Testboard for S-Parameter Measurements
ADS model fitted to measurement results
7) Measurement based Modeling
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Physical X-sectionsMeasure what the manufacturer deliversCreate model based on real Hardware
7) Measurement based Modeling
Traces(transmission line) Vias
Dielectric(FR4)
Cross section of PCB with blind and micro vias
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Dataeye @ 5.3Gb Measured vs. Simulated / Ball vs. Pad
2x45 Ohm (matched to the differential PCB Channel impedance)
Measurement @ ball
Measurement @ ball
8) Correlation Measurements
Simulated @ ball
Simulated @ padSimulated @ ball
Simulated @ pad2x65 Ohm (initial Setting)
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Digital timing Trace evaluationSpec compliant timings / Finding timing violationsDigital Timing Settings / MRS setting
9) Logic Analyzer Command Trace evaluation
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Statistical Command sequence evaluationStatistical Access evaluationPerformance/Power Optimization
9) Logic Analyzer Command Trace evaluation
Command Bank_00 Bank_01 Bank_02 Bank_03 Bank_04 Bank_05 Bank_06 Bank_07 Banks_All TOTAL
RD 1289 402 1180 3884 0 0 0 7 0 6762WR 1107 402 0 7 0 0 0 4 0 1520ACT 45 31 31 30 0 0 0 1 0 138RD_AP 0 0 0 0 0 0 0 0 0 0WR_AP 0 0 0 0 0 0 0 0 0 0PRE 16 2 2 1 0 0 0 1 0 22PRE_A 0 0 0 0 0 0 0 0 30 30des 0 0 0 0 0 0 0 0 55843 55843nop 0 0 0 0 0 0 0 0 0 0MRS 0 0 0 0 0 0 0 0 0 0REF 0 0 0 0 0 0 0 0 31 31SRE 0 0 0 0 0 0 0 0 0 0SRX 0 0 0 0 0 0 0 0 0 0PDE 0 0 0 0 0 0 0 0 0 0PDX 0 0 0 0 0 0 0 0 0 0PRE_I 0 0 0 0 0 0 0 0 0 0PDCONT 0 0 0 0 0 0 0 0 0 0BST 0 0 0 0 0 0 0 0 0 0DPD 0 0 0 0 0 0 0 0 0 0
Timings:AL=3 BL=4 RL=4 TCCD=2 TCK=3750 TFAW=14 TPDN=0 TRAS=12 TRC=16 TRCD=4 TRFC=54TRP=4 TRRD=3 TRTP=2 TRTW=2 TWR=4 TWTR=2 VDD=1800 WIDTH=64 WL=3 XT=1
Name Min Max Name Min MaxtRAS_bank_0 12 2025 tRC_bank_0 16 2150tRAS_bank_1 259 2025 tRC_bank_1 761 2158tRAS_bank_2 450 2020 tRC_bank_2 718 2182tRAS_bank_3 1874 2030 tRC_bank_3 2032 2122tRAS_bank_4 - - tRC_bank_4 - -tRAS_bank_5 - - tRC_bank_5 - -tRAS_bank_6 - - tRC_bank_6 - -tRAS_bank_7 573 573 tRC_bank_7 - -tRAS_rank 12 2030 tRC_rank 16 2182
tRCD_bank_0 1 5 tRP_bank_0* 4 124tRCD_bank_1 1 11 tRP_bank_1* 5 1763tRCD_bank_2 1 6 tRP_bank_2* 5 268tRCD_bank_3 1 10 tRP_bank_3* 5 142tRCD_bank_4 - - tRP_bank_4* - -tRCD_bank_5 - - tRP_bank_5* - -tRCD_bank_6 - - tRP_bank_6* - -tRCD_bank_7 5 5 tRP_bank_7* 1089 1089tRCD_rank 1 11 tRP_rank 4 1763
tRFC 55 55tREFI 2072 2091tRRD 3 2070tCCD 2 77
Observed timings
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Memory test failure AnalyisEvaluate log files from Software Memory testsNarrow down failure reason
DQ vs. CA related failSingle DQ vs. DQS failRead vs. Write failDevice vs. Signal integrity related fail
Vref Margin test implementationAdjust VREF until fail and evaluate fail behavior
Timing Margin test implementationChange Controller delays (DQS and CLK) until fail and evaluate fail behavior
10) Failure analysis
12742808 12742822
FAILURE: possible bad address line at offset 0x00000000 = address 0x099C0038Expected value F663FFC7, Read value 099C0038Re-Read:Expected value F663FFC7, Read value 099C0038Expected value F663FFC7, Read value 099C0038Expected value F663FFC7, Read value 099C0038Expected value F663FFC7, Read value 099C0038
FAILURE: possible bad address line at offset 0x018A5141 = address 0x062D4504Expected value F9D2BAFB, Read value 8002BAFBRe-Read:Expected value F9D2BAFB, Read value 8002BAFBExpected value F9D2BAFB, Read value 8002BAFBExpected value F9D2BAFB, Read value 8002BAFBExpected value F9D2BAFB, Read value 8002BAFBSkipping to next test...
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DDR2 RDIMM 4GB
11) Design / Layout4GB DDR2 Registered
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Top view
CA BUS
Termination
RANK 0
ECC
Bottom viewTermination
CA BUS RANK 1
ECC
11) Design / Layout DDR3 Unbuffered VLP
DDR3 UBU VLP 1Rx8/2Rx8 ECC/non ECC: DIMM view
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D0 D1 D2
D4D8-ECCD3
D5 D6 D7
WEAK CASE39 ohm Termination
Setup/Hold: 481ps /334ps Setup/Hold: 423ps/406ps
11) Design / LayoutDDR3 Unbuffered VLP : Timing budget
Setup/Hold: 341ps/478ps
Setup/Hold: 298ps/513ps Setup/Hold: 273ps/512ps Setup/Hold: 226ps/524ps
Setup/Hold: 558ps/336ps Setup/Hold: 532ps/368ps Setup/Hold: 511ps/336ps
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system specification limits (e.g. for PC, Server)
measurement resultsDDR2 P-/R-DIMM on SUN Fire T2000
"Ontario"
12) EMC / EMI InvestigationsSpec. Limits & Measurements