EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 1
EE247Lecture 23
ADC Converters• Techniques to reduce flash ADC complexity
(continued)– Interleaved ADCs– Multi-Step ADCs
• Two-Step flash• Pipelined ADCs
– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall ADC performance
• Error correction by adding redundancy• Digital calibration
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 2
Summary Last Lecture
ADC Converters– Comparator design (continued)
• Comparator architecture examples
– Techniques to reduce flash ADC complexity (to be continued)• Interpolating• Folding
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 3
Time Interleaved Converters• Example:
– 4 ADCs operating in parallel at sampling frequency fs
– Each ADC converts on one of the 4 possible clock phases
– Overall sampling frequency= 4fs– Note T/H has to operate at 4fs!
• Extremely fast:Typically, limited by speed of T/H
• Accuracy limited by mismatch among individual ADCs (timing, offset, gain, …)
T/H
4fsADC
fs
ADC
ADC
ADC
Out
put C
ombi
ner
VIN
Dig
ital O
utpu
tfs+T/4
fs+2T/4
fs+3T/4
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 4
Two-Step Example: (2+2)Bits
• Using only one ADC: output contains large quantization error
• "Missing voltage" or "residue" ( -εq1)
• Idea: Use second ADC to quantize and add -εq1
0 1 2 300
01
10
11
0 1 2 3-1
-0.5
0
0.5
1
[LS
B]
ADC Input [LSB]
Vin
+Dout = Vin + εq1
2-bit ADC 2-bit ADC
???
ε q1
D out
Vin
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 5
Two Stage Example
• Use DAC to compute missing voltage• Add quantized representation of missing voltage• Why does this help? How about εq2 ?
Vin “Coarse“
+
Dout= Vin + εq1
2-bit ADC 2-bit ADC
“Fine“+-
2-bit DAC-εq1
-εq1+εq2
-εq1+εq2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 6
Two Step (2+2) Flash ADC
Vin Vin Vin
4-bit Straight Flash ADC Ideal 2-step Flash ADC
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 7
Two Stage Example
• Fine ADC is re-used 22 times• Fine ADC's full scale range needs to span only 1 LSB of coarse
quantizer
221
22
2 222 ⋅== refref
q
VVε
00 01 10 11
Vref1/22
−εq1
00
01
10
11
First ADC“Coarse“
Second ADC“Fine“VinVref1
Vref2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 8
Two-Stage (2+2) ADC Transfer Function
0000000100100011010001010110011110001001101010111100110111101111
CoarseBits(MSB)
FineBits(LSB)
Dout
VinVref1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 9
Residue or Multi-Step Type ADCIssues
• Operation:– Coarse ADC determines MSBs– DAC converts the coarse ADC output to analog- Residue is found by
subtracting (Vin-VDAC)– Fine ADC converts the residue and determines the LSBs– Bits are combined in digital domain
• Issue: 1. Fine ADC has to have precision in the order of overall ADC 1/2LSB 2. Speed penalty Need at least 1 clock cycle per extra series stage to resolve
one sample
(optional)Coarse ADC
(B1-Bit)Vin
Residue
DAC(B1-Bit)
Fine ADC(B2-Bit)
Bit
Com
bine
r
(B1+
B2)
-Bit
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 10
Solution to Issue (1)Reducing Precision Required for Fine ADC
• Accuracy needed for fine ADC relaxed by introducing inter-stage gain
– Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit case, precision required for fine ADC is reduced to 2-bit only!
– Additional advantage- coarse and fine ADC can be identical stages
Vin “Coarse“
+
Dout= Vin + εq1
2-bit ADC 2-bit ADC
“Fine“+-
2-bit DAC-εq1
-εq1+εq2
-εq1+εq2
G=2B1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 11
Solution to Issue (2)Increasing ADC Throughput
• Conversion time significantly decreased by employing T/H betweenstages– All stages busy at all times operation concurrent– During one clock cycle coarse & fine ADCs operate concurrently:
• First stage samples/converts/generates residue of input signal sample # n• While 2nd samples/converts residue associated with sample # n-1
Vin “Coarse“
+Dout= Vin + εq1
2-bit ADC
2-bit ADC
“Fine“+-
2-bit DAC-εq1
- εq1+εq2
T/H+(G=2B1)
T/H
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 12
Pipelined A/D Converters
• Ideal operation• Errors and correction
– Redundancy– Digital calibration
• Implementation – Practical circuits– Stage scaling
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 13
Pipeline ADCBlock Diagram
• Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!)
• Each stage performs coarse A/D conversion and computes its quantization error, or "residue“
• All stages operate concurrently
Align and Combine Data
Stage 1B1 Bits
Stage 2B2 Bits
Digital output(B1 + B2 + ... + Bk) Bits
Vin
MSB... ...LSB
Stage k Bk Bits
Vres1 Vres2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 14
Pipeline ADCCharacteristics
• Number of components (stages) grows linearly with resolution
• Pipelining– Trading latency for conversion speed– Latency may be an issue in e.g. control systems– Throughput limited by speed of one stage → Fast
• Versatile: 8...16bits, 1...200MS/s
• One important feature of pipeline ADC: many analog circuit non-idealities can be corrected digitally
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 15
Pipeline ADC Concurrent Stage Operation
• Stages operate on the input signal like a shift register• New output data every clock cycle, but each stage
introduces at least ½ clock cycle latency
Align and Combine Data
Stage 1B1 Bits
Stage 2B2 Bits
Digital output(B1 + B2 + ... + Bk) Bits
VinStage kBk Bits
φ1φ2
acquireconvert
convertacquire
...
...
CLKφ1
φ2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 16
Pipeline ADCLatency
[Analog Devices, AD 9226 Data Sheet]
Note: One conversion per clock cycle & 8 clock cycle latency
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 17
Pipeline ADCDigital Data Alignment
• Digital shift register aligns sub-conversion results in time
Stage 2B2 Bits
VinStage kBk Bits
φ1φ2
acquireconvert
convertacquire
...
...
+ +Dout
CLK CLK CLK
Stage 1B1 Bits
CLKφ1
φ2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 18
Cascading More Stages
• LSB of last stage becomes very small • Impractical to generate several Vref• All stages need to have full precision
VinADC
+-DACADC
B3 bitsB2 bitsB1 bits
Vref Vref /2B1 Vref /2(B1+B2) Vref /2(B1+B2+B3)
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 19
Pipeline ADC Inter-Stage Gain Elements
• Practical pipelines by adding inter-stage gain use single Vref• Precision requirements decrease down the pipe
– Advantageous for noise, matching (later), power dissipation
Vin ADCB3 bitsB2 bitsB1 bits
Vref
2B1
+-DACADC
Vref Vref Vref
2B22B3
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 20
Complete Pipeline StageVin +
-B-bitDAC
B-bitADC
D
-GVres
Vin0
0
Vref
−εq1
“ResiduePlot“
E.g.:B=2
G=22 =4
Vres
Vref
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 21
Pipeline ADC Single StageModel
Vin
−
Dout
-G V res
−εq
Σ
εq
Σ
Vres = Gxεq
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 22
Pipeline ADCErrors
• Non-idealities associated with sub-ADCs, sub-DACs and gain stages error in overall pipeline ADC performance
• Need to find means to tolerate/correct errors
• Important sources of error– Sub-ADC errors- comparator offset– Gain stage offset– Gain stage gain error– Sub-DAC error
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 23
Pipeline ADC Multi-Stage Model
1 q2 2out in,ADC q1
d1 d1 d 2
q( n 1) ( n 1) qnn 2 n 1
d( n 1)dj djj 1 j 1
G GD V 1 1
G G GG
.. . 1GG G
εε
ε ε− −− −
−
= =
⎛ ⎞ ⎛ ⎞= + − + − +⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠⎛ ⎞⎜ ⎟+ − +⎜ ⎟⎝ ⎠∏ ∏
ΣΣ
εq1
- G1
Σ
ΣΣ
εq2
- G2
Σ
ΣΣ
εq(n-1)
- Gn-1
Σ
Vin,ADC
Dout 1/Gd1 1/Gd2
Vres1 Vres2 Vres(n-1)
Σ
1/Gd(n-1)
εqnD1 D2 D(n-1)Dn
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 24
Pipeline ADC Model• If the "Analog" and "Digital" gain/loss is precisely matched:
∏+
⎟⎟⎠
⎞⎜⎜⎝
⎛∏×
⎟⎟⎠
⎞⎜⎜⎝
⎛∏××=
∏×
==
−
=≈
−
=≈
−
=−
=
1
12
1
12
1
11
1
log
2log
223log20
212
22log20.
log20..
n
jjnADC
n
jj
BADC
n
jj
B
n
jj
B
ref
ref
GBB
GB
G
G
V
V
NoiseQuantrmsSignalFSrmsRD
n
n
n
∏−
=
+= 1
1
, n
jj
qnADCinout
GVD
ε
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 25
Pipeline ADCObservations
• The aggregate ADC resolution is independent of sub-ADC resolution!
• Effective stage resolution Bj=log2(Gj)
• Overall conversion error does not (directly)depend on sub-ADC errors!
• Only error term in Dout contains quantization error associated with the last stage
• So why do we care about sub-ADC errors?Go back to two stage example
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 26
Pipeline ADCSub-ADC Errors
∏−
=
+= 1
1
, n
jj
qnADCinout
GVD
ε
1
2, G
VD qADCinout
ε+=
Grows outside ½ LSB bounds
Vin,ADC ADC2-bits
B1 =2-bits
Vref Vref
Vres1
V εq2Vin0
0
Vref
Vres1
ref
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 27
Pipeline ADC1st-Stage Comparator Offset
First stage ADC Levels:(Levels normalized to LSB)Ideal comparator threshold: -1, 0, +1Comparator threshold including offset: -1, 0.3, +1
Problem: Vres1 exceeds 2nd pipeline stage overload range
Missing Code!
Overall ADC Transfer Curve
Vres1
Vres2
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 28
Pipeline ADC Three Ways to Deal with Errors
• All involve "sub-ADC redundancy“
• Redundancy in stage that produces errors– Choose gain for residue to be processed
by the 2nd stage < 2B1
– Higher resolution sub-ADC
• Redundancy in succeeding stage(s)
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 29
(1) Inter-Stage Gain Following 1st stage < 2B1
• Choose G1 slightly less than 2B1
• Effective stage resolution could become non-integer B1eff=log2G1
• E.g. If G1=3.8B1eff =1.8-bit!
Ref: A. Karanicolas et. al., JSSC 12/1993Vin
Vref00
Vref
Vres1
Vin,ADCADCB1 bits
Vref Vref
εq2
Vres1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 30
Correction Through Redundancy
“enlarged” residuum still within input range of next stage
Overall ADC Transfer Curve
Vres1
Vres2
If G1=2 instead of 4 Only 1-bit resolution from first stage (3-bit total) No overall error!
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 31
(2) Higher Resolution Sub-ADC
• Keep G1=2B1 (e.g. keep G1=4)
• Add extra decision levels in sub-ADC (e.g. add 1 extra bit to 1st
stage)
• E.g. B1=B1eff+1
Ref: Singer et. al., VSLI1996
Vin
Vref00
Vref
Vres1
Vin,ADCADCB1 bits
Vref Vref
εq2
Vres1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 32
(3) Over-Range AccommodationThrough Increase in Following Stage Resolution
• No redundancy in stage with errors
• Add extra decision levels in succeeding stage
Ref: Opris et. al., JSSC 12/1998
Vin
Vref00
Vref
Vres1
Vin,ADCADCB1 bits
Vref Vref
εq2
Vres1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 33
Redundancy• The preceding analysis applies to any stage
in an n-stage pipeline• Can always perceive a multi-stage pipelined
ADC as a single stage + backend ADCVin
B4 bitsB3 bitsB2 bitsB1 bits
VinB2+B3+B4 bitsB1 bits
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 34
Redundancy• In literature, sub-ADC redundancy schemes
are often called "digital correction" – a misnomer!
• No error correction takes place• We can tolerate sub-ADC errors as long as:
– The residues stay "within the box", or– Another stage downstream "returns the residue to
within the box" before it reaches last quantizer• Let's calculate tolerable errors for popular
"1.5 bits/stage" topology
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 35
1.5 Bits/Stage Example
• Comparators placed strategically to minimize overhead
• G=2
• Beff=log2G=log22=1
• B=log2(2+1)=1.589...
Ref: Lewis et. al., JSSC 3/1992
Vin
Vref00
Vref
Vres1
Vos=Vref/8
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 36
3-Stage 1.5-bps Pipelined ADC
• All three stagesComparator with
offset
• Overall transfer curve
No missing codesSome DNL error
Ref: S. Lewis et al, “A 10-b 20-MS/s Analog-to-Digital Converter,” J. Solid-State Circ., pp. 351-8, March 1992
Overall Transfer Curve
Vres1
Vres2
Vres3
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 37
Pipeline ADCErrors
• Non-idealities associated with sub-ADCs, sub-DACs and gain stages error in overall pipeline ADC performance
• Need to find means to tolerate/correct errors
• Important sources of error– Sub-ADC errors- comparator offset– Gain stage offset– Gain stage error– Sub-DAC error
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 38
Inter-Stage Amplifier Offset
• Input referred converter offset – usually no problem• Equivalent sub-ADC offset - accommodated through
adequate redundancy
+
ADC DAC-
D
VresVin G+
Vos +
-Vos
+
Vos
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 39
Pipeline ADCErrors
• Non-idealities associated with sub-ADCs, sub-DACs and gain stages error in overall pipeline ADC performance
• Need to find means to tolerate/correct errors
• Important sources of error– Sub-ADC errors- comparator offset– Gain stage offset– Gain stage gain error– Sub-DAC error
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 40
Gain Stage Gain Error
1, 1
1
2 ( 1) ( 1)22 1
1 2 ( 1)
1 1
1
1 ... 1
out in ADC qd
q q n n qnn n
d d d ndj dj
j j
GD VG
GGG G G
G G
ε
ε ε
δδ
ε− −− −
−
= =
⎛ ⎞+= + −⎜ ⎟+⎝ ⎠⎛ ⎞⎛ ⎞
+ − + + − +⎜ ⎟⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠∏ ∏
ΣΣ
εq1
- G1+δ
Σ
ΣΣ
εq2
- G2
Σ
ΣΣ
εq(n-1)
- Gn-1
Σ
Vin,ADC
Dout 1/(Gd1+δ ) 1/Gd2
Vres1 Vres2 Vres(n-1)
Σ
1/Gd(n-1)
εqnD1 D2 D(n-1)Dn
Small amount of gain error can be tolerated
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 41
Interstage Gain Error
-1 -0.5 0 0.5 11
0
1First Stage Residue (Gain Error)
Vin
Vre
s
1 0.5 0 0.5 11
0
1Converter Transfer Function (Gain Error)
Vin
Dou
t1 0.5 0 0.5 1
0.2
0
0.2Transfer Function Error(Gain Error)
Vin
Dou
t(ide
al) -
Dou
t
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 42
Gain Errors
• Gain error can be compensated in digital domain – "Digital Calibration"
• Problem: Need to measure/calibrate digital correction coefficient
• Example: Calibrate 1-bit first stage
• Objective: Measure G in digital domain
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 43
ADC Model
( )DACinres VVGV −⋅=1
2/)1(0)0(
refDAC
DAC
VDVDV
====
2
VrefG Vin⎛ ⎞⎜ ⎟⋅ −⎝ ⎠
inG V⋅
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 44
Calibration – Step 1
Vin= const.+
-1-bitDAC
1-bitADC
D
GVres1
(1)
BackendDback
(1)
MUX
“1“
Vref
( )( )
storeVVV
GD
VVGV
ref
refinback
refinres
→−
⋅=
−⋅=
2/
2/
)1(
)1(1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 45
Calibration – Step 2
Vin= const.+
-1-bitDAC
1-bitADC
D
GVres1
(2)
BackendDback
(2)
MUX
“0“
Vref
( )( ) storeVVGD
VGV
ref
inback
inres
→−⋅=
−⋅=0
0)2(
)2(1
EECS 247 Lecture 23 Mult-Step & Pipeline ADCs © 2007 H.K. Page 46
Calibration – Evaluate
( )
( )
GDD
VVGD
VVV
GD
backback
ref
inback
ref
refinback
⋅=−
−−−−−−−−−−−−−−−−−
−⋅=−
−⋅=
21
0
2/
)2()1(
)2(
)1(
• To minimize the effect of backend ADC noise perform measurement several times and take the average