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ECE501 F11, Introduction, Slide 2
Course Syllabus
ECE 501 Contemporary Digital Systems
Introduction to sequential logic, state machines, high-performance
digital systems, theory and application of modern design, alternative
implementation forms and introduction to HDL, productivity,
recurring and non-recurring costs, flexibility, testability, software
drivers, and hardware/software integration.
Prerequisite: ECE 215 or equivalent
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ECE501 F11, Introduction, Slide 3
Text Book
Advanced Digital Design
with the
Verilog HDL
by Michael Ciletti
Publisher
Prentice Hall
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ECE501 F11, Introduction, Slide 4
Course Outline
Introduction
Review of Boolean Algebra and Combinatorial Logic
HDL Approach to Logic Design
Introduction to Verilog HDL
Structural and Behavioral Specification
Gates and combinatorial logic
Flip-flops and Registers
Clocked Circuits
Simulation
Procedural Specification
Module Design and Validation
Finite State Machines Moore and Mealy Machines
System on a Programmable Chip (SOPC) Introduction
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ECE501 F11, Introduction, Slide 5
Laboratory and Tools
You will need access to a laptop to complete the lab assignments
Labs will be done in our class room using the Altera DE2 board
Programs will be written in Verilog using the Altera Quartus II design
tools
Turn in projects and design homework online using Isidore All executable programs will be demonstrated in class
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ECE501 F11, Introduction, Slide 6
Projects and Grading
Grades based on homework assignments, projects, and final project
Assignments 60%
Final Exam 40%
Course will combine lecture and lab projects
Assignments
1. Theorem proofs
2. 4 bit / 16 bit adder
3. Encoders / Decoders
4. Shift Register
5. 16 Bit ALU6. Stack Memory
7. ALU Tester
8. Serial Port
The assignments will be implemented with
HDL code and tested with the Quartus
simulator and then on the Altera DE2 board.
Each assignment will consist of a written
report outlining your design considerationsand choices, a copy of the HDL files used,
simulation results and test results. If you
have used test software, include those files
along with a description.
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ECE501 F11, Introduction, Slide 7
Office Hours
Room KL341-I
Tuesday and Thursday
12:30PM to 1:15PM
Other times by appointment
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ECE501 F11, Introduction, Slide 8
Lecture Notes & Class Assignments
Lecture notes will be posted on Isidore To use Isidore go to http://isidore.udayton.edu
Login using your LDAP Name and Password
Once logged in you should see all of your classes for this term
Select ECE_501Section 01 (IntroDigital Systms)
Lecture notes posted under Resources
http://isidore.udayton.edu/http://isidore.udayton.edu/8/4/2019 ECE 501 F11 Session 1a Intro
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ECE501 F11, Introduction, Slide 9
Isidore trial run
Due Tuesday, 8/29/2011
Using Isidore submit the following information
Your name (first last)
Your email address(es)
Use the assignment named Name and email
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ECE501 F11, Introduction, Slide 10
Reports for Assignments and Projects
Acceptable formats
Microsoft Word
Must have a report
What you were trying to do?
What you accomplished?
Explain results What went right or wrong
Did you get what was expected
Include Source code (HDL) and simulation screen shots
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ECE501 F11, Introduction, Slide 11
Where did this
value come from
Explain the values you get
Use Decimal
format
No need to show both thecombined bus and theindividual signals
Show multiple examples
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ECE501 F11, Introduction, Slide 13
Good Example
Simulation of the 16-bit ripple carry adder:
6 + 3 = 9
8 + 4 + Carry = 13 10 + 5 + Carry = 0
Show that you obtained
the expected results
Explain signal changes that occur
What is this?