Dynamic and Dynamic and Pass-Transistor Pass-Transistor
LogicLogic
Dynamic and Dynamic and Pass-Transistor Pass-Transistor
LogicLogicProf. Vojin G. OklobdzijaProf. Vojin G. Oklobdzija
References References (used for creation of the presentation material):(used for creation of the presentation material):1.1. Masaki, Masaki, “Deep-Submicron CMOS Warms Up to High-Speed Logic”,“Deep-Submicron CMOS Warms Up to High-Speed Logic”, IEEE IEEE
Circuits and Devices Magazine, November 1992.Circuits and Devices Magazine, November 1992.2.2. Krambeck, C.M. Lee, H.S. Law, Krambeck, C.M. Lee, H.S. Law, “High-Speed Compact Circuits with “High-Speed Compact Circuits with
CMOS”CMOS”, IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982., IEEE Journal of Solid-State Circuits, Vol. SC-13, No 3, June 1982.3.3. V.G. Oklobdzija, R.K. Montoye, V.G. Oklobdzija, R.K. Montoye, “Design-Performance Trade-Offs in CMOS-“Design-Performance Trade-Offs in CMOS-
Domino Logic”Domino Logic”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April , IEEE Journal of Solid-State Circuits, Vol. SC-21, No 2, April 1986.1986.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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References:References:
4. Goncalves, H.J. DeMan, “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures”, IEEE Journal of Solid-State Circuits, Vol. SC-18, No 3, June 1983.
5. L.G. Heller, et al, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family”, in 1984 Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1984.
6. L.C.M.G. Pfennings, et al, “Differential Split-Level CMOS Logic for Subnanosecond Speeds”, IEEE Journal of Solid-State Circuits, Vol. SC-20, No 5, October 1985.
7. K.M. Chu, D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4, August 1987.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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References:References:Pass-Transistor Logic:
8. S. Whitaker, “Pass-transistor networks optimize n-MOS logic”, Electronics, September 1983.
9. K. Yano, et al, “A 3.8-ns CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 25, No 2, April 1990.
10. K. Yano, et al, “Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs", Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
11. M. Suzuki, et al, “A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic”, Journal of Solid-State Circuits, Vol. 28. No 11, November 1993.
12. N. Ohkubo, et al, “A 4.4-ns CMOS 54x54-b Multiplier Using Pass-transistor Multiplexer”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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References:References:
13. V. G. Oklobdzija and B. Duchêne, “Pass-Transistor Dual Value Logic For Low-Power CMOS,” Proceedings of the 1995 International Symposium on VLSI Technology, Taipei, Taiwan, May 31-June 2nd, 1995.
14. F.S. Lai, W. Hwang, “Differential Cascode Voltage Switch with the Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems”, Proceedings of the 1993 International Symposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995
15. A. Parameswar, H. Hara, T. Sakurai, “A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications”, Proceedings of the Custom Integrated Circuits Conference, San Diego, California, May 1-4, 1994.
16. T. Fuse, et al, “0.5V SOI CMOS Pass-Gate Logic”, Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco February 8, 1996.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor Logic Pass-Transistor Logic
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor LogicPass-Transistor Logic
0 10
1
0 1
B
A
1 0
A
A
B
B
F
F
B B
(a)XOR function implemented with pass-transistor circuit
(b)Karnaough map showing derivation of the XOR function
(a) (b)
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor LogicPass-Transistor Logic
A
A
X
Y
F
X Y F0 0 00 1 A1 01 1 10 B AB01 B1B 0B 1B 0 A+BB 1BB BBB B B
B
B
B
B
B
A
BA
BABA
BABA
BA
BA
BA
General topology of pass-transistor function generator
Karnaough map of 16 possible functions that can be realized
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor LogicPass-Transistor LogicA A B B
P0
P1
P2
P3
F(A,B)
Function generator implemented with pass-transistor logic
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor LogicPass-Transistor Logic
A
B=Vdd
B
Fmax = Vdd-Vth
A=Vdd
Vth+
-
Cout
Vdd
Vdd
Fmax = Vdd-Vth
Cout
Vth+
-Vth
+
-
Vdd
(a) (b)
Voltage drop does not exceed Vth when there are multiple transistors in the path
Threshold voltage drop at the output of the pass-transistor gate
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Pass-Transistor LogicPass-Transistor Logic
A=0V
In=VddFmax= Vdd
A=Vdd
Vth+
-
Cout
Vdd
Vdd
Cin
Vth+
-
(a) (b)
+
-Vdd
ON
+Vdd
Elimination of the threshold voltage drop by:
(a)pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Complementary Pass-Transistor Complementary Pass-Transistor Logic (CPL) Logic (CPL)
f
Inputs
Pass Variables
ControlVariables
F F
f
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Basic logic functions in CPL Basic logic functions in CPL A ABB
B
B
A ABB
B
B
A B
A B
A A
B
B
A A
A ABB
C
C
A B
A C B C
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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CPL LogicCPL Logic
AA
S S
A A
B
B
C
C
SS(a) (b)
B
B
Q Qb
n1 n2
n4n3
CPL provides an efficient implementation of XOR function
XOR gateSum circuit
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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CPL Inverter CPL Inverter
OutputInput
Feedback Inverter
Output Inverter
Level RestorationTransistor
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic Double Pass-Transistor Logic (DPL): (DPL):
A
B
A B B A
VDD
B
A
OO
A B
A
B
A B BA
B
A
OO
B
A
B A B A
B
A
A B
XOR/XNOR
AND/NAND
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic Double Pass-Transistor Logic (DPL): (DPL):
(a) (b)
B
B
A A
C
C
O
Q Qb
n1
p1 n2
p2 n1
p1 n2
p2
B
B
A A
SSO
XOROne bit full-adder:
Sum circuit
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic Double Pass-Transistor Logic (DPL): (DPL):
A
A
B
B
Vcc
A
A
B
B
Vcc
C C
S
S
Vcc
BufferMultiplexer
OR/NOR
AND/NAND
The critical path traverses two transistors only (not counting the buffer)
DPL Full Adder
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Formal Method for CPL Logic Formal Method for CPL Logic DerivationDerivation
Markovic et al. 2000Markovic et al. 2000
(a) Cover the Karnaugh-map with largest possible cubes (overlapping allowed)
(b)Express the value of the function in each cube in terms of input signals
(c) Assign one branch of transistor(s) to each of the cubes and connect all the branches to one common node, which is the output of NMOS pass-transistor network
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Formal Method for P-T Logic Formal Method for P-T Logic DerivationDerivation
Complementary function can be implemented from the same circuit structure by applying complementarity principle:
Complementarity Principle: Using the same circuit topology, with pass signals inverted, complementary logic function is constructed in CPL.
By applying duality principle, a dual function is synthesized:
Duality Principle: Using the same circuit topology, with gate signals inverted, dual logic function is constructed.
Following pairs of basic functions are dual:AND-OR (and vice-versa)
NAND-NOR (and vice-versa)XOR and XNOR are self-dual (dual to itself)
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Derivation of P-T LogicDerivation of P-T Logic
0 0
0 1
0 1
0
1A
B
L 1 L 2
B
B
AND
A B
L 2 L 1
1 1
1 0
0 1
0
1A
B
L 1 L 2
1 1
1 0
0 1
0
1
A
B
L 1 L 2
B
B
NAND (OR)
A B
L 2 L 1
B
B
OR
A B
L 1 L 2
B
A A
B
A
B
A
B
AND NAND
OR OR
Copmplementarity: AND NAND; Duality: AND OR
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Derivation of CPL LogicDerivation of CPL Logic
Duality: AND ORNAND NOR
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
B
B
AND
A A
B
B
OR NOR
A A
(c)
NAND
(b)
B B BB
L 2 L 1
Complementarity: AND NAND
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Two-Input Function with balanced Two-Input Function with balanced input loadinput load
Each input A, B, or A, B has FO=2
B
B
AND
A B
A
A
NAND
B A
B
B
OR
B A
A
A
NOR
A B
(a) (b)
gatedrainin CCC
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Derivation of CPL LogicDerivation of CPL Logic
(a) XOR function Karnaugh map, (b) XOR/XNOR circuit
0 1
1 0
BA 0 1
0
1A
B
L 1 L 2
(a)
B
B
XOR
A A
XNOR
(b)
A A
L 2 L 1
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Synthesis of three-input CPL Synthesis of three-input CPL logic logic
0 0
0 0
BC
A 00 01
0
1A
C
L 3
L 2
(a)
A
B
AND
C
(b)
11 10
0 0
1 0
L 1
NAND
C
A
B
B
A B A B
L 3L 2L 1
(a) AND function Karnaugh map, (b) AND/NAND circuit
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Circuit realization of 3-input Circuit realization of 3-input AND/NAND functionAND/NAND function
0 0
0 0
BC
A 00 01
0
1A
C
(a)
A
B
AND
C
(b)
11 10
0 0
1 0
NAND
C
A
B
B
A B A B
C 3
C 2
C 1
C 1 C 2 C 3
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic Double Pass-Transistor Logic (DPL): (DPL):
Synthesis RulesSynthesis Rules1. Two NMOS branches can not be overlapped
covering logic 1s. Similarly, two PMOS branches can not be overlapped covering logic 0s.
2. Pass signals are expressed in terms of input signals or supply. Every input vector has to be covered with exactly two branches.
At any time, excluding transitions, exactly two transistor branches are active (any of the pairs NMOS/PMOS, NMOS/NMOS and PMOS/PMOS are possible), i.e. they both provide output current.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Double Pass-Transistor Logic Double Pass-Transistor Logic (DPL): (DPL):
Synthesis RulesSynthesis RulesComplementarity Principle: Complementary logic
function in DPL is generated after the following modifications:
• Exchange PMOS and NMOS devices. Invert all pass and gate signals
Duality Principle: Dual logic function in DPL is
generated when:
• PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged.
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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DPL Synthesis: DPL Synthesis:
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
A B
B A
(b)
L
L
3
4
BA
GND GND
AND
A B
B A
BA
NAND
+V DD +V DD
L 2L 4
L 1L 3
(a) AND function Karnaugh map (b) AND/NAND circuit
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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DPL Synthesis: DPL Synthesis: OR/NOR circuitOR/NOR circuit
A B
BA
B A
OR
A B
B A
BA
GND GND
NOR
+V DD +V DD
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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XOR/XNOR in DPLXOR/XNOR in DPL
Circuit realization of 2-input XOR/XNOR function in DPL, with balanced input load
0 1
1 0
BA 0 1
0
1A
B
(a)
B B
A A
(b)
AA
B B
XNOR
B B
A A
AA
B B
XOR
(PMOS)
(NMOS)
(PMOS)
(NMOS)
C 4
C 3
C 1 C 2
C 1 C 2
C 3C 4
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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DPL Synthesis: DPL Synthesis:
0 0
0 1
BA 0 1
0
1A
B
L 1 L 2
(a)
A B
B A
(b)
L
L
3
4
BA
GND GND
AND
A B
B A
BA
NAND
+V DD +V DD
L 2L 4
L 1L 3
AND function Karnaugh map AND/NAND circuit
A B
BA
B A
OR
A B
B A
BA
GND GND
NOR
+V DD +V DD Duality Principle: PMOS and NMOS devices are exchanged, and VDD and GND signals are exchanged:AND ORNAND NOR
Complementarity Principle: Exchange PMOS and NMOS devices. Invert all pass and gate signalsAND NAND
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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DVL LogicDVL LogicAdvantage of CPL and DPL were recognized in DVL which attempts to generalize pass-transistor networks and minimize the number of transistors and input loads.
Rules:
1. Cover all input vectors that produce “0” at the output, with largest possible cubes (overlapping allowed) and represent those cubes with NMOS devices, with sources connected to GND
2. Repeat step 1 for input vectors that produce “1” at the output and represent those cubes with PMOS devices, with sources connected to Vdd
3. Finish with mapping input vectors, not mapped in steps 1 and 2 (overlapping with cubes from steps 1 and 2 allowed) that produce”0” or “1” at the output. Represent those cubes with parallel NMOS (good pull-down) and PMOS (good pull-up) branches, with sources connected to one of the input signals
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Two input AND/NAND in DVL LogicTwo input AND/NAND in DVL Logic
Circuit realization of 2-input AND/NAND function in DVL
0 0
0 1
BA 0 1
0
1A
B
C 1
(a)
B
A
(b)
C 3
BA
AND
A
B
BA
NAND
Vdd Vdd
( A*)
( B* )
C 2
C 3 C 1
C 2
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Two input OR/NOR in DVL LogicTwo input OR/NOR in DVL Logic
Circuit realization of 2-input OR/NOR circuit in DVLXOR/XNOR realization is identical to that of DPL.
B
A
A
NOR
A
B
BA
OR
Vdd Vdd
B
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Three input AND function in DVL Three input AND function in DVL LogicLogic
0 0
0 0
BC
A 00 01
0
1A
C
(a)
AND
(b)
11 10
0 0
1 0 A B B B
A A
C
B
C 3
C 2
C 1
C 2 C 1 C 3 C 3
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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Three input OR/NOR in DVLThree input OR/NOR in DVL
Circuit realization of 3-input OR/NOR functions in DVL
NOR
A B B B
A A
C
OR
A B B B
A A
CV dd
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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ComparisonComparison
Realization
# of input signal
s
Signal terminatio
n
Trans.Count
Output load
CMOS 9 10G 10 4S
DVL (b) 9 8G + 6S 8 6S
DVL (c) 9 7G + 3S 7 4S
TABLE I. Realizations of 3-input function F=B’C+ABC’
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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ComparisonComparison
Realizations of 3-input function F=B’C+ABC’ (a) Standard CMOS, (b) DVL, (c) DVL
0 1
0 1
BC
A 00 01
0
1A
C
F
11 10
0 0
0 1
B C
C
C
B
B
B
A
A B C
Vdd
0 1
0 1
BC
A 00 01
0
1A
C
11 10
0 0
0 1
B
0 1
0 1
BC
A 00 01
0
1A
C
11 10
0 0
0 1
B
C
B
C
C
B C B
F
BCC
A
B
B
A
B B
C
F
C
B
C
B
C
A
(a) (b) (c)
B C A B CF = +
C 2 C 1
C 2 C 1
C 1
C 1
C 2
C 2
C 3
C 3
C 3C 2C 1 C 1 C 2
C 3
C 2C 3C 3
Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design
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ConclusionConclusionGeneral rules for synthesizing logic gates in three
representative pass-transistor techniques were shown.
An algorithmic way for generation of various circuit topologies (complementary and dual circuits) is discussed.
Generation of circuits with balanced input loads is suitable for library based designs is possible if complementarity and commutative principles are applied.
This lays the foundation for development of computer aided design (CAD) tools capable of generating fast and power-efficient pass-transistor logic.