Clocked Synchronous State Machine Design
•Design a clocked synchronous state machine with two inputs, A and B and a single output Z that is equal to 1 if:–A has the same value at each of the two previous clock ticks, or–B has been 1 since the last time that the first condition was true.
•Otherwise Z should be 0.
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
Output00 01 11 10 Z
Initial State INIT 0
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 0Got a 1 on A A1 0
S*
MeaningInput - AB
S
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
• Try:– (A,B) = (0,0),(0,0),(0,1),(0,0)– (A,B) = (0,0),(0,0),(0,1),(1,0)
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK ? OK OK ? 1
S*
MeaningInput - AB
S
Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
• Try the sequence (A,B) = (1,0), (1,0), (1,1), (0,0).
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Two equal, A=0 last OK0 OK0 OK0 OK1 A1 1Two equal, A=1 last OK1 A0 OK0 OK1 OK1 1
S*
MeaningInput - AB
S
State Minimization
• Equivalence:– For a given input, two states are
equal if their outputs are the same, and their next state is the same or an equivalent one.
Output0 1 Z
A A B 0B C D 0C A D 0D E F 1E A F 1F G F 1G A F 1
S*
Input - XS
State Assignment• Procedures concerned with
methods for assigning binary values to states in such a way as to reduce the cost of the combinational circuit that drives the flip-flops.
• Methods:– Choose an initial coded state
which the machine can easily be forced to at reset.
– Minimize the number of state variables that change on each transition.
– Maximize the number of state variables that do not change
State Assignment• Methods:– Exploit symmetries by assigning
state variables differing only in one bit to both states or group of states.
– If there are unused states, then choose the best of the available state-variable combinations to achieve the foregoing goal.
– Decompose the set of state variables into individual bits or fields, with well defined meaning.
– Consider using more than the minimum number of state variables to make decomposed assignments possible.
State Assignment
Assignment Table 7-7Possible state assignments for the state machine in Table 7-6.
State Name
Simplest Q1–Q3
Decomposed Q1–Q3
One-hot Q1–Q5
Almost One-hot Q1–Q4
INIT 000 000 00001 0000
A0 001 100 00010 0001
A1 010 101 00100 0010
OK0 011 110 01000 0100
OK1 100 111 10000 1000
• Unused states:– Minimal risk – assumes that it is
possible for the state machine to get into one unused or illegal state.
– Minimal cost – assumes that the state machine will never enter an unused state.
Designing State Machines Using State Diagrams
• State-diagram design is simpler but it is more prone to errors.– State table is an exhaustive listing
of the next states for each state/input combination. No ambiguity is possible.
– When constructing a state diagram there is no guarantee that the transition expressions written on the arcs leaving a particular state, cover all input combination exactly once.
Designing State Machines Using State Diagrams
• Design a state machine to control the tail lights of a 1965 Ford Thunderbird. The tail lights are composed of three light on each side which operate for the turns in the manner shown in the picture below.
ZOTTFFSCALIFORNIA
RA RB RCLC LB LA
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Designing State Machines Using State Diagrams
LC(a) LB LA RA(b) RB RC
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
• The state machine has:– Three inputs: left, and right turns,
and hazard.– Six outputs: LA, LB, LC, RA, RB,
and RC.– Free running clock with frequency
equal to the flashing rate.
Designing State Machines Using State Diagrams
LR3
R1R3
R2
IDLE
L1
L2
LEFT1
1
RIGHT1
1 1
HAZ
L3
(LEFT + RIGHT + HAZ)′
1 1
State
IDLE
L1
L2
L3
R1
R2
R3
LR3
LC
0
0
0
1
0
0
0
1
LB
0
0
1
1
0
0
0
1
LA
0
1
1
1
0
0
0
1
RA
0
0
0
0
1
1
1
1
RB
0
0
0
0
0
1
1
1
RC
0
0
0
0
0
0
1
1
Output Table
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
• LA = L1+L2+L3+LR3• LB = L2+L3+LR3• LC = L3+LR3• RA = R1+R2+R3+LR3• RB = R2+R3+LR3• RC = R3+LR3
Designing State Machines Using State Diagrams
• Mutual exclusion: For each state the logical product of each pair of transition expression on arcs leaving that state is zero.
• All inclusion: For each state the logical sum of the transition expressions on all arcs leaving the state is one.
LR3
R1R3
R2
IDLE
L1
L2
LEFT • HAZ′ • RIGHT′1
1
RIGHT • HAZ′ • LEFT′1
1 1
HAZ + LEFT • RIGHT
L3
(LEFT + RIGHT + HAZ)′
1 1
Designing State Machines Using State Diagrams
LR3
R1R3
R2
IDLE
L1
L2
LEFT • HAZ′ • RIGHT′
1
1
RIGHT • HAZ′ • LEFT′ 1
HAZ′ HAZ′ HAZ
HAZ + LEFT • RIGHT
L3
(LEFT + RIGHT + HAZ)′
HAZ′ HAZ′ HAZ
HAZ
HAZ
Designing State Machines Using State Diagrams
• IDLE state of 000.• Q1 and Q0 are used to count in gray code
sequence (IDLE→L1→L2→L3→IDLE) (IDLE→R1→R2→R3→IDLE).
• Q2 identifies LEFT or RIGHT turn.• HAZ state of 100.
Table 7 -16State assignment for T-bird tail-lights state machine.
State Q2 Q1 Q0
IDLE 0 0 0
L1 0 0 1
L2 0 1 1
L3 0 1 0
R1 1 0 1
R2 1 1 1
R3 1 1 0
LR3 1 0 0
Designing State Machines Using State Diagrams
S Q2 Q1 Q0 Transition Expression S∗ Q2∗ Q1∗ Q0∗ Table 7-17 Transition list for T-bird tail-lights state machine.
IDLE 0 0 0 (LEFT + RIGHT + HAZ)′ IDLE 0 0 0
IDLE 0 0 0 LEFT ⋅ HAZ′ ⋅ RIGHT′ L1 0 0 1
IDLE 0 0 0 HAZ + LEFT ⋅ RIGHT LR3 1 0 0
IDLE 0 0 0 RIGHT ⋅ HAZ′ ⋅ LEFT′ R1 1 0 1
L1 0 0 1 HAZ′ L2 0 1 1
L1 0 0 1 HAZ LR3 1 0 0
L2 0 1 1 HAZ′ L3 0 1 0
L2 0 1 1 HAZ LR3 1 0 0
L3 0 1 0 1 IDLE 0 0 0
R1 1 0 1 HAZ′ R2 1 1 1
R1 1 0 1 HAZ LR3 1 0 0
R2 1 1 1 HAZ′ R3 1 1 0
R2 1 1 1 HAZ LR3 1 0 0
R3 1 1 0 1 IDLE 0 0 0
LR3 1 0 0 1 IDLE 0 0 0
Feedback Sequential Circuits
• Fundamental mode circuits:– Most common example of
feedback sequential circuits.– Inputs are not normally allowed
to change simultaneously.• Feedback sequential circuits
may be Mealy or Moore circuits.
• A circuit with n feedback loops has n binary state variables and 2n states.
Feedback Sequential Circuits
• Analysis:– Assumes that input changes occur one
at a time to allow enough time between successive changes for the circuit to settle into a internal stable state.
– Break the feedback loops so that the next value stored in each loop can be predicted as a function of the circuit inputs and the current value stored in all loops.
D
C
(C • D)′
(C • D′)′
C • D′+Y′
C • D+(C • D′+Y′)′
D′
Q
QN
Y∗Y
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Feedback Sequential Circuits
D
C
(C • D)′
(C • D′)′
C • D′+Y′
C • D+(C • D′+Y′)′
D′
Q
QN
Y∗Y
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
C D
Y 00 01 11 10
0 0 0 1 0
1 1 1 1 0
Y*
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
• Y* = (C D ) + (C D’ + Y’)’• Y* = C D + C’ Y + D Y
• Q = Y* = C D + C’ Y + D Y• QN = C D’ + Y’
Feedback Sequential Circuits
• Total state: combination of internal state(value of feedback loop) and input state (current input value) .
• Stable total state: Total state whose next state predicted by the state table is the same as the current internal state.
• Unstable total state: Total state whose next state predicted by the state table is the same as the current internal state.
• Note that Q and QN are outputs, not state variables.
C D
Y 00 01 11 10
0 0 0 1 0
1 1 1 1 0
Y*
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
C D
S 00 01 11 10
S0 S0 , 01
, 10
, 01 , 01
, 10
, 11
, 10 , 01
S0 S1 S0
S1 S1 S1 S1 S0
S*, Q QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Feedback Sequential Circuits
C D
S 00 01 11 10
S0 S0 , 01
, 10
, 01 , 01
, 10
, 11
, 10 , 01
S0 S1 S0
S1 S1 S1 S1 S0
S*, Q QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
C D
S 00 01 11 10
S0 S0 , 01
, 10
, 01 , 01
, 10
, 11
, 10 , 01
S0 S1 S0
S1 S1 S1 S1 S0
S*, Q QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
• Simultaneous input changes don’t always cause unpredictable behavior.
Races• A race is said to occur when multiple
internal variables change state as a result of a single input changing state.
• Noncritical race: the final state does not depend on the order in which the state variables change.
• Starting at state 011/00 change CLK to 1.
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 000
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
Races• Critical race: the final state depends on the
order in which the state variables change.• State 010/10 has been changed from 000 to
110.• Try starting at state 011/00 change CLK to
1 and see what state you end up at.
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 110
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
State Tables and Flow Tables
• Once it has been determined that a transition table does not have any critical races, the state-variable combinations can be named and outputs can be determined to obtain a state/output table.
CLK D
S 00
S0 S2 , 01
S1 S3 , 10
S2 S2 , 01
S3 S3 , 10
S* , Q QN
S4 S2 , 01
S5 S3 , 10
S6 S2 , 01
S7 S3 , 10
01
S2 , 01
S3 , 10
S6 , 01
S7 , 10
S2 , 01
S3 , 10
S6 , 01
S7 , 10
11
S0 , 01
S0 , 10
S6 , 01
S7 , 10
S7 , 11
S7 , 10
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
S0 , 01
S7 , 11
S7 , 10
S7 , 11
S7 , 10
CLK D
Y1 Y2 Y3 00 01 11 10
000 010 010 000 000
001 011 011 000 000
010 010 110 110 000
011 011 111 111 000
Y1∗ Y2∗ Y3∗
100 010 010 111 111
101 011 011 111 111
110 010 110 111 111
111 011 111 111 111
State Tables and Flow Tables
• Flow table eliminates:– Rows for unused internal states (states
that are stable for no input combination).– Next state entries for total states that
cannot be reached from a stable total state as the result of a single input change.
• It eliminates multiple hops and show only the ultimate destination of each transition.
CLK D
S 00
S0 S2 , 01
S1 S3 , 10
S2 S2 , 01
S3 S3 , 10
S* , Q QN
S4 S2 , 01
S5 S3 , 10
S6 S2 , 01
S7 S3 , 10
01
S2 , 01
S3 , 10
S6 , 01
S7 , 10
S2 , 01
S3 , 10
S6 , 01
S7 , 10
11
S0 , 01
S0 , 10
S6 , 01
S7 , 10
S7 , 11
S7 , 10
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
S0 , 01
S7 , 11
S7 , 10
S7 , 11
S7 , 10
CLK D
S 00
S0 S2 , 01
S2 S2 , 01
S3 S3 , 10
S6 S2 , 01
S* , Q QN
S7 S3 , 10
01
S6 , 01
S6 , 01
S7 , 10
S6 , 01
S7 , 10
11
S0 , 01
–– , –
–– , –
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
–– , –
S7 , 10
State Tables and Flow Tables
• Assume internal state S0/10.• Change D to 1, then 0.• Change clock to 0.• Change D to 1, then 0.• What happens when clock changes
to 1.
CLK D
S 00
S0 S2 , 01
S2 S2 , 01
S3 S3 , 10
S6 S2 , 01
S* , Q QN
S7 S3 , 10
01
S6 , 01
S6 , 01
S7 , 10
S6 , 01
S7 , 10
11
S0 , 01
–– , –
–– , –
S7 , 11
S7 , 10
10
S0 , 01
S0 , 10
S0 , 01
–– , –
S7 , 10
SSI Latches andFlip-Flops
• PLDs and FPGAs have to a large extent eliminated their use.
74x37574x74
3
2
7
12
1
4
9
15
1,2C
1D
2D
3,4C
3D
4D
1Q
1Q5
5
4
1
3
2
6
62Q
11
103Q
13
144Q
2Q
3Q
4Q
D Q
QCLK
CLR
PR
74x74
9
10
13
11
12
8
D Q
QCLK
CLR
PR
74x109
10
11
15
12
14
9
J
13K
Q
Q
CLK
CLR
PR
74x112
9
10
14
13
11
7
J
12K
Q
Q
CLK
CLR
PR
74x109
6
5
1
4
2
7
J
3K
Q
Q
CLK
CLR
PR
74x112
5
4
15
1
3
6
J
2K
Q
Q
CLK
CLR
PR
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Debouncer• Bouncing – Behavior of mechanical
of switches which causes their contacts to close, and open several times before finally reaching a resting or stable closed state.
• Typically switches bounce for 10 –20 ms, which is a very long time compared to the switching speeds of logic gates.
push
+5V
SW_L DSW
(a)
1
0
+5V
GND
pushfirst contact bounce
(b)
SW_L
DSW
74LS04
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Debouncer• Debouncing – providing a single
signal change or pulse for each switch transition.
(a)
SW_L
SW_L
SW
SW DSWpush
push
first contactbounce(b)
GNDVOL
VOH
GNDVOL
VOH
SW
SW_L
DSW1
0
74LS04 74LS04
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
SWD_L
DSW_L
DSW
SWU_L
push
+5 V
+5 V
74LS00
R
R
Registers• Collection of two or more D flip-
flops with a common clock input.• Often used to store a collection of
related bits, such as a byte of data.• May also be used to store unrelated
bits of data.
74x175
CLR
CLK
1D1Q
9
2
1Q3
1
4
2D5
3D12
4D13
2Q7
6
3Q10
11
4Q
2Q
3Q
4Q
15
14
(b)
(a)
D Q
QCLK
CLR
(2)
(3)
(4)1Q
1Q_L
1D
D Q
QCLK
CLR
(7)
(6)
(5)2Q
2Q_L
2D
D Q
QCLK
CLR
(10)
(11)
(12)3Q
3Q_L
3D
D Q
QCLK
CLR
(15)
(14)
(13)
(9)
(1)
4Q
4Q_L
4D
CLK
CLR_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Registers
74x374
OE
CLK
1D 1Q
11
1
2
2Q5
3
2D4
3D7
4D8
5D13
6D14
3Q6
9
5Q12
15
4Q
6Q
7D17 16
7Q
8D18 19
8Q
(b)
(a)
(2)
(3)
1Q
1D
2D
(1)
(11)
OE_L
CLK
D
QCLK
(5)
(4)
2Q
D
QCLK
3D(6)
(7)
3Q
D
QCLK
4D(9)
(8)
4Q
D
QCLK
5D(12)
(13)
5Q
D
QCLK
6D(15)
(14)
6Q
D
QCLK
7D(16)
(17)
7Q
D
QCLK
8D(19)
(18)
8Q
D
QCLK
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Registers74x273
CLR
1D 1Q
11
1
2
2Q5
3
2D4
3D7
4D8
5D13
6D14
3Q6
9
5Q12
15
4Q
6Q
7D17 16
7Q
8D18 19
8Q
CLK
74x373
OE
C
1D 1Q
11
1
2
2Q5
3
2D4
3D7
4D8
5D13
6D14
3Q6
9
5Q12
15
4Q
6Q
7D17 16
7Q
8D18 19
8Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Q
CLK
EN_L
CK
D
8D
8Q
(18)
(19)
(1)
(11)
74x377
EN
CLK
1D 1Q
11
1
2
2Q5
3
2D4
3D7
4D8
5D13
6D14
3Q6
9
5Q12
15
4Q
6Q
7D17 16
7Q
8D18 19
8Q
(a) (b)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
PLDI2
I3
I1
I4
P1 P2 P3 P4
O2
O3
O1
P5 P6
Cop
yrig
ht ©
200
0 by
Pre
ntic
e H
all,
Inc.
Dig
ital D
esig
n P
rinci
ples
and
Pra
ctic
es, 3
/e
I2
I3
I1
I4
P1 P2 P3 P4 P5 P6
O3
O2
O1
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
PLD
O1
O2
O3
P1′ P2′ P3′ P4′ P5′ P6′
I1
I2
I3
VCC
VCC
I4
I1I1′I2I2′I3I3′I4I4′
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
VCC
floating gate
nonfloating gate
active-lowinput lines
active-high AND lines
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
PLD(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9) (11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
IO1
O2
O3
O4
O5
O6
O7
IO8
OE_L
CLK
I1
I2
I3
I4
I5
I6
I7
I8
01234567
89
101112131415
1617181920212223
2425262728293031
3233343536373839
4041424344454647
4849505152535455
5657585960616263
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
PLD(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(11)
(15)
(17)O3
O5
OE_L
CLK
I1
I2
I3
I4
I5
I6
I7
I8
01234567
89
101112131415
1617181920212223
2425262728293031
3233343536373839
4041424344454647
4849505152535455
5657585960616263
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
(19)D Q
Q
O1
(18)O2
(16)O4
(14)O6
(13)O7
(12)O8
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
PLD
D Q
Q
CLKOE CLKOE
Registeredoutput logic macrocell
Combinationaloutput logic macrocell
(a) (b)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e