Lecture 6
Digital Electronics 2
Process statement, behavior based modeling, sequentialdesign, conditional and select signal assignment onsequential design
BTF4220 - Digital Electronics 2Apr. 10, 2015
Andreas HabeggerBern University of Applied Sciences
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.2
Agenda
Standard Models
The process Statement
The conditional assignment
Summary
Homework
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.3
An overview
We started with the data-flow model
We learned how to reuse functional units by using the structural model
It is high time to see an other approach, the behavioral based modeling
What is the difference between the three concepts
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.3
An overview
We started with the data-flow model
We learned how to reuse functional units by using the structural model
It is high time to see an other approach, the behavioral based modeling
What is the difference between the three concepts
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.3
An overview
We started with the data-flow model
We learned how to reuse functional units by using the structural model
It is high time to see an other approach, the behavioral based modeling
What is the difference between the three concepts
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.3
An overview
We started with the data-flow model
We learned how to reuse functional units by using the structural model
It is high time to see an other approach, the behavioral based modeling
What is the difference between the three concepts
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.3
An overview
We started with the data-flow model
We learned how to reuse functional units by using the structural model
It is high time to see an other approach, the behavioral based modeling
What is the difference between the three concepts
The structural modeling method is more an approach of combine an existingset of VHDL models rather than a basic design concept. I like to name it adesign method because components, if-generate, for-generate etc. structuresare typical structural VHDL constructs. We discussed those constructs duringan earlier session.
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.4
The fourth concurrent assignment construct
The fourth concurrent signal assignment method is based on the processstatement
The process statement itself is the key construct for the behavior baseddesign method
What is the behavior based design method?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.4
The fourth concurrent assignment construct
The fourth concurrent signal assignment method is based on the processstatement
The process statement itself is the key construct for the behavior baseddesign method
What is the behavior based design method?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.4
The fourth concurrent assignment construct
The fourth concurrent signal assignment method is based on the processstatement
The process statement itself is the key construct for the behavior baseddesign method
What is the behavior based design method?
In contrast to the data-flow method we do not describe how data flows acrossgates. It is more like an algorithmic description of our circuit. We describe howthe output behaves depending on the input. Hence this method is a higherabstraction of hardware description and gives the synthesizer more freedom.Keep all time in mind we are describing hardware! As a golden rule keep theprocess simple and readable and it will work efficiently and reliably.
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.5
The Process Statement
We use the process among other places mainly in the architecture
Three main sections sensitivity list, declaration area and descriptionarea
The label is optional but used it for every process to increase readability
The declarative area is special. There you declare process internalsubtypes, variables, functions etc. signal declaration is not allowed. Usesignals as inter-process communication elements
Example : Process Statement
1 <myProcess>: process (<sensitivity list>) is23 -- declarations45 begin -- process [myProcess]67 -- sequential signal assignments89 end process <myProcess>;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.5
The Process StatementWe use the process among other places mainly in the architectureThree main sections sensitivity list, declaration area and descriptionareaThe label is optional but used it for every process to increase readabilityThe declarative area is special. There you declare process internalsubtypes, variables, functions etc. signal declaration is not allowed. Usesignals as inter-process communication elements
Example : Process Statement
1 <myProcess>: process (<sensitivity list>) is23 -- declarations45 begin -- process [myProcess]67 -- sequential signal assignments89 end process <myProcess>;
In a process the signal assignments are evaluated sequentially. At the end of aprocess-run the signals are going to be updated. As a consequence the newassigned SIGNAL value(s) at S = x will be available at S = x + 1. Are-evaluation of new value to signal assignments is done on every change of asensitivity list signal.
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.6
Data-Flow vs. Behavioral
Let’s compare two methods (data-flow vs behavioral) of describing thefollowing relation : F = A and B
What is the difference between the two descriptions?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.6
Data-Flow vs. Behavioral
Let’s compare two methods (data-flow vs behavioral) of describing thefollowing relation : F = A and B
What is the difference between the two descriptions?
Example : data-flow AND
1 entity exAnd is2 port (3 A, B : in std_logic;4 F : out std_logic);5 end entity exAnd;6 architecture dataflow of exAnd is7 begin -- architecture dataflow89 F <= A and B;
10 --11 --12 end architecture dataflow;
Example : behavioral AND
1 entity exAnd is2 port (3 A, B : in std_logic;4 F : out std_logic);5 end entity exAnd;6 architecture behavioral of exAnd is7 begin -- architecture behv8 and_proc: process(A,B) is9 begin -- process
10 F <= A and B;11 end process and_proc;12 end architecture behavioral;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.6
Data-Flow vs. Behavioral
Let’s compare two methods (data-flow vs behavioral) of describing thefollowing relation : F = A and B
What is the difference between the two descriptions?
Example : data-flow AND
1 entity exAnd is2 port (3 A, B : in std_logic;4 F : out std_logic);5 end entity exAnd;6 architecture dataflow of exAnd is7 begin -- architecture dataflow89 F <= A and B;
10 --11 --12 end architecture dataflow;
Example : behavioral AND
1 entity exAnd is2 port (3 A, B : in std_logic;4 F : out std_logic);5 end entity exAnd;6 architecture behavioral of exAnd is7 begin -- architecture behv8 and_proc: process(A,B) is9 begin -- process
10 F <= A and B;11 end process and_proc;12 end architecture behavioral;
The statement appearing in the data-flow model is re-evaluated any time thereis a change in signal A or in the signal B. Whereas the re-evaluation isproceeded on changes of sensitivity list signals in the behavioral architecture.This is a functional difference rather than a cosmetic difference.
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignment
Remember the concurrent, conditional signal assignment statement
In the process statement there is a similar method for conditional signalassignments
The construct used is called if statement
Only allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descried
It provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignment
Remember the concurrent, conditional signal assignment statement
In the process statement there is a similar method for conditional signalassignments
The construct used is called if statement
Only allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descried
It provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statement
In the process statement there is a similar method for conditional signalassignments
The construct used is called if statement
Only allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descried
It provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statement
In the process statement there is a similar method for conditional signalassignments
The construct used is called if statement
Only allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descried
It provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statementIn the process statement there is a similar method for conditional signalassignmentsThe construct used is called if statementOnly allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descriedIt provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignmentEvery if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 D <= ’0’;6 elsif ((not A) and (not B)) then7 C <= ’1’;8 -- an assigment is missing9 -- latch inferred waring
10 else11 C <= ’0’;12 D <= ’1’;13 end if;14 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statementIn the process statement there is a similar method for conditional signalassignmentsThe construct used is called if statementOnly allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descriedIt provides multiple conditional signal assignmentsThis is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 D <= ’0’;6 elsif ((not A) and (not B)) then7 C <= ’1’;8 -- an assigment is missing9 -- latch inferred waring
10 else11 C <= ’0’;12 D <= ’1’;13 end if;14 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statementIn the process statement there is a similar method for conditional signalassignmentsThe construct used is called if statementOnly allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descriedIt provides multiple conditional signal assignmentsThis is a mayor difference to the concurrent version of conditional signalassignmentEvery if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 D <= ’0’;6 elsif ((not A) and (not B)) then7 C <= ’1’;8 -- an assigment is missing9 -- latch inferred waring
10 else11 C <= ’0’;12 D <= ’1’;13 end if;14 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.7
The conditional signal assignmentRemember the concurrent, conditional signal assignment statement
In the process statement there is a similar method for conditional signalassignments
The construct used is called if statement
Only allowed in the process statement and not outside in the architecturewhere concurrent signal assignments are descried
It provides multiple conditional signal assignments
This is a mayor difference to the concurrent version of conditional signalassignment
Every if-statement has a catch-all the else part of the construct
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 if (A and B) then4 C <= ’1’;5 elsif ((not A) and (not B)) then6 C <= ’1’;7 else8 C <= ’0’;9 end if;
1011 end process if_ex;
Example : if statement
1 if_ex: process (A,B) is2 begin -- process if_ex3 C <= ’0’;4 D <= ’1’;5 if (A and B) then6 C <= ’1’;7 D <= ’0’;8 elsif ((not A) and (not B)) then9 C <= ’1’;
10 end if;11 end process if_ex;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.8
Let’s do an example
Let’s realize the function
F (A,B,C) := ABC + BC
Write the entity, behavioral based architecture and use the if-syntax todescribe this circuit
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.8
Let’s do an example
Let’s realize the function
F (A,B,C) := ABC + BC
Write the entity, behavioral based architecture and use the if-syntax todescribe this circuit
Solution : F (A,B,C) := ABC + BC
1 library IEEE;2 use IEEE.std_logic_1164.all;34 entity IfEx is5 port(6 A, B, C : in std_logic;7 F_OUT : out std_logic);8 end entity IfEx;9
10 architecture behavioral of IfEx is11 begin12 proc1 : process(A, B, C) is13 begin14 if (A = ’1’ and B = ’0’ and C = ’0’) then15 F_OUT <= ’1’;16 elsif (B = ’1’ and C = ’1’) then17 F_OUT <= ’1’;18 else19 F_OUT <= ’0’;20 end if;21 end process proc1;22 end architecture behavioral;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.9
Lets describe a Mux
Describe a mux with 8 data input lines and one data output line, hence a8 to 1 multiplexer
How does the description look like?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.9
Lets describe a Mux
Describe a mux with 8 data input lines and one data output line, hence a8 to 1 multiplexer
How does the description look like?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.9
Lets describe a Mux
Describe a mux with 8 data input lines and one data output line, hence a8 to 1 multiplexer
How does the description look like?
Example : 8 to 1 Mux
1 -- library declaration2 library IEEE;3 use IEEE.std_logic_1164.all;4 -- entity5 entity Mux8to1 is6 port(7 DataxDI : in std_logic_vector (7 downto 0);8 SelxDI : in std_logic_vector (2 downto 0);9 DataxDO : out std_logic);
10 end entity Mux8to1;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.9
Lets describe a MuxDescribe a mux with 8 data input lines and one data output line, hence a8 to 1 multiplexerHow does the description look like?
Example : 8 to 1 Mux
1 -- library declaration2 library IEEE;3 use IEEE.std_logic_1164.all;4 -- entity5 entity Mux8to1 is6 port(7 DataxDI : in std_logic_vector (7 downto 0);8 SelxDI : in std_logic_vector (2 downto 0);9 DataxDO : out std_logic);
10 end entity Mux8to1;11 -- architecture12 architecture behv of Mux8to1 is13 begin14 mux_proc : process (DataxDI, SelxDI)15 begin16 if (SelxDI = "111") then DataxDO <= DataxDI(7);17 elsif (SelxDI = "110") then DataxDO <= DataxDI(6);18 elsif (SelxDI = "101") then DataxDO <= DataxDI(5);19 elsif (SelxDI = "100") then DataxDO <= DataxDI(4);20 elsif (SelxDI = "011") then DataxDO <= DataxDI(3);21 elsif (SelxDI = "010") then DataxDO <= DataxDI(2);22 elsif (SelxDI = "001") then DataxDO <= DataxDI(1);23 elsif (SelxDI = "000") then DataxDO <= DataxDI(0);24 else DataxDO <= ’0’;25 end if;26 end process my_mux;27 end mux_8t1_arc;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.10
An other method to describe a 8to1 multiplexer
Is there an other and more intuitive method as the if-statement?
It were nice to have something like a select statement
There is a other sequential statement the case-statement
An example of the case-statement is given below
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.10
An other method to describe a 8to1 multiplexer
Is there an other and more intuitive method as the if-statement?
It were nice to have something like a select statement
There is a other sequential statement the case-statement
An example of the case-statement is given below
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.10
An other method to describe a 8to1 multiplexer
Is there an other and more intuitive method as the if-statement?
It were nice to have something like a select statement
There is a other sequential statement the case-statement
An example of the case-statement is given below
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.10
An other method to describe a 8to1 multiplexer
Is there an other and more intuitive method as the if-statement?
It were nice to have something like a select statement
There is a other sequential statement the case-statement
An example of the case-statement is given below
Example : case syntax
1 case (expression) is2 when choices =>3 <sequential statements>4 when choices =>5 <sequential statements>6 when others =>7 <sequential statements>8 end case;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.10
An other method to describe a 8to1 multiplexer
Is there an other and more intuitive method as the if-statement?
It were nice to have something like a select statement
There is a other sequential statement the case-statement
An example of the case-statement is given below
Example : case syntax
1 case (expression) is2 when choices =>3 <sequential statements>4 when choices =>5 <sequential statements>6 when others =>7 <sequential statements>8 end case;
Let’s realize the function
F (A,B,C) := ABC + BC
Write the entity, behavioral based architecture by using the casestatement.
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.11
A case-statement example
F (A,B,C) := ABC + BC
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.11
A case-statement example
F (A,B,C) := ABC + BC
Solution : with don’t care
1 -- library declaration2 library IEEE;3 use IEEE.std_logic_1164.all;4 -- entity5 entity CaseEx is6 port(7 A, B, C : in std_logic;8 F : out std_logic);9 end entity CaseEx;
10 -- architecture11 architecture withDontCare of CaseEx is12 signal ABC : std_logic_vector(2 downto 0);13 begin14 -- group signals for case statement15 ABC <= A & B & C;16 Cproc: process (ABC)17 begin18 case (ABC) is19 when "100" => F <= ’1’;20 when "-11" => F <= ’1’;21 when others => F <= ’0’;22 end case;23 end process Cproc;2425 end architecture withDontCare;
Solution : without don’t care
1 -- library declaration2 library IEEE;3 use IEEE.std_logic_1164.all;4 -- entity5 entity CaseEx is6 port(7 A, B, C : in std_logic;8 F : out std_logic);9 end entity CaseEx;
10 -- architecture11 architecture noDontCare of CaseEx is12 signal ABC : std_logic_vector(2 downto 0);13 begin14 -- group signals for case statement15 ABC <= A & B & C;16 Cproc: process (ABC)17 begin18 case (ABC) is19 when "100" => F <= ’1’;20 when "011" => F <= ’1’;21 when "111" => F <= ’1’;22 when others => F <= ’0’;23 end case;24 end process Cproc;25 end architecture noDontCare;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.11
A case-statement example
F (A,B,C) := ABC + BC
The don’t care feature is nice but causes problems
Some synthesizer and simulation tool-chains are not handling it properly
Avoid using the don’t care feature hence re-write
F (A,B,C) := ABC + BC
F (A,B,C) := ABC + BC(A + A)
F (A,B,C) := ABC + ABC + ABC
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.12
Re-write the 8to1 Mux
Write the VHDL code to realize the 8 to 1 mux by using the case-statement.Extend the example with a CE signal. The CE has the following impact: WhenCE = 1, the output acts like the MUX we saw earlier. When CE = 0 the outputremains 0.
What feature provides the “CE” signal?
How can you implement the “CE” feature?
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.12
Re-write the 8to1 Mux
Solution : 8 to 1 Mux with CE
1 -- library declaration2 library IEEE;3 use IEEE.std_logic_1164.all;4 -- entity5 entity Mux8to1_ce is6 port (7 DataxDI : in std_logic_vector (7 downto 0);8 SelxDI : in std_logic_vector (2 downto 0);9 CexSI : in std_logic;
10 DataxDO : out std_logic);11 end entity Mux8to1_ce;12 -- architecture13 architecture anExample of Mux8to1_ce is14 begin15 theMux : process (DataxDI, SelxDI, CexSI)16 begin17 if (CexSI = ’1’) then18 case (SelxDI) is19 when "000" => DataxDO <= DataxDI(0);20 when "001" => DataxDO <= DataxDI(1);21 when "010" => DataxDO <= DataxDI(2);22 when "011" => DataxDO <= DataxDI(3);23 when "100" => DataxDO <= DataxDI(4);24 when "101" => DataxDO <= DataxDI(5);25 when "110" => DataxDO <= DataxDI(6);26 when "111" => DataxDO <= DataxDI(7);27 when others => DataxDO <= ’0’;28 end case;29 else30 DataxDI <= ’0’;31 end if;32 end process theMux;33 end architecture anExample;
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.12
Re-write the 8to1 Mux
Write the VHDL code to realize the 8 to 1 mux by using the case-statement.Extend the example with a CE signal. The CE has the following impact: WhenCE = 1, the output acts like the MUX we saw earlier. When CE = 0 the outputremains 0.
What feature provides the “CE” signal?
How can you implement the “CE” feature?
A great benefit of the behavioral design method is the nesting capability
To describe what we want, we nested a case-statement in a if-statement
Not only nesting is an advantage also multiple assignments per condition
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.13
Summary
The three main flavors of VHDL modeling styles include data-flow,structural and behavioral models
VHDL behavioral models, by definition, use process statements
The data-flow models by definition use concurrent signal assignment,conditional signal assignment and/or selected signal assignment
process statement is a concurrent statement. Statements appearingwithin the process statement are sequential statements
The if statement has a direct analogy to the conditional signalassignment statement used in data-flow modeling
The case statement has a direct analogy to the selected signalassignment statement used in data-flow modeling
Both the case statement and the if statement can be nested.Concurrent, conditional and selected signal assignment statementscannot be nested.
The signals in the sensitivity list trigger the re-evaluation of the sequentialsignal assignment
Digital Electronics 2
Andreas Habegger
Standard Models
The processStatement
The conditionalassignment
Summary
Homework
Rev. ab24f70 – 6.14
Homework
Read chapter 5 in the companion book (“Free Range VHDL”)
Finish the exercise of last session (second in the exercise booklet)
Write the VHDL model of a binary to 7-segment decoder to display hexnumbers
Prepare a 4 Bit adder as well as a subtractor for the laboratory sessionnext week