Analysis of HighAnalysis of High--speed Differential Line on PCB using HFSSspeed Differential Line on PCB using HFSS
2002. 10. 1
Terahertz Interconnection and Package LaboratoryKAIST (Korea Advanced Institute of Science and Technology)
Seungyong Baek (? ? ? )
Homepage : http://tera.kaist.ac.kr
2/31
Research Fields at TERA Lab. (in the view of Motherboard)Research Fields at TERA Lab. (in the view of Motherboard)
Spread Spectrum Clock Driver
EMI
Meander LINE
RAMBUSWLP
Single Line ModelingCrosstalk ModelingVia Modeling
Connector Modeling
SMT Component ModelingTwisted Pair on PCB/ChipModular Jack
Signal line across Split plane design
Memory Module Design
BGA ModelingAdaptive Output Driver
ESD
SATADifferential Line Modeling
Embedded Passive Modeling
Power Plane DesignMixed Mode Power Plane ModelingSplit Power System Modeling
MESH Plane Modeling
3/31
ContentsContents
u Introduction of Differential Signaling Scheme
u Characterization of Differential Signaling Scheme by Fabrication Error
u Impedance Change by Edge-Placement of High-speed Differential Lines
u An Evaluation of Differential Impedance in PCBs Using Two Single-
Ended Probes Only
u Conclusion
4/31
Introduction Introduction –– Frequency IncreaseFrequency Increase
2000 2002 2004 2006 2008 2010 2012 20140
1
2
3
4
5
6
7
Year
Freq
uenc
y [G
Hz]
On-chip Local Clock(High-performance)
Chip-to-Board(off-chip) Speed (high-performance, for peripheral buses)
Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA
u Off-chip data rate should move to the range of Gb/s-per-pin
? increased complexity and cost due to massive parallelism
5/31
Introduction Introduction –– Power Supply Voltage DecreasePower Supply Voltage Decrease
2.1
2000 2002 2004 2006 2008 2010 2012 20140
0.3
0.6
0.9
1.2
1.5
1.8
Year
Pow
er S
uppl
y V
olta
ge [V
]
Minimum logic Vdd(V)for maximum performance
Minimum logic Vdd(V)for minimum power
Ref.) ITRS (International Technology Roadmap for Semiconductors), 2000, SIA
u Reduction of power supply voltage
? power dissipation, transistor channel length, reliability of gate dielectric
6/31
Why Differential Signaling?Why Differential Signaling?
u Reduction of Crosstalk between Circuits
u Reduction of Simultaneous Switching Noise (SSN)
u Reduction of EMI
u Minimization of Common-mode noise
u Design of Low-voltage, Low-power
⇒ High-speed digital circuit
7/31
ObjectiveObjective
u Using HFSS simulation and Testing,
§ A Characterization of Differential Signaling Scheme by Fabrication Error
§ A Demonstration of Impedance Change by Edge-Placement of High-speed
Differential Lines
§ An Evaluation of New Test Method of Differential Lines Using Two Single-
Ended Probes Only
8/31
Process Variation Problem in Differential Line SchemeProcess Variation Problem in Differential Line Scheme
Common-ModeDifferential-Mode
q Variation of fabrication error : (? w, ? s) > (? h)
q Variation of fabrication error ? field change ? variation of electrical characteristics
q Variation of electrical characteristics by fabrication error
Differential-mode > Common-mode
? w? s
? h
Seungyoung Ahn, Albert Chee W. Lu, Wei fan, lai L Wai, and Joungho Kim, “Solution Space Analysis of Interconnects for Low Voltage Differential Signaling ( LVDS) Applications”, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP2001), pp. 297-330, Boston, USA, Oct. 2001.
9/31
Device Under TestDevice Under Test
DUT Width Width ? ?
#1
Space
100 µm –20 %125 µm
–10 %
0 %
10 %
20 %
125 µm
125 µm
125 µm
125 µm
112.5 µm
125 µm
137.5 µm
150 µm
#2
#3
#4
#5
DUT Width Space ? ?
#6
Space
100 µm –20 %125 µm
–10 %
0 %
10 %
20 %
125 µm
125 µm
125 µm
125 µm
112.5 µm
125 µm
137.5 µm
150 µm
#7
#8
#9
#10
? ? ?
u ? ? ? ? 10%? ? ? ? ? ? ? ? ? .
u ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? Signal line? Width? Space? ±10%, ±20% ? ? .
10/31
Characteristic Parameters Characteristic Parameters –– 1.Characteristic Impedance (Z1.Characteristic Impedance (Z00))
±20% of Width variation for Differential-mode signaling
u ZDifferential-mode (100 Ohm) ˜ ZCable (50×2 = 100 Ohm) ? ? Matching.
uWidth? (20%) ð Reflection ? ? (4.9 %)
? ? ? , Z0? (10.3 %)
u 4.9% reflection ð 10.9% Z0 ? ? (full-wave Simulation),
100 125 15080
100
120
140
10.9 %
Z0
(Ohm
)
Width (µm)
4.9 % reflection
Time (ns)
Vol
tage
(V)
Γ−Γ+
×−Γ−
Γ+×=−=∆
11
1001
1100
ref
refref ZZZ
Circuit Simulation (? ? TDR Setup) Full-wave simulation
11/31
Characteristic Parameters Characteristic Parameters –– 1.Characteristic Impedance (Z1.Characteristic Impedance (Z00))
u ZCommon-mode (33Ohm) > ZCable (50/2=25Ohm)? ? ? ? Mismatching
uWidth? (20%) ð Reflection ? ? (4.8 %)
u 4.8% reflection ð 10.9 % Z0 ? ? (full-wave Simulation)
±20% of Width variation for Common-mode signaling
Time (ns)
Vol
tage
(V) 4.8 % reflection
100 125 15010
30
50
70
10.9 %
Width (µm)
Z0
(Ohm
)
Circuit Simulation (? ? TDR Setup) Full-wave simulation
12/31
Characteristic Parameters Characteristic Parameters –– 1.Characteristic Impedance (Z1.Characteristic Impedance (Z00))
±20% of Space variation for Differential-mode signaling
1.8 % reflection
Time (ns)
Vol
tage
(V)
100 125 15080
100
120
140
3.2 %
Space (µm)
Z0
(Ohm
)u ZDifferential-mode (100 Ohm) ˜ ZCable (50×2 = 100 Ohm) ? ? Matching.
u Space? (20%) ð Reflection ? ? (1.8 %)
u 1.8% reflection ð 3.2% Z0 ? ? (full-wave Simulation)
Circuit Simulation (? ? TDR Setup) Full-wave simulation
13/31
Characteristic Parameters Characteristic Parameters –– 1.Characteristic Impedance (Z1.Characteristic Impedance (Z00))
Time (ns)
Vol
tage
(V) 1.1 % reflection
±20% of Space variation for Common-mode Signaling
100 125 150
2.6 %
10
30
50
70
Space (µm)
Z0
(Ohm
)u ZCommon-mode (33 Ohm) > ZCable (50/2=25 Ohm) ? ? ? ? Mismatching
u Space? (20%) ð Reflection ? ? (1.1 %)
u 1.1% reflection ð 2.6% Z0 ? ? (full-wave Simulation)
Circuit Simulation (? ? TDR Setup) Full-wave simulation
14/31
Effect by Edge Placement of Differential LineEffect by Edge Placement of Differential Line
Distance to edge (D)
Line Width = 0.4mm
Pitch=0.7mmSubstrate Width=20mm
Height = 0.3mm
Substrate length=80mm
Test PCB with finite width ground
0.8mm
10mm
? Consider the effects by edge placement of high-speed differential lines
? Demonstrate differential mode impedance change by edge placement
? Certificate variation of radiated emission using simulation and measurement
Seungyong Baek, Derek Kam, Bongcheol Park, Jung-Gun Byun, Cheol-Seung Choi, and Joungho Kim, “Increased Radiated Emission and Impedance Change by Edge-Placement of High-speed Differential Lines on Printed Circuit Board,” 2002 IEEE International Symposium on Electromagnetic Compatibility, vol 1, pp 200-204, Minnesota USA.
15/31
Current density of differential pair (Simulation)Current density of differential pair (Simulation)
(a) (b)
Trace 1 Trace 2 Trace 1 Trace 2
Substrate
Air
Substrate
Air
Current density when the distance to edge is 10mm Current density when the distance to edge is 1mm
10mm 1mm
u When differential pair is located in the center of PCB, current density is balanced in case of (a)
u The balance of current density is broken by edge placement in case of (b)
16/31
Differential impedance change by edge placement (Simulation)Differential impedance change by edge placement (Simulation)
10 9 8 7 6 5 4 3 2 1 020
30
40
50
60
70
80
90
100
110
Distance to edge (D) [mm]
Impe
danc
e [o
hm]
1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.625
30
35
40
45
50
55
60
65
Differential mode impedance
Common mode impedance
u Differential mode impedance remains about 100Ω from 10mm to 2mm
u Differential mode impedance suddenly falls off when D is 1mm
17/31
Measurement setup of differential impedanceMeasurement setup of differential impedance
Differential TDR module 80E04 + Sampling Oscilloscape TDS 8000B( Reflected rising time= 30ps )
Test PCB
50Ω termination
Test setup for measuring the differential mode impedance
18/31
Measurement results Measurement results –– differential mode impedancedifferential mode impedance
44.4 44.6 44.8 45 45.2 45.4 45.6 45.8 46 46.260
70
80
90
100
110
120
Time [ns]
Diff
eren
tial I
mpe
danc
e [o
hm] Distance to the edge (D) = 10mm
Distance to the edge (D) = 0.8mm
Reduction of 17%
u Distance to the edge = 10mm à Differential mode impedance = 102Ω
u Distance to the edge = 0.8mm à Differential mode impedance = 85Ω
u The differential mode impedance suddenly falls off to 85Ω when D = 0.8mm
19/31
Variation of radiated emission by edge placementVariation of radiated emission by edge placement
Edge placement of high-speed differential lines
Balance of the differential lines is collapsed
Balance of the current density is also broken
Increase of common mode current
Variation of radiated emission
20/31
Radiated emission according to location of differential pairRadiated emission according to location of differential pair
10mm
3mm
1mm
0.8mm
MAX : 0.25V/m
MAX : 0.522V/m
0.2
0.4
0.6
30
210
60
240
90
270
120
300
150
330
180 0
Total electric field plot at 1GHz (V/m)
D=3mm (b)D=1mm (c)D=0.8mm (d)
D=10mm (a)
Simulated total electric field at 1GHz
(a)
(b)
(c)
(d)
21/31
Measurement setup of radiation emissionMeasurement setup of radiation emission
180°Phase Shifter
0°180°100MHz
CrystalOscillator
DC PowerSupply
Shielding Box
Anechoic Chamber
Antenna
Radiated Emission
Test PCB
Test setup for measuring an amount of the radiated emission
Spectrum Analyzer
22/31
Measurement result Measurement result –– maximum radiated emissionmaximum radiated emission
100 200 300 400 500 600 700 800 900 1000-85
-80
-75
-70
-65
-60
-55
Frequency [MHz]
dBm
Maximum Spectrum (Peak-to-Peak envelop)
D=10mmD=7mmD=5mmD=3mm
? The closer differential pair to the PCB edge, the more radiated emission occur
? When the differential pair is placed at the edge of the PCB, the shielding effect
by the ground plane is no longer effective
23/31
u Only a small skew of TDR pulses can result in considerable error.
B. J. Rubin, “Understanding Modeling and Measurements of Differential Transmission Lines”,Proc. IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging, 2001, pp. 313-316
Conventional Method 1: Differential TDRConventional Method 1: Differential TDR
u Its instrumentation is expensive because of such difficulties assynchronizing two TDR pulses.
S. Corey, et al., “Electronic Package Characterization Using Differential TDR Techniques”,Proc. IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, 2000, pp. 172-174.
Dong Gun Kam, Heeseok Lee, Woonghwan Ryu, Jonghoon Kim, Bongcheol Park, and Joungho Kim, "An Evaluation of Differential Impedance in PCBs Using Two Single-Ended Probes Only," IEEE Workshop on Signal Propagation on Interconnects (SPI), 2002
24/31
2-port VNA
DUTBalun Balun
Conventional Method 2: BalunConventional Method 2: Balun
u Balun = Power Splitter + Phase Shifter
u It is very difficult to make broadband baluns.
25/31
Conventional Method 3: MixedConventional Method 3: Mixed--Mode SMode S--parametersparameters
D. E. Bockelman, “Combined Differential and Common-Mode Scattering Parameters: Theory andSimulation”, IEEE Trans-MTT, Vol. 43, No. 7 (1995), pp. 1530-1539
u Although it is theoretically perfect, it is very expensive.
26/31
WhatWhat’’s the Matters with the Conventional Methodss the Matters with the Conventional Methods
4-port Measurement
Expensive
BalunOnly narrow-band
Need forde-embedding balun effect
Differential TDRAccurate synchronization of two TDR pulses is required
Expensive
27/31
Proposed MethodProposed Method
u Two single-ended probes are connected to each signal traceswith a metallic plane on the bottom layer floating.
28/31
1mm4mm1mm#3
1mm3mm2mm#2
1mm2mm3mm#1
H(dielectric)
S(space)
W(width)DUT
Measured ResultsMeasured Results
132O (+2.3%)129O126O (-2.3%)#3
91.1O (+2.8%)88.6O86.7O (-2.1%)#2
68.9O (+1.1%)67.8O67.1O (-1.0%)#1
Simulation(MoM)
4-portMeasurement
ProposedMethodDUT
u Device-Under-Test (DUT) : Coupled Microstrip Line
u Measured Differential Impedance at 500MHz
29/31
Full Wave Simulation (Using Ansoft HFSS)Full Wave Simulation (Using Ansoft HFSS)
129 O126.8O (-1.7%)126.5O (-1.9%)126.8O (-1.7%)#3
88.6O91.0O (+2.7%)91.3O (+3.0%)91.4O (+3.2%)#2
67.8O73.2O (+8.0%)72.3O (+6.6%)72.9O (+7.5%)#1
Ref.5 GHz2 GHz500 MHzDUT
30/31
The PROS and CONS of the Proposed MethodThe PROS and CONS of the Proposed Method
Advantage
Disadvantage
Differential only
Simple
Cheap
Non-invasive
Practical !!!
31/31
ConclusionConclusion
? We have been researching Signal Integrity, Power/Ground Integrity
and EMI in Tera Lab.
? We introduced Differential Signaling Scheme
§ Variation of differential line characteristics by fabrication error
§ Change of differential impedance by edge placement
§ Proposal of new test method of differential lines