Designing a Single Cycle Datapath
In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte are used
with permission.
The Big Picture: Where are We Now?
° The Five Classic Components of a Computer
° Today’s Topic: Design a Single Cycle Processor
Control
Datapath
Memory
ProcessorInput
Output
The Big Picture: The Performance Perspective
° Performance of a machine is determined by:
• Instruction count
• Clock cycle time
• Clock cycles per instruction
° Processor design (datapath and control) will determine:
• Clock cycle time
• Clock cycles per instruction
° Single cycle processor - one clock cycle per instruction
• Advantages: Simple design, low CPI
• Disadvantages: Long cycle time, which is limited by the slowest instruction.
CPI
Inst. Count Cycle Time
How to Design a Processor: step-by-step
1. Analyze instruction set => datapath requirements• the meaning of each instruction is given by register
transfers
R[rd] <– R[rs] + R[rt];• datapath must include storage element for ISA
registers• datapath must support each register transfer
2. Select set of datapath components and establish clocking methodology
3. Design datapath to meet the requirements
4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
5. Design the control logic
MIPS Instruction set
MIPS operands
Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero alw ays equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants.
Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so
232 memory Memory[4], ..., sequential w ords dif fer by 4. Memory holds data structures, such as arrays,
words Memory[4294967292] and spilled registers, such as those saved on procedure calls.
MIPS assembly language
Category Instruction Example Meaning Commentsadd add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers
Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers
add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register
store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register
store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory
load upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits
branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100
Equal test; PC-relative branch
Conditional
branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100
Not equal test; PC-relative
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0
Compare less than; for beq, bne
set less than immediate
slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0
Compare less than constant
jump j 2500 go to 10000 Jump to target address
Uncondi- jump register jr $ra go to $ra For switch, procedure return
tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
Review: The MIPS Instruction Formats
° All MIPS instructions are 32 bits long. The three instruction formats are:
• R-type
• I-type
• J-type
° The different fields are:• op: operation of the instruction• rs, rt, rd: the source and destination register specifiers• shamt: shift amount• funct: selects the variant of the operation in the “op” field• address / immediate: address offset or immediate value• target address: target address of the jump instruction
op target address
02631
6 bits 26 bits
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
Translating MIPS Assembly into Machine Language
° Humans see instructions as words (assembly language), but the computer sees them as ones and zeros (machine language).
° An assembler translates from assembly language to machine language.
° For example, the MIPS instruction add $t0, $s1, $s2 is translated as follows (see back of book):
Assembly Comment
add op = 0, shamt = 0, funct = 32
$t0 rd = 8
$s1 rs = 17
$s2 rt = 18
00000 100000
functshamt
01000
rd
10010
rt
10001
rs
000000
op
MIPS Addressing Modes
° Addressing modes specify where the data used by an instruction is located.
mode example action
register direct add $s1, $s2, $s3 $s1 $s2 + $s3
immediate addi $s1, $s2, 200 $s1 = $s2 + 200
base+index lw $s1, 200($s2) $s1 = mem[200 + $s2]
PC-relative beq $s1, $s2, 200 if ($s1 == $s2)
PC = PC+4+200*4
Pseudo-direct j 4000 PC = (PC[31:28], 4000*4)
° Often, the type of addressing mode depends on the type of operation being performed (e.g., branches all use PC relative)
° A summary of MIPS addressing modes is given on the back cover of the book.
MIPS Addressing Modes/Instruction Formats
op rs rt rd
immed
register
Register (direct)
op rs rt
register
Base+index
+
Memory
immedop rs rtImmediate
immedop rs rt
PC
PC-relative
+
Memory
• All MIPS instructions are 32 bits wide - fixed lengthadd $s1, $s2, $s3
addi $s1, $s2, 200
lw $s1, 200($s2)
beq $s1, $s2, 200
Step 1a: The MIPS Subset for Today
° ADD and SUB• addu rd, rs, rt• subu rd, rs, rt
° OR Immediate:• ori rt, rs, imm16
° LOAD and STORE• lw rt, rs, imm16• sw rt, rs, imm16
° BRANCH:• beq rs, rt, imm16
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
Register Transfer Logic (RTL)
° RTL gives the meaning of the instructions
° All instructions start by fetching the instructionop | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16 = MEM[ PC ]
inst Register Transfers
addu R[rd] <– R[rs] + R[rt]; PC <– PC + 4
subu R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ori R[rt] <– R[rs] + zero_ext(imm16); PC <– PC + 4
load R[rt] <– MEM[ R[rs] + sign_ext(imm16)]; PC <– PC + 4
store MEM[ R[rs] + sign_ext(imm16) ] <– R[rt]; PC <– PC + 4
beq if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(imm16)] || 00 else PC <– PC + 4
Step 1: Requirements of the Instruction Set
° Memory
• instruction & data
° Registers (32 x 32)
• read rs
• read rt
• write rt or rd
° PC
° Extender (sign extend or zero extend)
° Add and sub register or extended immediate
° Add 4 or shifted extended immediate to PC
° Adder
° MUX
° ALU
32
32
A
B32
Sum
Carry
32
32
A
B32
Result
OP
32A
B32
Y32
Select
Ad
der
MU
XA
LU
CarryIn
3
Step 2: Components of the Datapath
Combinational Logic:Does not use a clock
Storage Element: Register (Basic Building Blocks)
° Register
• Similar to the D Flip Flop except
- N-bit input and output
- Write enable input
• Write Enable:
- negated (0): Data Out will not change
- asserted (1): Data Out will become Data In on the falling edge of the clock
Clk
Data In
Write Enable
N N
Data Out
Clocking Methodology - Negative Edge Triggered
° All storage elements are clocked by the same clock edge
° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew
Clk
Don’t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
Storage Element: Register File
° Register File consists of 32 registers:
• Two 32-bit output busses:
busA and busB
• One 32-bit input bus: busW
° Register is selected by:
• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1
° Clock input (CLK)
• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic block:
- RA or RB valid => busA or busB valid after “access time.”
Clk
busW
Write Enable
3232
busA
32busB
5 5 5RWRARB
32 32-bitRegisters
° Built using D flip-flops
Register File - Read
Read registernumber 1 Read
data 1Read registernumber 2
Readdata 2
Writeregister
WriteWritedata
Register file
Read registernumber 1
Register 0
Register 1
. . .
Register n – 2
Register n – 1
M
u
x
Read registernumber 2
M
u
x
Read data 1
Read data 2
Register File - write
Write
01
n-to-2n
decoder
n – 1
n
Register 0
C
D
Register 1
C
D
Register n – 2
C
D
Register n – 1
C
D
...
Register number...
Register data
Storage Element: Idealized Memory
° Memory (idealized)
• One input bus: Data In
• One output bus: Data Out
° Memory word is selected by:
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memoryword to be written via the Data In bus
° Clock input (CLK)
• The CLK input is a factor ONLY during write operation
• During read operation, memory behaves as a combinational logic block:
- Address valid => Data Out valid after “access time.”
Clk
Data In
Write Enable
32 32DataOut
Address32
Step 3
° Register Transfer Requirements –> Datapath Design• Instruction Fetch
• Decode instructions and Read Operands
• Execute Operation
• Write back the result
3a: Overview of the Instruction Fetch Unit
° The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
- Sequential Code: PC <- PC + 4
- Branch and Jump: PC <- “something else”
32
Instruction WordAddress
InstructionMemory
PCClk
Next AddressLogic
3b: Add & Subtract
° R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt
• Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the instruction
32
Result
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
3
3c: Logical Operations with Immediate
° R[rt] <- R[rs] op ZeroExt[imm16] Example : ori rt, rs, imm16
32
Result
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRdRegDst
ZeroE
xt
Mu
x
Mux
3216imm16
ALUSrc
AL
U
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd?
immediate
016 1531
16 bits16 bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3
3d: Load Operations
° R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRd
RegDst
Exten
der
Mu
x
Mux
3216
imm16
ALUSrc
ExtOp
Clk
Data InWrEn
32
Adr
DataMemory
32
AL
U
MemWr Mu
x
W_Src3
3e: Store Operations
° Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
Rd
RegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrcExtOp
Clk
Data InWrEn
32
Adr
DataMemory
MemWr
AL
U
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
32
Mu
x
W_Src
3
3f: The Branch Instruction
° beq rs, rt, imm16
• mem[PC] Fetch the instruction from memory
• Equal <- R[rs] == R[rt] Calculate the branch condition
• if (COND eq 0) Calculate the next instruction’s address
- PC <- PC + 4 + ( SignExt(imm16) x 4 )
else
- PC <- PC + 4
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
Datapath for Branch Operations
° beq rs, rt, imm16 Datapath generates condition (equal)
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
32
imm16
PC
Clk
00
Ad
der
Mu
x
Ad
der
4nPC_sel
Clk
busW
RegWr
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs Rt
Eq
ual
?
Cond
PC
Ext
Inst Address
Putting it All Together: A Single Cycle Datapath
imm
16
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
Ad
der
Ad
der
PC
Clk
00
Mu
x
4
nPC_sel
PC
Ext
Adr
InstMemory
3
Step 4: Given Datapath: RTL -> Control
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<0:5>
Fun
RegWr
<26:31>
A Single Cycle Datapath
° We have everything except control signals (underlined)• Today’s lecture will look at how to generate the control signals
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrc
ExtOp
Mu
x
MemtoReg
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWrA
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Meaning of the Control Signals
° ExtOp: “zero”, “sign”
° ALUsrc: 0 => regB; 1 => immed
° ALUctr: “add”, “sub”, “or”
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWr
AL
U
Equal
0
1
0
1
01
° MemWr: write memory
° MemtoReg: 0 => ALU; 1 => Mem
° RegDst: 0 => “rt”; 1 => “rd”
° RegWr: write dest register
=
3
RTL: The Add Instruction
° add rd, rs, rt
• mem[PC] Fetch the instruction from memory
• R[rd] <- R[rs] + R[rt] The actual operation
• PC <- PC + 4 Calculate the next instruction’s address
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
The Single Cycle Datapath during Add/Sub
32
ALUctr = Add
Clk
busW
RegWr = 1
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 1
Exten
der
Mu
x
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mu
x
MemtoReg = 0
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>° R[rd] <- R[rs] op R[rt]
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
op rs rt rd shamt funct
061116212631
nPC_sel= +4
Instruction Fetch Unit at the End of Add
° PC <- PC + 4• This is the same for all instructions except Branch and Jump
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00
Mu
x
4
nPC_sel = +4
imm
16Instruction<31:0>
The Single Cycle Datapath during Load
32
ALUctr = Add
Clk
busW
RegWr = 1
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Exten
der
Mu
x
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mu
x
MemtoReg = 1
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
° R[rt] <- Data Memory {R[rs] + SignExt[imm16]}
op rs rt immediate
016212631
nPC_sel= +4
The Single Cycle Datapath during Store
32
ALUctr = Add
Clk
busW
RegWr = 0
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Exten
der
Mu
x
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mu
x
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 1A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
° Data Memory {R[rs] + SignExt[imm16]} <- R[rt]
op rs rt immediate
016212631
nPC_sel= +4
The Single Cycle Datapath during Branch
32
ALUctr = Subtract
Clk
busW
RegWr = 0
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Exten
der
Mu
x
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mu
x
MemtoReg = x
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
° if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0
op rs rt immediate
016212631
nPC_sel= “Br”
Instruction Fetch Unit at the End of Branch
° if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;
else PC = PC + 4
op rs rt immediate
016212631
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00
Mu
x
4
nPC_sel
imm
16Instruction<31:0>
See book for what the datapath and control looks like for jump instructions.
Compared to book our processor also supports the ORI instructions.
A Summary of the Control Signals
add sub ori lw sw beq jump
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
nPCsel
Jump
ExtOp
ALUctr<2:0>
1
0
0
1
0
0
0
x
Add
1
0
0
1
0
0
0
x
Subtract
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
op target address
op rs rt rd shamt funct
061116212631
op rs rt immediate
R-type
I-type
J-type
add, sub
ori, lw, sw, beq
jump
func
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A10 0000See 10 0010 We Don’t Care :-)
Step 5: The Concept of Local Decoding
R-type ori lw sw beq jump
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
Branch
Jump
ExtOp
ALUop<N:0>
1
0
0
1
0
0
0
x
“R-type”
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
MainControl
op
6
ALUControl(Local)
func
N
6ALUop
ALUctr
3
AL
U
The Encoding of ALUop
° In this exercise, ALUop has to be N=2 bits wide to represent:
• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, and (4) Subtract
° To implement the full MIPS ISA, ALUop has to be 3 bits to represent:
• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, (4) Subtract (5) And (6) Set on <
MainControl
op
6
ALUControl(Local)
func
N
6ALUop
ALUctr
3
R-type ori lw sw beq jump
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx
The Decoding of the “func” Field
R-type ori lw sw beq jump
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx
MainControl
op
6
ALUControl(Local)
func
N
6ALUop
ALUctr
3
op rs rt rd shamt funct
061116212631
R-type
funct<5:0> Instruction Operation
10 0000
10 0010
10 0100
10 0101
10 1010
add
subtract
and
or
set-on-less-than
ALUctr<2:0> ALU Operation
000
001
010
110
111
Add
Subtract
And
Or
Set-on-less-than
Get func from back of book for R-typeOur processor only implements subset ofoperations
The Truth Table for ALUctr<2>
R-type ori lw sw beqALUop(Symbolic) “R-type” Or Add Add Subtract
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0
bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 0
0 1 x x x x x Or 0 0 1
1 x x 0 0 0 0 Add 0 1 0
1 x x 0 0 1 0 Subtract 1 1 0
1 x x 0 1 0 0 And 0 0 0
1 x x 0 1 0 1 Or 0 0 1
1 x x 1 0 1 0 Set on < 1 1 1
funct<3:0> Instruction Op.
0000
0010
0100
0101
1010
add
subtract
and
or
set-on-less-than
This control is for more R-type instructions than our processor, but fewer than the entire MIPS ISA.
The Logic Equation for ALUctr<2>
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<2>
0 x 1 x x x x 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1
° ALUctr<2> = !ALUop<2> & ALUop<0>
+ ALUop<2> & func<1>
The Truth Table for ALUctr <1>
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0
bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 0
0 1 x x x x x Or 0 0 1
1 x x 0 0 0 0 Add 0 1 0
1 x x 0 0 1 0 Subtract 1 1 0
1 x x 0 1 0 0 And 0 0 0
1 x x 0 1 0 1 Or 0 0 1
1 x x 1 0 1 0 Set on < 1 1 1
The Logic Equation for ALUctr<1>
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x 1
ALUctr<1>
0 x 1 x x x x 1
1 x x 0 0 0 0 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1
° ALUctr<1> = !ALUop<2> & !ALUop<1>
+ ALUop<2> & func<2>
The Truth Table for ALUctr<0>
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>
0 0 0 x x x x
ALUctrALUOperation
Add 0 1 0
bit<2> bit<1> bit<0>
0 x 1 x x x x Subtract 1 1 0
0 1 x x x x x Or 0 0 1
1 x x 0 0 0 0 Add 0 1 0
1 x x 0 0 1 0 Subtract 1 1 0
1 x x 0 1 0 0 And 0 0 0
1 x x 0 1 0 1 Or 0 0 1
1 x x 1 0 1 0 Set on < 1 1 1
The Logic Equation for ALUctr<0>
ALUop func
bit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<0>
0 1 x x x x x 1
1 x x 0 1 0 1 1
1 x x 1 0 1 0 1
° ALUctr<0> = !ALUop<2> & ALUop<1>
+ ALUop< 2> & func<2> & func<0>
+ ALUop<2> & func<3>
The ALU Control Block
ALUControl(Local)
func
3
6ALUop
ALUctr
3
° ALUctr<2> = !ALUop<2> & ALUop<0>
+ ALUop<2> & func<1>
° ALUctr<1> = !ALUop<2> & !ALUop<1>
+ ALUop<2> & func<2>
° ALUctr<0> = !ALUop<2> & ALUop<1>
+ ALUop< 2> & func<2> & func<0>
+ ALUop<2> & func<3>
The “Truth Table” for the Main Control
R-type ori lw sw beq jump
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
Branch
Jump
ExtOp
ALUop (Symbolic)
1
0
0
1
0
0
0
x
“R-type”
0
1
0
1
0
0
0
0
Or
0
1
1
1
0
0
0
1
Add
x
1
x
0
1
0
0
1
Add
x
0
x
0
0
1
0
x
Subtract
x
x
x
0
0
0
1
x
xxx
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
ALUop <2> 1 0 0 0 0 x
ALUop <1> 0 1 0 0 0 x
ALUop <0> 0 0 0 0 1 x
MainControl
op
6
ALUControl(Local)
func
3
6
ALUop
ALUctr
3
RegDst
ALUSrc
:
The “Truth Table” for RegWrite
R-type ori lw sw beq jump
RegWrite 1 1 1 0 0 0
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
° RegWrite = R-type + ori + lw
= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type)
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori)
+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)
op<0>
op<5>. .op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
R-type ori lw sw beq jump
RegWrite
PLA Implementation of the Main Control
op<0>
op<5>. .op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
op<5>. .<0>
R-type ori lw sw beq jumpRegWrite
ALUSrc
MemtoReg
MemWrite
Branch
Jump
RegDst
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>
Putting it All Together: A Single Cycle Processor
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrc
ExtOp
Mu
x
MemtoReg
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWrA
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
MainControl
op
6
ALUControlfunc
6
3
ALUopALUctr
3RegDst
ALUSrc
:Instr<5:0>
Instr<31:26>
Instr<15:0>
nPC_sel
An abstract view of the critical path - load instructionCritical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew
Clk
5
Rw Ra Rb
32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
16Imm
32
323232
A
B
Nex
t A
dd
ress
Worst case delay for load is much longer than needed for all other instructions, yet this sets the cycle time.
An Abstract View of the Implementation
° Logical vs. Physical Structure
DataOut
Clk
5
Rw Ra Rb
32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
Summary
° 5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock
methodology• 3. Design datapath meeting the requirements• 4. Analyze implementation of each instruction to determine setting
of control points that effects the register transfer.• 5. Design the control logic
° MIPS makes it easier• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates
° Single cycle datapath => CPI=1, CCT => long
° Next time: implementing control