ZEBROS PROJECTS
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VLSI PROJECTS
FINAL YEAR PROJECTS
IEEE PROJECTS 2013-2014
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ZEBROS PROJECTS
Office Address: No 4 / Flat No 3D, Sai Kiran Apts, First Main Road, Kasturba Nagar, Chennai-20 web: www.zebros.in e mail : [email protected] mob: 99400 98300,9500075001
DESIGN OF TESTABLE REVERSIBLE SEQUENTIAL
CIRCUITS
Abstract
In recent years, reversible logic has emerged as a promising computing
paradigm having its applications in low power computing, quantum computing and
nanotechnology. Power dissipation is one of the most important factors in VLSI circuit
design. Reversible logic naturally takes care of heating since in reversible circuits the
input vectors can be uniquely recovered from its corresponding output vectors. It
shows that zero energy dissipation is possible only if the gating network consists of
reversible gates. Thus reversibility will become future trends towards low power
dissipating circuit design. Conservative logic gates which are based on any sequential
circuit can be tested for typical unidirectional stuck-at faults by only two test vectors.
The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches can
be performed with the help of master-slave flip-flops and double edge triggered (DET)
flip-flop. The significance of the future work lies in the fact that it offers the design of
reversible sequential circuits entirely testable for any stuck-at fault by only two test
vectors, in this way eradicating the need for any access to internal memory cells by
means of scan-path. We examined the fault patterns in the conservative reversible
Fredkin gate due to a single missing/additional cell defect in molecular QCA. We also
displayed the presentation of the proposed method toward 100% fault coverage for
single missing/additional cell defect in the quantum- dot cellular automata (QCA)
layout of the Fredkin gate. A new conservative logic gate called multiplexer
conservative QCA gate (MX-cqca) are also presented and that is not reversible in nature
but has same properties as the Fredkin gate of working as 2:1 multiplexer. The
proposed MX-cqca gate betters the Fredkin gate in terms of density (the number of
majority voters), speed, and area.
ZEBROS PROJECTS
Office Address: No 4 / Flat No 3D, Sai Kiran Apts, First Main Road, Kasturba Nagar, Chennai-20 web: www.zebros.in e mail : [email protected] mob: 99400 98300,9500075001
ZEBROS PROJECTS
SOFTWARE BASED HARDWARE BASED
Networking VLSI
Data Mining Mat lab
Grid Computing Robotics
Network Security Embedded
Image Processing Bio Medical
Web Applications Power Systems
Mobile Computing Power Electronics
Software Engineering Java with Embedded
Cloud Computing Android
What is IEEE?
The Institute of Electrical and Electronics Engineers or IEEE (read eye-triple-e) is Incorporated in the State of New York, United States. It was formed in 1963 by the merger of the Institute of Radio Engineers (IRE, founded 1912) and the American Institute of Electrical Engineers (AIEE, founded 1884). A membership organization comprised of engineers, scientists and students that sets standards for computers and communications. It is a nonprofit organization with more than 365,000 members in around 150 countries.
The IEEE describes itself as "the world's largest technical professional society -- promoting the development and application of electro technology and allied sciences for the benefit of humanity, the advancement of the profession, and the well-being of our members."
Why IEEE based projects?
It grantees for standard
It assured latest solution for problems
It delivers new patented technologies at an ever-increasing pace
It access world-class technical information provided by the IEEE and cut down your
research time.
ZEBROS PROJECTS
Office Address: No 4 / Flat No 3D, Sai Kiran Apts, First Main Road, Kasturba Nagar, Chennai-20 web: www.zebros.in e mail : [email protected] mob: 99400 98300,9500075001
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0th Review 1st Review
Abstract Existing System Disadvantages Proposed System Advantages Objective System Requirements System Architecture
Literature Survey Module List Module Description Data Flow Diagram Level DFD Module Wise DFD Problem Definition Review Document Explanation
2nd Review 3rd Review
Use case Diagram Class Diagram Collaboration Diagram Sequence Diagram Activity Diagram Testing & test cases Partial Code Screenshot for First two
module Review Document Explanation
Conclusion References Future Enhancement 65% code (Executable Format) Required Software Review Document Explanation
Final Review
Complete Code with Enhancement
Final Document (University Standard Format)
Complete Explanation for Project Concept & Code