Indian Journal of Pure & Applied Physics
Vol. 51, January 2013, pp. 60-66
Design and implementation of quantum cellular automata based novel parity
generator and checker circuits with minimum complexity and cell count
M Mustafa & M R Beigh*
Department of Electronics & Instrumentation Technology, University of Kashmir, Kashmir, India
*Email: [email protected]
Received 6 June 2012; revised 23 August 2012; accepted 2 September 2012
Quantum-dot Cellular Automata (QCA) is a possible future nanoelectronic computing technology, based on cells of
coupled quantum dots. The QCA cells have features on the very low nanometer scale, much smaller than the present state of
art size of the smallest transistor. This paper presents design and layout of novel XOR gate implementations with minimum
complexity and cell count in comparison with the already proposed designs. We present here QCA implementation of
combinational circuits like parity generator and checker based on the proposed XOR gate designs. The proposed designs
were verified using simulation from QCA designer tool. These algorithms and simulations are useful for building more
complex circuits based on QCA.
Keywords: Nanoelectronics, Quantum cellular automata, Majority logic, Parity checker, QCA designer
1 Introduction
As the CMOS technologies approach its
fundamental physical limits, there has been extensive
research in recent years in development of
nanotechnology for future generation IC. Gordon
Moore has predicted, in 1965, that the capacity of a
computer chip would grow exponentially with time.
Since then, the so-called Moore’s Law had governed
the development and performance of microprocessors.
Shrinking transistor size has been the major trend to
achieve circuits with fast speed, high densities and low
power dissipation. However, when scaling is brought
down to submicron level, many problems occur with
regard to performance of the circuits. Physical limits
such as quantum effects and non-deterministic
behaviour of small currents and technological limits
like power dissipation and design complexity may
hinder the further progress of microelectronics using
conventional circuit scaling. Consequently to maintain
trends of increasing microprocessor performance,
alternative technologies need to be explored and
developed. As an alternative to CMOS-VLSI,
researchers have proposed an approach to computing
with quantum dots, the quantum cellular automata1
(QCA). QCA is based upon the encoding of binary
information in the charge configuration within
quantum dot cells. Computational power is provided
by the Coulombic interaction between QCA cells. The
local interconnections between cells are provided by
the physics of cell-to-cell interaction due to the
rearrangement of electron positions2. Recent work
showed that QCA can achieve high density, fast
switching speed and room temperature operation3-5
.
QCA cells as well as, the circuits utilizing them have
been fully fabricated and tested by researchers6-9
.The
objective of this paper is to propose a detailed design,
layout and simulation of combinational circuits based
on novel XOR gate configurations. We proposed an
optimal design for XOR based parity generator and
checker circuits. The aim is to maximize the circuit
density and focus on the layouts that are simple and
minimal in their use of cells. The proposed QCA
circuits have been designed and simulated using the
QCA designer tool.
2 Quantum-Dot Cellular Automata
Quantum-dot Cellular Automata emerged as a new
paradigm, beyond current switches to encode binary
information. QCA encodes binary information in the
charge configuration within a cell. Coulomb
interaction between cells is sufficient to accomplish
the computation in QCA arrays-thus no interconnect
wires are needed between cells. No current flows out
of the cell so that low power dissipation is
possible10,11
.
2.1 Basic QCA Device
QCA cells perform computation by interacting
Coulombically with neighbouring cells to influence
each other’s polarization. A high-level diagram of a
four-dot QCA cell is shown in Fig. 1. Four quantum
dots are positioned to form a square. Quantum dots are
small semiconductor or metal islands with a diameter
MUSTAFA & BEIGH: QUANTUM CELLULAR AUTOMATA BASED NOVEL PARITY GENERATOR
61
that is small enough to make their charging energy 12
greater than kBT (where kB is Boltzmann’s constant
and T is the operating temperature in kelvin). In future,
they will shrink to regions within specially designed
molecules13
. If this is the case, they will trap individual
charge barriers8. Exactly two mobile electrons are
loaded in the cell and can move to different quantum
dots in the QCA cell by means of electron tunneling.
Coulombic repulsion will cause the electrons to
occupy only the corners of the QCA cell resulting in
two specific polarizations as shown in Fig. 1.
For an isolated cell, there are two energetically
minimal equivalent arrangements of the two electrons
in the QCA cell, denoted by cell polarizations P = +1
and P = −1 representing a binary 1 and a binary 0,
respectively. It is also worth noting that there is an
unpolarized state as well. In an unpolarized state,
interdot potential barriers are lowered which reduce
the confinement of the electrons on the individual
quantum dots. Consequently, the cells exhibit little or
no polarization and the two-electron wave functions
delocalize across the cell14.
The fundamental QCA logical circuit is the three-
input Majority Gate8 (MG), is shown in Fig. 2.
Computation is performed with the majority gate by
driving the device cell (cell 4 in the figure) to its
lowest energy state. This happens when it assumes the
polarization of the majority of the three input cells.
Gates such as AND and OR can be realized by
forcing a single input to −1 and +1, respectively as
shown in Fig. 2(c). Thus, all the logic gates can be
implemented using MGs.
2.2 QCA Inverter and Wires
QCA inverter can be implemented in two ways-
positioning and rotation. Fig. 3(a) shows one way to
position QCA cells to invert the output from input
logic level. Figure 3(b) shows the way which
successive cells alternate the logic level. The quantum
dots within the QCA cell are rotated by 45°. Fig. 3(c)
shows a more robust QCA NOT implementation.
Figure 4 shows how a binary value propagates
down the length8,12
of a QCA “wire”. The binary
signal propagates from left-to-right in a horizontal row
of QCA cells because of the Coulombic interactions
between cells.
A QCA wire can also be comprised of cells oriented
at 45-degrees [Fig. 3(b)]. With the 45-degree
orientation, as the binary value propagates down the
length of the wire, it alternates between the two
polarizations.
QCA wires possess the unique property that they
are able to cross in the plane without the destruction of
the value being transmitted on either wire. However,
this property holds only if the QCA wires are of
different orientations as shown in Fig. 5.
Fig. 1 — QCA cell polarizations and representations of binary 1
and binary 0
(a) (b)
(c)
Fig. 2 — (a) Fundamental QCA logic device-the majority gate (b)
Circuit symbol (c) AND, OR Implementation
(a) (b)
(c)
Fig. 3 — Implementations of NOT gate
Fig. 4 — QCA Wire
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2.3 QCA Clock
All QCA circuit proposals require a clock not only
to synchronize and control information flow but the
clock actually provides the power to run the circuit.
QCA computation is performed by controlling the
tunneling with a four phase “clock” signal as shown in
Fig. 6. The clocking of QCA can be accomplished by
controlling the potential barriers between adjacent
quantum-dots15,16
. The clock used in QCA consists of
four phases: hold, release, relax, and switch. It is
considered that the lag between adjacent phases is 90°.
Rather, it can be said that the clock changes phase
when the potential barriers that affect a group of QCA
cells (referred to as a clocking zone) are raised or
lowered or remain raised or lowered.
During the switch phase, the inter-dot barrier is
gradually raised, and the QCA cell settles down to one
of the two ground polarization states as influenced by
its neighbours. During the hold phase, the inter dot
barrier is held high, suppressing electron tunneling and
maintaining the current ground polarization state of
the QCA cell.
During the release and relax phases, the inter dot
barriers are lowered, and the excess electrons gain
mobility. In these two phases, a QCA cell remains
unpolarized. Overall, the polarization of a QCA cell is
determined when it is in its switch phase by the
polarizations of its neighbours that are in switch and
hold phases. The unpolarized neighbours in release
and relax phases have no effect on determining the
state of the QCA cell17. The clock signals (through an
induced electric field) can be generated by CMOS
wires embedded below the QCA plane14
.
3 QCA Implementation
The AND and OR gates are realized by fixing the
polarization to one of the inputs of the majority gate to
either P = −1 (logic “0”) or P = 1 (logic “1”).The
NAND function is the complement of AND function.
It is realized by connecting AND gate followed by an
inverter. Similarly the NOR gate is realized by
connecting OR gate followed by an inverter. If the last
two cells are arranged as shown in Fig. 7 then it acts as
an inverter. By using this 2 cell inverter, the area
required and complexity can be minimized.
3.1 XOR Gate
In addition to AND, OR, NOT, NAND and NOR
gates, exclusive-OR (XOR) and exclusive-NOR
(XNOR) gates are also used in the design of digital
circuits. These have special functions and applications.
These gates are particularly useful in arithmetic
operations as well as error-detection and correction
circuits. XOR and XNOR gates are usually found as
2-input gates. No multiple-input XOR/XNOR gates
are available since they are complex to fabricate with
hardware.
The exclusive-OR (XOR) performs the following
logic operation:
A � B = A'B + AB'
The graphic symbol and truth table of XOR gate is
shown in Fig. 8.
Fig. 5 — Two wires crossing in the plane12
Fig. 6 — 4 phases of QCA Clock
Fig. 7 — Layout of NOR and NAND gate
MUSTAFA & BEIGH: QUANTUM CELLULAR AUTOMATA BASED NOVEL PARITY GENERATOR
63
Exclusive or also known as Exclusive disjunction
and symbolized by XOR, is a logical operation on two
operands that results in a logical value of true if and
only if one of the operands, but not both, has a value
of true. This forms a fundamental logic gate in many
operations to follow. If a specific type of gate is not
available, it can be constructed from other available
gates. An XOR gate can be trivially constructed from
an XNOR gate followed by a NOT gate. If we
consider the expression, A'B+AB' we can construct an
XOR gate directly using AND, OR and NOT gates.
However, this approach requires five gates of three
different kinds.
Logically, the exclusive OR (XOR) operation can
be seen as either of the following operations:
(1) AB'+A'B
(2) (A+B) (AB)'
These can be implemented by the gate arrangements
as shown in Fig. 9. They can also be implemented
using NAND gates only.
The QCA implementation for the layout is shown in
Fig. 9(a), has been proposed by different
researchers8,18
. This design needs either coplanar
cross-overs or multiple layers to implement. The
design provided as a sample file with QCA designer19
Version 2.0.3 needs two cross-overs and uses three
layers to implement. This design is shown in Fig. 10.
We propose the QCA design and layout of XOR
gate based on logic gate arrangements as shown in
Figs 9(b-d). The proposed layouts are shown in
Fig. 11. These designs do not require any cross-over
and have minimum number of cell count. According to
QCA designer, the design shown in Fig. 11(a) has
latency of only one clock cycle and consists of just 41
cells (including input and output cells) and an area of
approximately 0.07 �m2. It will require one crossover
in order to input A separately out of the gate. The
designs shown in Fig. 11(b and c) do not require any
cross-overs. The design in Fig. 11(c) uses a robust
NOT gate and has a latency of 1.5 clock cycles.
The simulation results for the layouts shown in
Fig. 11(a), (b) and (c), are shown in Fig. 12(a), (b) and
(c), respectively. As seen from the simulation results,
the first layout has a latency of one clock cycle, the
second one has two and the third layout has a latency
of only 1.5 clock cycles.
Table 1 gives the comparison of proposed designs
with that of conventional design as shown in Fig. 10.
It is evident from Table 1 that the proposed designs
are efficient in terms of cell count, area and cross-
overs (number of layers).
The proposed layouts can be easily used to design
complex circuits based on XOR operation. We will
present here a parity generator and checker circuits
based on the layouts shown in Fig. 11. We have used
the XOR layout shown in Fig. 11(a), for being the
simplest in implementation, and one out of those
shown in Fig. 11(b and c).
3.2 Parity Generator and Checker
Exclusive-OR functions are very useful in systems
using parity bits for error-detection. A parity bit is
Fig. 8 — XOR gate truth table and graphic symbol
(a) (b)
(c) (d)
Fig. 9 — Implementations of XOR
Fig. 10 — Conventional XOR implementation
INDIAN J PURE & APPL PHYS, VOL 51, JANUARY 2013
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used for the purpose of detecting errors during
transmission of binary information. A parity bit is an
extra bit included with a binary message to make the
total number of 1’s in this message (including the
parity bit) either odd or even. The message, including
the parity bit, is transmitted and then checked at the
receiving end for errors. An error is detected if the
checked parity does not correspond with the one
transmitted. The circuit that generates the parity bit at
(a)
(b)
(c)
Fig. 12 — Simulation results of proposed XOR layouts
Table 1 — Feature comparison of various designs
Proposed Designs Fig. 11 Feature Conventional
Design (Fig. 10) (a) (b) (c)
Area(�m2) 0.09 0.07 0.09 0.09
Cell count 88 44 55 62
Number of
Crossovers
2 1 0 0
Latency 1 1 2 1.5
the transmitter side is called a parity generator. The
circuit that checks the parity at the receiver side is
called a parity checker.
As an example, consider a 3-bit message to be
transmitted together with an even parity bit. The Table
in Fig. 13 shows the truth table for the even parity
(a)
(b)
(c)
Fig. 11 — Proposed QCA XOR implementations
MUSTAFA & BEIGH: QUANTUM CELLULAR AUTOMATA BASED NOVEL PARITY GENERATOR
65
generator. The three bits, X, Y, and Z, constitute the
message and are the inputs to the even parity generator
circuit whose output is the parity bit P.
For even parity, whenever the message bits (X, Y and
Z) have an odd number of 1’s, the parity bit P must be
1. Otherwise, P must be 0. Therefore, P can be
expressed as three-variable exclusive-OR function:
P = X � Y � Z. The logic diagram for the even parity
generator circuit is also shown in Fig. 13.
The layout of Parity Generator is shown in
Fig. 14(a). It consists of 99 cells with an area of
0.17 �m2. Figure 14(b) shows the simulation results
for this layout. The latency of the layout is 2 clock
cycles and hence the above mentioned output P, can be
found after an interval of 2 clocks from the inputs
X, Y and Z.
The 4 bits (X, Y, Z and P) are transmitted to their
destination, where they are applied to a parity-checker
circuit to check for possible errors in the transmission.
Since the information was transmitted with even
parity, the received four bits must have an even
number of 1’s. The parity checker generates an error
signal (C = 1), whenever the received four bits have an
odd number of 1’s. The table in Fig. 15 shows the
truth table for the even-parity checker. The logic
diagram of the even-parity checker is also shown in
Fig. 15.
The layout of Parity Checker is shown in Fig. 16(a).
Here we have used 145 cells with an area of 0.28 �m2.
Figure 16(b) shows the simulation results for the given
layout. The latency of the layout is 3 clock cycles and
hence the output C, can be found after an interval of 3
clocks from the inputs X, Y, Z and P. The logic
implementation is done using: C = X� Y� Z � P
It is worth noting that the parity generator can also
be implemented with the circuit of this figure if the
input P is connected to logic-0 and the output is
marked with P. This is because Z�0 = Z, causing the
value of Z to pass through the gate unchanged. The
advantage of this is that the same circuit can be used
for both parity generation and checking.
The Parity checker design reported in Ref. 18 has
approximately double the area and cell count as
compared to the proposed design with the same
latency. Thus, the proposed design is simple in
Fig 1 3 — Logic diagram and Truth table for even parity
generator
(a)
(b)
Fig. 14 — Parity generator layout and simulation results
Fig. 15 — Logic diagram and truth table for parity checker
INDIAN J PURE & APPL PHYS, VOL 51, JANUARY 2013
66
implementation, uses lesser number of cell count and
obviously consumes less area and power.
4 Conclusions
This paper presents the design, layout and
simulation of combinational circuits based on novel
XOR gate configurations. An optimal design for XOR
based parity generator and checker circuits is
proposed. The proposed layouts were simulated using
QCA designer, the design and simulation tool for
QCA based circuits. These designs are efficient in
terms of cell count, area and power consumption. They
also enjoy the advantage of coplanar design without
using cross-overs. We conclude QCA technology one
of the promising nanotechnologies in future that can
be used to build arithmetic logic units and
microprocessors etc. There are further opportunities
for optimization which could lead to densities greater
than reported in our present work and could be taken
up for further studies. The current QCA technology
does not specifically set the possible operating
frequency and actual propagation delays, but it can be
analyzed as an important parameter in future works.
This research work is an attempt to find a reasonable
and optimum, way of realizing combinational circuits
designed from a simple QCA based XOR gate.
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(a)
(b)
Fig. 16 — Parity checker layout and simulation results