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Decoders

Outline

Useful MSI circuits

Decoders

Implementing Functions with Decoders

Decoders with Enable

Larger Decoders

Standard MSI Decoders


Outline

Useful MSI circuits

Decoders



Larger Decoders



Useful MSI circuits

Four common and useful MSI circuits are: Decoder Encoder Demultiplexer Multiplexer

Block-level outlines of MSI circuits:

decodercode entity

encodercodeentity

mux datainput

select

demuxdata output

select

Outline

Useful MSI circuits

Decoders



Larger Decoders



Decoders (1/5)

Codes are frequently used to represent entities, e.g. your name is a code to denote yourself (an entity!).

These codes can be identified (or decoded) using a decoder. Given a code, identify the entity.

Convert binary information from n input lines to (max. of) 2n output lines.

Known as n-to-m-line decoder, or simply n:m or nm decoder (m 2n).

May be used to generate 2n (or fewer) minterms of n input variables.

Decoders (2/5)

Example: if codes 00, 01, 10, 11 are used to identify four light bulbs, we may use a 2-bit decoder:

2x4Dec2-bit

codeX

Y

F0

F1

F2

F3

Bulb 0Bulb 1Bulb 2Bulb 3

This is a 24 decoder which selects an output line based on the 2-bit code supplied.

Truth table:X Y F0 F1 F2 F3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

Decoders (3/5)

From truth table, circuit for 24 decoder is:

Note:

Each output is a 2-variable minterm (X'.Y', X'.Y, X.Y' or X.Y)

X Y F0 F1 F2 F3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

F0 = X'.Y'

F1 = X'.Y

F2 = X.Y'

F3 = X.Y

X Y

Decoders (4/5)

Design a 38 decoder.

x y z F0 F1 F2 F3 F4 F5 F6 F7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

F1 = x'.y'.z

x zy

F0 = x'.y'.z'

F2 = x'.y.z'

F3 = x'.y.z

F5 = x.y'.z

F4 = x.y'.z'

F6 = x.y.z'

F7 = x.y.z

Application?

Binary-to-octal conversion.

Decoders (5/5)

In general, for an n-bit code, a decoder could select up to 2n lines:

: :n-bitcode

n to 2n

decoderup to 2n

output lines

Outline

Useful MSI circuits

Decoders



Larger Decoders



Decoders: Implementing Functions (1/5)

A Boolean function, in sum-of-minterms form decoder to generate the minterms, and an OR gate to form the sum.

Any combinational circuit with n inputs and m outputs can be implemented with an n:2n decoder with m OR gates.

Good when circuit has many outputs, and each function is expressed with few minterms.


Example: Full adder

S(x, y, z) = m(1,2,4,7)

C(x, y, z) = m(3,5,6,7)

3x8Dec

S2

S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1


3x8Dec

S2

S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

10000000

0

0

0

0

0


3x8Dec

S2

S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

01000000

1

0

0

0

1


3x8Dec

S2

S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

00000001

1

1

1

1

1

Outline

Useful MSI circuits

Decoders



Larger Decoders



Decoders with Enable (1/2)

Decoders often come with an enable signal, so that the device is only activated when the enable, E=1.

Truth table:

E X Y F0 F1 F2 F3

1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 X X 0 0 0 0

F0 = EX'Y'

F1 = EX'Y

F2 = EXY'

F3 = EXY

X Y E

Circuit:

Decoders with Enable (2/2)

In the previous slide, the decoder has a one-enable signal, that is, the decoder is enabled with E=1.

In most MSI decoders, enable signal is zero-enable, usually denoted by E’ (or E). The decoder is enabled when the signal is zero.

E X Y F0 F1 F2 F3

1 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 10 X X 0 0 0 0

E' X Y F0 F1 F2 F3

0 0 0 1 0 0 00 0 1 0 1 0 00 1 0 0 0 1 00 1 1 0 0 0 11 X X 0 0 0 0

Decoder with 1-enable Decoder with 0-enable

Outline

Useful MSI circuits

Decoders



Larger Decoders



Larger Decoders (1/6)

Larger decoders can be constructed from smaller ones.

For example, a 3-to-8 decoder can be constructed from two 2-to-4 decoders (with one-enable), as follows:

3x8Dec

S2

S1

S0

wxy

01::7

F0 = w'x'y'F1 = w'x'y::F7 = wxy

2x4Dec

S1

S0

0123

F0 = w'x'y'F1 = w'x'yF2 = w'xy'F3 = w'xyE

2x4Dec

S1

S0

0123

F4 = wx'y'F5 = wx'yF6 = wxy'F7 = wxyE

wxy


3x8Dec

S2

S1

S0

wxy

01::7

F0 = w'x'y'F1 = w'x'y::F7 = wxy

2x4Dec

S1

S0

0123


2x4Dec

S1

S0

0123


wxy

000

0000

1000

0 = disabled

1 = enabled


3x8Dec

S2

S1

S0

wxy

01::7

F0 = w'x'y'F1 = w'x'y::F7 = wxy

2x4Dec

S1

S0

0123


2x4Dec

S1

S0

0123


wxy

001

0000

0100

0 = disabled

1 = enabled


3x8Dec

S2

S1

S0

wxy

01::7

F0 = w'x'y'F1 = w'x'y::F7 = wxy

2x4Dec

S1

S0

0123


2x4Dec

S1

S0

0123


wxy

110

0010

0000

1 = enabled

0 = disabled


Construct a 4x16 decoder from two 3x8 decoders with 1-enable.

4x16DecS3

S2

S1

S0

wxyz

01::

15

F0

F1

::F15

3x8Dec

S2

S1

S0

01:7

F0

F1

:F7E

3x8Dec

S2

S1

S0

01:7

F8

F9

:F15E

wxyz


Note: The input, w and its complement, w', is used to select either one of the two smaller decoders.

Decoders may also have zero-enable and/or negated outputs. (Normal outputs = active high; negated outputs = active low.)

Exercise:

What modifications must be made to provide an ENABLE input for the 3x8 decoder (2 slides ago) and the 4x16 decoder (previous slide) created?

Exercise:

How to construct a 4x16 decoder using five 2x4 decoders with enable?

Outline

Useful MSI circuits

Decoders



Larger Decoders



Standard MSI Decoders (1/2)

74138 (3-to-8 decoder)

74138 decoder module. (a) Logic circuit. (b) Package pin configuration.

Standard MSI Decoders (2/2)

74138 decoder module.

(c) Function table.

74138 decoder module. (d) Generic symbol. (e) IEEE standard logic symbol.

Source: The Data Book Volume 2, Texas Instruments Inc.,1985

Negated outputs

Outline

Useful MSI circuits

Decoders



Larger Decoders



Decoders: Implementing Functions Revisit (1/2)

Example: Implement the following logic function using decoders and logic gates

f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)

We may implement the function in several ways:

(a) Use a decoder (with active-high outputs) with an OR gate:f(Q,X,P) = m0 + m1 + m4 + m6 + m7

(b) Use a decoder (with active-low outputs) with a NAND gate:

f(Q,X,P) = ( m0' . m1' . m4' . m6' . m7' )'

(c) Use a decoder (with active-high outputs) with a NOR gate:f(Q,X,P) = ( m2 + m3 + m5 )' [ = M2.M3.M5]

(d) Use a decoder (with active-low outputs) with an AND gate:f(Q,X,P) = m2' . m3' . m5'

Decoders: Implementing Functions Revisit (2/2)

3x8Dec

A

B

C

Q

X

P

01234567

f(Q,X,P) f(Q,X,P)

3x8Dec

A

B

C

Q

X

P

01234567

3x8Dec

A

B

C

Q

X

P

01234567

f(Q,X,P) f(Q,X,P)

3x8Dec

A

B

C

Q

X

P

01234567

(a) Active-high decoder with OR gate. (b) Active-low decoder with NAND gate.

(c) Active-high decoder with NOR gate. (d) Active-low decoder with AND gate.

f(Q,X,P) = m(0,1,4,6,7)