CSE331 W01.1 Irwin Fall 07 PSU
CSE 331Computer Organization and
DesignFall 2007
Week 1
Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)
Section 2: Krishna Narayanan
Course material on ANGEL: cms.psu.edu
[slides adapted from D. Patterson slides with additional credits to Y. Xie]
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Course Administration Instr (Sec1): Mary Jane Irwin ([email protected])
348C IST Bldg OH’s: Tues 2:30 – 3:45pm & Wed 9:15 – 10:30am
Instr (Sec2): Krishna Narayanan ([email protected] ) 348D IST Bldg OH’s: TBD
TA: Evens Jean ([email protected] ) 360E IST Bldg OH’s: Tues, Thurs 2:30 – 4:00pm
Web: ANGEL, cms.psu.edu Lab: Accounts on CSE machines in 220 IST, Windows
Lab Texts: Computer Organization and Design: The
Hardware/Software Interface, 3rd Edition Revised Printing, Patterson and Hennessy
VHDL Starter’s Guide, 2nd Edition, Yalamanchili
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Grading Information Grade determinates
Exam #1~20%
- Tuesday, October 2, 6:30 – 7:45pm, 113 IST
Exam #2~20%
- Thursday, November 8, 6:30 – 7:45, 113 IST
Final Exam ~25%- Section 1 & 2: TBD
Homeworks/Programming Assignments ~25% Quizzes (in-class & ANGEL) ~ 5% Class attendance ~
5%
CSE 331 is a “C required course” for both CmpSc and CmpEng majors
Email instructor ASAP if you have an exam conflict !
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Grading Policies Assignments will be submitted electronically through
ANGEL and must be submitted by 5:00pm on the due date. No late assignments will be accepted.
Most programming assignments will follow the “pair programming” paradigm
Duplicate assignments will receive duplicate grades of zero. Second offenses will result in a final course grade of F.
Grades will be posted on the ANGEL website See TA about questions on the assignments; see instructors
about grading questions on the exams Must submit email request for change of grade after
discussions with the TA or instructor December 12 deadline for filing grade corrections; no requests
for grade changes/updates will be accepted after this date
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What is Pair Programming?
Two programmers work side-by-side at one computer continuously collaborating on the same design, algorithm, code, or test
The fourteen principles of pair programming Share everything Play fair – take turns
“driving”, when not “driving” don’t be a passive observer, do be active and engaged
Don’t hit people – stay on task (so no reading email or surfing) … Take a nap (or a break from working together) every afternoon
Why do it? Has been shown to improve productivity and the quality of
software
http://portal.acm.org/citation.cfm?id=332833.332848&coll=portal&dl=ACM&idx=332833&part=periodical&WantType=periodical&title=Communications%20of%20the%20ACM&CFID=891725&CFTOKEN=22811657
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Course Goals and Structure
Introduction to the major components of a computer system, how they function together in executing a program, how they are designed
MIPS assembler programming using the spim system VHDL design simulation using Mentor Graphics ModelSim
Prerequisite: CSE 271 (INTRO TO DIGITAL SYSTEMS. Introduction to logic design and digital systems, boolean algebra, and introduction to combinatorial and sequential circuit design and analysis)
If you are also taking CSE 472 you will learn yet another assembly language (Motorola 68HC12)
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spim Assembler and Simulator
spim is a simulator that runs MIPS32 assembly language programs
It provides a simple assembler, debugger and a simple set of operating system services
It implements both a simple, terminal-style interface (spim) and a visual windowing interface (xspim and PCSpim)
(Version 7.3) available as xspim (or spim) for unix, linux, and Mac OS X
- Installed on the CSE unix/linux machines in the lab
PCSpim (or spim) for Windows (NT, 2000, XP)- Installed on the CSE windows machines in 220 IST and/or can
be downloaded and installed on your own PC from
http://pages.cs.wisc.edu/~larus/spim.html
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vhdl Simulation ModelSim is a hardware description language simulator
from Mentor Graphics Simulation (gate-level and RTL-level) and integrated debug
environment- Verilog and VHDL
- Intuitive GUI for post-simulation debug and analysis
http://www.model.com/products/products_se.asp - ModelSim SE is installed on the windows machines in 220 IST
ModelSim PE Student Edition is available for free download from
http://www.model.com/resources/student_edition/student_default.asp
If you are taking CSE 471 or 478 you will gain even more experience with the Mentor Graphics tools
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ModelSim Screen Shot
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What You Should Already Know How to write, compile and run programs in a higher
level language (C, C++, Java, …) How to represent and operate on positive and negative
numbers in binary form (two’s complement, sign magnitude, etc.)
Logic design How to design of combinational and sequential components
(Boolean algebra, logic minimization, technology mapping, decoders and multiplexors, latches and flipflops, registers, mealy/moore finite state machines, state assignment and minimization, etc.)
How to use a logic schematic capture and simulation tool (e.g., LogicWorks)
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Schedule
This week’s material Course introduction, basics of a computer system,
introduction to SPIM
- Reading assignment – PH 1.1 through 1.3 and A.9
Next week’s material Introduction to MIPS assembler, adds/loads/stores
- Reading assignment - PH 2.1 through 2.4
Entire semester course schedule can be accessed on ANGEL under the Lessons tab
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Quote for the Day
“I got the idea for the mouse while attending a talk at a computer conference. The speaker was so boring that I started daydreaming and hit upon the idea.”
Doug Engelbart
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The Evolution of Computer Hardware
When was the first transistor invented? Modern-day electronics began with the invention in
1947 of the transfer resistor - the bi-polar transistor - by Bardeen et.al at Bell Laboratories
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The Evolution of Computer Hardware
When was the first IC (integrated circuit) invented? In 1958 the IC was “born” when Jack Kilby at
Texas Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate
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The Underlying Technologies
Year Technology Relative Perform/Unit Cost
1951 Vacuum Tube 1
1965 Transistor 35
1975 Integrated Circuit (IC) 900
1995 Very Large Scale IC (VLSI) 2,400,000
2005 Submicron VLSI 6,200,000,000
What if technology in the transportation industry advanced at the same rate?
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The PowerPC 750
Introduced in 1999
3.65M transistors366 MHz clock
rate40 mm2 die size250nm
(0.25micron) technology
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Technology Outlook
High Volume Manufacturing
2004 2006 2008 2010 2012 2014 2016 2018
Technology Node (nm)
90 65 45 32 22 16 11 8
Integration Capacity (BT)
2 4 8 16 32 64 128 256
Delay = CV/I scaling
0.7 ~0.7 >0.7 Delay scaling will slow down
Energy/Logic Op scaling
>0.35 >0.5 >0.5 Energy scaling will slow down
Bulk Planar CMOS High Probability Low ProbabilityAlternate, 3G etc Low Probability High ProbabilityVariability Medium High Very HighILD (K) ~3 <3 Reduce slowly towards 2 to 2.5RC Delay 1 1 1 1 1 1 1 1
Metal Layers 6-7 7-8 8-9 0.5 to 1 layer per generation
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Impacts of Advancing TechnologyProcessor
logic capacity: increases about 30% per year
performance: 2x every 1.5 to 2 years
Memory DRAM capacity: 4x every 3 years, about 60% per
year speed: 1.5x every 10 years cost per bit: decreases about 25% per year
Disk capacity: increases about 60% per year speed: cost per bit:
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Growth Capacity of DRAM Chips
K = 1024 (210)In recent years growth rate has slowed to 2x every 2 year
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Computer Organization and Design
This course is all about how computers work
But what do we mean by a computer? Different types: embedded, laptop, desktop, server
Different uses: automobiles, graphics, finance, genomics,…
Different manufacturers: Intel, AMD, IBM, HP, Apple, IBM, Sony, Sun …
Different underlying technologies and different costs !
Best way to learn: Focus on a specific instance and learn how it works
While learning general principles and historical perspectives
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Embedded Computers in You Car
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Growth of Sales of Embedded Computers
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Why Learn This Stuff?
You want to call yourself a “computer scientist/engineer”
You want to build HW/SW people use (so you need to deliver performance at low cost)
You need to make a purchasing decision or offer “expert” advice
Both hardware and software affect performance The algorithm (CSE 465) determines number of source-level
statements
The language/compiler/architecture (CSE 428/421/331&431) determine the number of machine-level instructions
- (Chapter 2 and 3)
The processor/memory (CSE 331&431) determine how fast machine-level instructions are executed
- (Chapter 5, 6, and 7)
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What is a Computer?
Components: processor (datapath, control) input (mouse, keyboard) output (display, printer) memory (cache (SRAM), main memory (DRAM), disk
drive, CD/DVD) network
Our primary focus: the processor (datapath and control)
Implemented using millions of transistors Impossible to understand by looking at each transistor We need abstraction!
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Major Components of a Computer
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Head’s Up This week’s material
Course introduction- Reading assignment – PH 1.1 through 1.3 and A.9
Reminders Make sure your CSE account is operational; change your
password to something you can remember and that is secure (must be 12 or more alphanumeric characters of three types)
Question/comments about the system go to [email protected] ; questions about the programming assignments go to the course TA
Check out the course homepage at ANGEL!
Next week’s material Introduction to MIPS assembler
- Reading assignment - PH 2.1 through 3.3, 3.4, and 3.7
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Quote for the Day
“We all make mistakes … Our designs have to work flawlessly despite us.”
Bob Colwell
The Pentium Chronicles
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Below the Program High-level language program (in C)
swap (int v[], int k)(int temp;
temp = v[k];v[k] = v[k+1];v[k+1] = temp;
)
Assembly language program (for MIPS)swap: sll $2, $5, 2
add $2, $4, $2lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)jr $31
Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000
. . .
C compiler
assembler
one-to-many
one-to-one
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Advantages of Higher-Level Languages ?
Higher-level languages
As a result, very little programming is done today at the assembler level
Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, Java for web programming, …)
Improve programmer productivity – more understandable code that is easier to debug and validate
Improve program maintainability Allow programs to be independent of the computer on which
they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine)
Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine
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Machine Organization
Capabilities and performance characteristics of the principal Functional Units (FUs)
e.g., register file, ALU, multiplexors, memories, ...
The ways those FUs are interconnected
e.g., buses
Logic and means by which information flow between FUs is controlled
The machine’s Instruction Set Architecture (ISA) Register Transfer Level (RTL) machine description
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ISA Sales
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Major Components of a Computer
Processor
Control
Datapath
Memory
Devices
Input
Output
Network
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Below the Program
C compiler
assembler
High-level language program (in C) swap (int v[], int k) . . . Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31
Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000
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Input Device Inputs Object Code
Processor
Control
Datapath
Memory
000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000
Devices
Input
Output
Network
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Object Code Stored in Memory
Processor
Control
Datapath
Memory
000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000
Devices
Input
Output
Network
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Processor Fetches an Instruction
Processor
Control
Datapath
Memory
000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000
Processor fetches an instruction from memory
Devices
Input
Output
Network
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Control Decodes the Instruction
Processor
Control
Datapath
Memory000000 00100 00010 0001000000100000
Control decodes the instruction to determine what to execute
Devices
Input
Output
Network
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Datapath Executes the Instruction
Processor
Control
Datapath
Memory
contents Reg #4 ADD contents Reg #2results put in Reg #2
Datapath executes the instruction as directed by control
000000 00100 00010 0001000000100000
Devices
Input
Output
Network
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What Happens Next?
Processor
Control
Datapath
Memory
000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000
Fetch
DecodeExec
Devices
Input
Output
Network
Processor fetches the next instruction from memory
How does it know which location in memory to fetch
from next?
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Processor Organization Control needs to have circuitry to
What location does it load from and store to?
Decide which is the next instruction and input it from memory Decode the instruction Issue signals that control the way information flows between
datapath components Control what operations the datapath’s functional units
perform
Execute instructions - functional units (e.g., adder) and storage locations (e.g., register file)
Interconnect the functional units so that the instructions can be executed as required
Load data from and store data to memory
Datapath needs to have circuitry to
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Output Data Stored in Memory
Processor
Control
Datapath
Memory
000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000
At program completion the data to be output resides in memory
Devices
Input
Output
Network
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Output Device Outputs Data
Processor
Control
Datapath
Memory
000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000
Devices
Input
Output
Network
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The Instruction Set Architecture (ISA)
instruction set architecture
software
hardware
The interface description separating the software and hardware
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The MIPS ISA
Instruction Categories Load/Store Computational Jump and Branch Floating Point
- coprocessor
Memory Management Special
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
Q: How many already familiar with MIPS ISA?
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How Do the Pieces Fit Together?
I/O systemProcessor
Compiler
OperatingSystem
Applications
Digital Design
Circuit Design
Instruction Set Architecture
Firmware
Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation
Memory system
Datapath & Control
network
CSE 411CSE 421
CSE 331 & 431
CSE 447 & 477
CSE 271 & 471
CSE 458
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Review and Reminder Next week’s material
Introduction to MIPS assembler- Reading assignment - PH 2.1 through 2.4
Homework 1 due on Tuesday, Sept. 4 by 5:00 PM- Submit on ANGEL – individual programming this time !
Other reminders Install PCSpim on your laptop Keep track of course updates on ANGEL Make sure your CSE account is operational; change your
password to something you can remember and that is secure (must be at least 12 alphanumeric characters of 3 types)
Question/comments about the lab hardware/system go to [email protected] ; questions about the programming assignments go to the course TA