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SPICE
by
L. W. Nagel and D. O. Pederson
Memorandum No. UCB/ERL M382
12 April 1973
\Presented at the 16 MidveEt Symposium on Circuit Theory,
Waterloo, Ontario, April 12, 1973.
Simulation Program with Integrated Circuit Emphasis(SPICE)
'•*; L. W. Nagel and D. 0. Pederson
W
«. %
Department of Electrical Engineering and Computer Sciencesand the Electronics Research Laboratory
University of California, Berkeley, California 94720
AbstractA new circuit simulation program, SPICE, is described. The
simulation capabilities of nonlinear dc analysis, small signal analysis,and nonlinear transient analysis are combined in a nodal analysis programto yield a reasonably general purpose electronic circuit simulationprogram. Particular emphasis i6 placed upon the circuit modelsfor the BJT and the FET which are implemented in SPICE.
Research sponsored by the National Science Foundation, Grant GK-17931
•X- ^lE'ST. digital computer to simulate the el•««£*£™*«*tt~"of electronic circuits has been an important part of circuit '«*£«'-.evaluation since the advent of integrated circuits. The peculiarities« of Integrated circuit design, such as the need for dc coupling and* minimal use of resistances, made hand analysis of even the earliest
analog Integrated circuits Impractical. Increased size and complexityv of both analog and digital integrated circuits have made computer simulation* an even more important factor in/efficient circuit design. A circuitsimulation program has an additional advantage at academic institutions,in that it provides students with a "dry lab" capability. In essence,
* each student is supplied with his own "workbench" where he can design,build, and test circuits in a fraction of the time and expense that areal laboratory would require. This allows for a more relevant andeducational set of assignments than noraally would be possible in thetime constraints of an academic term.
Because of the several advantages of computer simulation, we havebeen heavily involved in the development and use of simulation programsfor several years. We found available programs to be either too cumbersome or too inefficient for classroom use, and it became necessary todevelop our own set of simulation prograas. The first program developedat our laboratory was BIAS [1]. The need for a transient analysiscapability lead to the development of CANCER [2] and TIME [3]. A newversion of TIME, entitled SINC, has been developed by S. P. Fan at ourlaboratory. Our program SLIC (Simulator for Linear Integrated Circuits)[4] was developed especially for the aiculation of analog integratedcircuits. The latest prograc developed at our laboratory is SPICE(Simulation Program with Integrated Circuit Emphasis). This program isan improvement of the CANCER program and is used extensively forclassroom instruction and graduate research for the large signal simulation of analog and digital integrated circuits.
II. Description of SPICESPICE is a general purpose simulation program for integrated
circuits. It contains the three basic analysis capabilities whichprovide the bulk of information of a circuit's performance: a) nonlinear dc analysis, with the provision for "stepping" an input source toobtain a set of static transfer curves, b) small-signal, sinusoidalsteady-state analysis, including a noise analysis [5] to evaluate noiseperformance, c) nonlinear, time-domain, transient analysis.The circuit size limitations for SPICE are 400 nodes, and 200 total elements.of which no more than 100 can be semiconductor devices. A user's guidefor the SPICE program is included in the Appendix.
Built-in models are included for the most common semiconductordevices: diodes, bipolar junction transistors (BJT's), junction field-effect, transistors (JFET's). and metal-oxide-semiconductor field-effecttransistors (MOSFET's). The BJT models are based on either the Ebers-Holl 110] or the Cummel-Poon [17] formulations; the models for the FET sare derived from the model of Shlchman and Hodges [6].
Because SPICE is used extensively for undergraduate instruction, itwas designed to be easy to learn and easy to use. The input language isfree format to minimize user errors. Where possible, the programsupplies "default" values for circuit parameters that are not specified,
so that the beginning user need specify only-few ^j^™^™*arguable either as abular istings of the output variables or!s Uneprinter plots! The program contains 8000 Fortran IV statementsSd requires AO.uOO decimal words of core memory to execute on the c~ 6
'•«, available at the University of California, Berkeley.The basic program organization is shown in Figure 1 The 'i-i^isdescribed on aIll'o?^ c-ds. ^program «"t rea sa, processe
i- the Input deck and checks for input errors. The next step f th. «.-£.--1 U establishing the necessary set of pointers for the sparse matrix re s
171 Thase nolnters enable the two dimensional Y matrix to De cci-apsec£2. aone'dimensional vector containing only the nonzero*£»» S««iv.t*. «atrix routines then operate only on the nonzero terms container .a t.n.svector! This saves asubstantial amount of core memory and central processor"^The^ext^tep in the simulation is the actual analysis. One set ofroutines is used for the iterative solution of the nodal equations for dcanalysis or for a given timepoint in the transient analysis [2], andSorter sel or routines is used for the solution of the complex nodalequations in the small signal analysis. .«„,™,ri«t»The final simulation step is the output phase, where the appropriatetabular listings and line printer plots are generated. Droeraln
As mentioned earlier, SPICE is an improvement of the CANCER V™?3*'and many of rt" algorithms used in SPICE are the same as those used xnCANCER and discussed in Ref. [2). In particular, the sPa"e"££*routines in both CANCER and SPICE are improvements of those °"|™£ydeveloped by Berry [7]. The basic Newton iteration alf°"tnm of SrxC.and CANCER are the same, and both programs use an implicit, trapezoidalEtegration formula and afixed, user supplied timestep for transientanalysis. The small-signal.routines are similar, except that a^presentation of flicker (i) noise [8] has been added to the noiseanalysis of SPICE. The actual Fortran coding has been substantiallyimproved in the transition from CANCER to SPICE.
I1ITheBmost°silnificant development in SPICE is the implementation ofadequate device models for the BJT. JFET. and MOSFET Because the BJTis so important in integrated circuits, the BJT model deserves special
' ' ""tw^BJT models were necessary to accomodate the separate needs for asimple model to be used in classroom use and for amore soP«*»'lc"»* ,
•• model for graduate research. Both models are represented by the electr ea-•chematic shown in Figure 2. The charge storage elements QB£ ^V^\...represent the stored base charge and depletion layer charges. The pSras.cicelements r ,rw, r .and C-- are assumed to be constant. The dc charac-"eristics Sf X simpler mSlel are derived from the familiar Ebers-Mollmodel 1101 with an added representation of basewidth modulation 111.,.The dc, intrinsic model is defined by the terminal equations:
*An overlaid version can be executed in approximately 25,000 decimal wor.is.
'c-'sh(5V). mQty [, %]. i [„r (*) -i]
S H-jjKtyHbW*:- where q is the electronic charge, k is Boltzman's constant, and T is the: absolute temperature. The remaining variables, Ig, $f, B , and V , are
user supplied model parameters. The saturation current, Ig, is the extra-. polated intercept current of log (I-) versus V in the forward region and
log (I )versus V_r in the reverse region as shown in Figure 3. The parameters |f and B are the forward and reverse short circuit current gains,respectively, which are assumed not to vary with operationg point. Theparameter VA, referred to as the "Early voltage", produces a finite valueof output conductance, g , due to basewidth modulation. The output conductance is given by the equation:
%
8o
Hence, output conductance is proportional to Ic> with the constant ofproportionality being (y ). A graphical intepretation of VA is shown inFigure 4.
The nonlinear charge storage elements QBE and Q are determined bythe equations:
V
/ V "*e
«BE **F «. h [~W)~ l] +Cieo J [*" yVBC _ ^-o
«BC•*R h[«P fkf)" *] +CJco j [~ h] C
dV
dV
Possibly a more meaningful method of expressing these charge storageelement equations is the voltage dependent, small-signal capacitanceformulae:
c -!5kBc 3VBC
Charge storage is modeled by two base storage terms, whidi.are characterizedw III llZllit times t and t . and two depletion terms which areSaractertzed by the parameters C.eo. *.and .. for the emitter depletion
" ~£on andc ... and m for tnfcolfector dlpletion region. For theSS SerslfiSil^det. tfie parameters m and » are fixed at avalue\ of 0.5. The numerical instability of theedeplet£on layer capacitance
formulae is avoided by using a linear approximation for depletion
^he's^mpler E^s-Sou'transistor model lacks arepresentation of .any ••of the important second order effects present in actual devices; the rwomost important neglected effects are high level ^ection which causes adrop in 8, and 8 and an increase in t, and t when high level injectionIs reachel [12. h. 14). and depletionflayer recombination which causesa drop inx, andx at low levels of collector current [15]. These ei.ec.sare iicludeS in thl more complicated BJT model that is implemented ir.SPICE. This model is an adaptation of the model proposed by Gur=e- a...Poon [16. 17, 18). The equations for the dc characteristics are:
^h(^)-^vshr*)-1]where the normalized base charge, C^, Is defined by the equations:
V V* . 14. *C 4. I|E1 VA B
Ib-iIvA2*"1*]
-5-
The model parameters for the dc portion of the Gummel-Poon model are Ig,T a C C n .n .I,., lu .VA, »d V The charge 6tora*eBfmt Brm* 29 gA* e* nc' k* kr» A* B - .- .elements Qot? and Qnr are identical to the SPICE Ebers-Moll model.
BE •**• . .The second order effect of depletion layer recombination is
Included in the model with the two nonideal base current componentsdetermined by the parameters C2 and n for the emitter depletion regionand C and n for the collect©* region. This is shown in the graph ofI agiinst V* shown in Figured. Both the effect of basewidthmodulation aSI asimple treatment of high level injection «•*»*£*}«•*Into the model via the base charge term, ^. This is best understood byconsidering two limiting cases. First, consider the case when Q2s-0.Then, in the forward region,
I *C VBC
1 v vVA B
^ - {ty-H ~> (^) [x -^]•
low level injection,
4XS /*VBb\« 1.
the collector current follows the "ideal" law:
hvh"» m1 For high levels of injection.
»i.
the collector current becomes "nonldeal"
7^ ~P \2kT-J«.„
Hence the emission coefficient changes from 1 (ideal) to 2as predictedoy first oX theory [12]. Asimilar argument holds for the reverseregion, where high level injection occurs when
4Is /«vbc\ :rj «* K-vr)" l'The narameters I, and''I,, are termed the forward knee current and thereversed current. anl can be interpreted as the approximate valueof collector current (for forward region) and emitter current (forreverse region) where high level injection becomes significant.
Serhaps more insight into the SPICE Gummel-Poon parameters is obtainedbv inspection of the asymptotic behavior of the short circuit currentJain « shown in Figure6. The current gain is essentially constant at avalue of 8™ for collector currents greater than J_ , falls off ,-with aslofg of 1-l/ne for collector currents l<»ss than I.«**•£" ofrwith a slope of -1 for collector currents greater than Ifc; 1^, the lowcurrent breakpoint, is given by the equation:
ne
\ mh tc2Me<
This, of course, is only an asymptotic relation. For cases where lowlevel and high level effects overlap, as is true in most transistors,some trial and error is required to obtain the correct parameters.
Although not obvious from the defining equations, the effectivetransit times of the device, and hence the f is also dependent uponcollector current. The effective forward transit time is given by:
'flCff1 •lef^V*BHence, as high level injection is reached, Tf is no longer constant butInstead is directly proportional to Qfi, as shown in Figure 7.
The more complex Gummel-Poon modelDthat is implemented in SPICE hasbeen quite adequate for the graduate research in our laboratory [19].However, we anticipate the necessity of adding current dependent baseresistance [12] and base pushout [171 into the model.
Default and typical values for the Ebers Moll and Gummel-Poon•jodels parameters are given In the Appendix.
-7-
IV. Circuit examplesThe shunt-series feedback amplifier 6hown in Figure 8 provides an
illustrative example of the difference between the two BJT models inan actual circuit simulation. This circuit was simulated using themodel parameters shown in Table 1. The graph of the forward currentgain against Ir is superimposed on the asymptotic curve shown inFigure 6. For the Ebers-Moll model, 0- "as chosen to match the amplifiergain in the Gumcel-Poon simulation. The first stage of the circuitoperates at a bias current one decade above the lower knee current^I - 1 wA while the second stage is biased at 1 mA. The upper Tcneecurrent I. is 3 mA. Since the circuit is current-driven, the effectsof a current-dependent beta are more pronounced than with a voltage-driven circuit.
The dc transfer curve of V against I , for the open loop case(IL^ and R-. removed), is shown in Figure 9. The maximum dc swingpredicted by the two models differs by 48%, while the small signalgain at aero input differs by about 12%. In the transient analysis,a 0.02 pA (peak-to-peak) sine wave with a frequency of 100kHz wasapplied to the input. The Ebers-Moll simulation predicted an outputvoltage of 2.00 volts (peak-to-peak), while the Gummel-Poon simulationpredicted an output voltage of 1.78 volts (peak-to-peak). _
When the"simulation was repeated for the closed loop case (Kp.and R_, are now included; the loop gain is 2.65) the maximum dc swingwas of course the same; the small-signal gain differed by about 6% forthe two models, and the transient output voltage differed by about 7%for the two models.
The necessity for a more complex BJT model is obviously circuitdependent. The above example was purposefully chosen to accentuate thedifferences between the two models; in many circuit designs thedifference in the predicted waveforms is much less. The centralprocessor time required for these two simulations was 4.6 sec for theEbers-Moll model and 5.2 sec for the Gummel-Poon model. Of thesetimes, 2.1 sec was required for reading, error checking, matrix setup,and output; the Gummel-Poon model hence requires 25% additional time ona per Newton Iteration basis or 13% total additional job time.
"Additional simulation"execution times are shown In~Table 2 for aSN7400 TTL inverter and in Table 3 for the uA 741 operational amplifier.Both of these examples used the Ebers-Moll transistor model. Thesetimes were observed on the CDC 6400 computer available at the Universityof California Computer Center at Berkeley.
V. FET Models a . .The increasing use of the M0SFET device in digital integrated circuits,
and to a lesser extent the JFET device in analog integrated circuits,necessitated the inclusion of suitable models for these two devices. The .circuit schematic for the JFET model used in SPICE is shown in Figure 10.
*M
- V
The two parasitic ohmic resistances. »a and r^ •"'^Yimple %£?•The equation for internal drain current, ID. Is taken as • "™P" "J™" ...law relation with an added parameter to model channel width ovulation [6].The piecewSe relations for the various regions of operation of the JFETare:
X. Vns >0 (forward region)
y 'OS" 'TO* °BOU- vTO)2 (i +xv„) o <vGS- vT0< vns
xcs
'gs to' dsav„el2(vr_Q- vT0) - vDSl d ♦ xvDS) o <vDS< vGS- v.
'ds1*v:gs vto' wds
II. V_c < 0 (reverse region)
TO
V - V «< 0VGD TO
"•<W V2 (1 "XV °*V*>" VT0< "VDS*V2(VGD- V +V (1 "XW °*"W VGD- VT0
The three dc parameter which determine the ^T operation are Vto,8 and X. The parameter VT0. which is always negative for JFET s. ismosfcommonS referred to Is the "pi.eh.ff" ™}"*e-* **''"Tf"rans-8and Vto are probably best understood by examining the graph of transconductance. g*. as afunction of V§S (in the forward ""™^ln«£on)as shown in Figure 11. The tranaconductance is assumed to be a llne"functt™ of VG! with aslope of 26. The parameter Xis analogous to theP«ameterVA fir BJT's. The output conductance of the device, in theforward saturated region, is given by the equation:
8<18at -6X(VGS- VM)2 -XI„Hence, the output conductance is assumed to vary linearly with draincurrentl with the constant of proportionality being X. The graphic•fnt-enretation of the parameter is shown in Figure 12.
Thl two gate Junctions are modeled as ideal diodes with the followingdefining equations:
*cd •h["* (~kf^) •" x]The charge storage elements, QGS and Qgd, are modeled as ideal, step
Junc^Ln deletion Lpacitances. because the gate l^J^^^J^reverse biased, the diffusion charge storage mechanism is omitted. Thecharge storage elements are defined by the equations:
V is assumed to be negative for all depletion mode devicesTO - - ------irrespective of channel polarity.
-9-
VGS
<fcs " ccso J A.v_M/2
VGDdV
Oct " CGDO I /.> V„\l/2JFWAs for the depletion capacitances in the bipolar modele, these chargestorage elementscan also be expressed in terms of the voltage dependent.small signal capacitances:
1-1/2
CGS * CGS0
CGD " CGD0
[-*}
R]The MOSFET model used in SPICE is very similar to the model proposed
fev Shiehman and Hodges.1*1Although more sophisticated models for theby Snicnman ana noages. *r23t243, we have found this model adequateMOSFET device have been proposed,i"»~*rf» « ***»„+ ftffor our investigations. It includes arepresentation of the effect ofsubstrate bias on gate threshold voltage and areprRation «^he effectof channel width modulation. The circuit schematic for the SPICE MOSFETmodel is shown in Figure 13. The internal drain current generator. In. isgiven by the following piecewise equations for aU regions of operation ofthe MOSFET device:
I. v > 0 (forward region)Do
*te - vio+* [v'^r -^v - V < 0VGS TE
h-{6(VGS- VTE>2 (1 **V ° *VGS" VTE' VDS-6 V2(VGS- VTE> " V <X +XV ° *W 'OS" VTE
II. V-,c < 0 (reversed region)
v„„- VTO< 0fO CD TE
\ -»(»„- vIE)2 (x -xvDS) o«•*„-*„« •U VDS12(VCD- V +VDS] (1 -XV0S) 0<-VDS< VGD-
"VDS
TE
The five dc parameters which determine the operating characteristics«* iZ MOSFET are- *l-o. 8. X, y and *. The interpretation of theof the MOSFET are. *T0. *• "J t Tthe interpretation of theseparameters Vjo, 6and X*»^£a* £ <f the £STtI, VT0 ie positive for
the following defining equations:
ha'h
The charge storage effect, in the MOSFET £*£.»j^* ^stant.capacitances. The capacitors CCD. Cgs. «»d Cgb «• '"*aal °,t junctionThe charge storage elements Qbd and QBS »re treated as ">•"• "»p Jdepletion capacilances. Sine! the substrate 3-nctions "« ~™£lv ^reverse biased, the diffusion charge storage mechanism is omitted. Thesetwo charge storage elements are defined by the equations:
VBD/dV
o *B
VBS/dV
<*BS"CBS0 J fl_^l/2
These elements can alao be expressed in terms of the voltage dependent,small signal capacitances:
V.^ 1-1/2
CBD " CBDO
CBS " SsO
t-%][-%]
B
V_ 1-1/2
-11-
We have found these FET models quite adequate for both instructionaluse and research. To attain reasonable convergence in the dc analysisit is necessary to limit the change in VGS and Vgp from iteration toiteration, just as it is necessary to linlt junction voltage changes.I2'Ve have found an acceptable limit to be 0.1 + \Vjo\ (volts). The gatejunctions for JFET*8 and the substrate junctions for MOSFET's aremodeled by an equivalent conductance
• "kT
in the reverse bias region (where they normally operate). With theseprecautions, we have found the convergence properties of the FET modelsto be comparable to those of the BJT models.
Default and typical values for JFET and MOSFET model parametersare shown in the Appendix.
VI. Conclusions :The implementation of suitable device models for the BJT and FET's,
coupled with improved program coding and organization, has provided uswith a simulation program which is much more powerful and efficient than
its predecessor, CANCER. However, one can never assume that a simulationprogram is complete, and we forsee many enhancements for SPICE at thetime of this writing.
The most desirable addition to the program is a reliable timestepcontrol in the transient analysis. Our program SINC has a timestepcontrol which is based on the Iteration count at each timepolnt; however,we have found this method not totally satisfactory in controlling thestability properties of the trapezoidal method. Instead, it is necessaryto estimate and control the truncation error at each timepolnt to obtaina satisfactory transient solution. Because of the method in which enintegration algorithm is implemented in a nodal analysis program [2, 20],the use of variable order Integration methods [21, 22] constitute atremendous increase in. the program code. Furthermore, our research hasshown that higher order integration algorithms are poorly suited to thehighly nonlinear digital logic circuits because of their inherent poorstability properties. The major problem in a tlmestep control is theestimation of truncation error, which aaounts to numerical differentiation.Since higher order formulae require estimation of higher order derivatives,a reliable estimation of truncation error can only become more difficultas order is increased. At this time, it appears that a single order,probably Euler or Trapezoidal, is the most reliable and efficient integration algorithm to use in a nodal analysis program.
VII. AcknowledgementsWe are pleased to acknowledge the contributions and valuable dis
cussions of S. Chisholm, R. I. Dowell, S. P. Fan, I. E. Getreau, D. A. Hodges,W. J. McCalla, R. G. Meyer, and R. A. Roarer. 'We also gratefully acknowledgethe many hours of computer time provided us by the Computer Center of theUniversity of California, Berkeley, without which it would have been impossibleto develop SPICE. The work on SPICE has been supported by the NationalScience Foundation, Grant GK-17931.
ADDENDUM
Flicker Noise Analysis in SPICE
The ability to simulate flicker noise sources in the noise analysis
of SPICE (refer to IEEE Journal of Solid State Circuits, August 1971,
pp. 204-215) has been added to SPICE. Flicker noise is included by
adding another term to the current generators for the devices:
a. Junction diodes /
2 "!j| -2, In Af +-^ Af
b. Bipolar Junction Transistors
i£ -2q IB Af +KIaK1Bf
Af
c. Field effect transistors (both JFET's and MOSFET's).
KIa4«AkT(fgn)Af+-1*Af
For bipolar devices, our measurements have shown that ael for npn
devices and a«=1.5 for pnp devices, and ^6.6 x 10 for npn devices
—13and 0.3 x 10 for pnp devices (these measurements are for the
devices in a 741 operational amplifier, but should be representative
of monolithic devices in general).
Operationally, the flicker noise parameters are defined on the
•MODEL card by setting two parameters:
FNK Flicker noise coefficient DefaulfO. 0
FNA Flicker noise exponent Default"0.1
-12a-
«. I
These parameter names are the same for all four devices. Hence,
a model card for an npn transistor, with flicker noise, might look
like:
0
.MODEL Ml NPN BF-35 RB»100 RE-0.1 IS-1.5E-15 FNK-6.6E-16 FNA-1.0
External Models in SPICE
The ability to define an arbitrary device which contains allowable
elements has been included in SPICE (versions IG and later). Hence
the gate shown in Figure 1 could be defined to be an element in
SPICE just as a bipolar device is a model in SPICE. The restrictions
are:
a. External models cannot be nested, that is, an external model
cannot contain an external model.
b. An external model cannot have more than 20 external nodes (the
gate on the following page has 5 external nodes and three internal
nodes)•
To define an external model, a group of cards is required. The
first card is a .MODEL card which contains the word .MODEL, the name
of the model, the letter X, and the external nodes of the device.
The following cards are the set of element cards which define the
model card, and the last card is a .FINIS card, which contains simply
the word .FINIS. The following group of cards defines the TTL gate
shown in Figure 1.
•MODEL TTLGATE X 1 2 3 4 5 .Ql 6 8 1 MlQ2 6 8 2 MlQ3 6 8 3 MlQ4 4 6 7 MlQ5 4 7 0 Ml
-12b-
'%
Rl 5 4 IK
R2 7 0 1.5KR5 5 8 4K.MODEL Ml NPN BF*80 RB=50 TF«0;1NS TR-10NS CJC-0.3PF CJE-0.5PF.FINIS
Once the model has been defdined, it can be referenced just as an
internal built-in model is referenced. The "device" name must begin
with the letter X. The device is specified by the name, the external
nodes, and the model name. For example, the logic circuit shown in
Figure 2 could be simulated by the following group of cards:
EXAMPLE LOGIC CIRCUIT
VCC 10 0 DC 5
VIN1 1 0 PULSE 0 5 IONS IONS IONS 100NS
VIN2 2 0 PULSE 0 5 200NS IONS IONS 100NS
XG1 1113 10 TTLGATE
XG2 1 1 2 4 10 TTLGATE
XG5 5 2 4 5 10 TTLGATE
.OUT V5 5 0 PLOT TRAN
•TRAN 5NS 500NS
•MODEL TTLGATE 112345
*Q1*6..&.1.M1Q2 6 8 2 MlQ3 6 8 3 MlQ4 4 6 7 MlQ5 4 7 0 MlRl 5 4 IK '
R2 7 0 1.5K
R3 5 8 4K
.MODEL Ml NPN BF«80 RB=50 TF^O.INS TR-10NS CJC-0.3PF CJE=0.5PF
•FINIS
•END
-12c-
DC Sensitivity Analysis in SPICE
A dc sensitivity analysis capability was also included in SPICE
(versions IG and later) but never documented. This option is used to
obtain the dc, small-signal sensitivities of a given output variable
with respect to every circuit value. The general format for sensitivity
analysis is:
.SENS ovar 1 ovar 2. ... ovar 10
Note that from one to ten outputs can be specified. Only one .SENS
card should be used in a deck. The syntax for the output variables
(ovar 1 ... ovar n) is identical to the syntax for output variables
in the .OUTPUT card.
Examples:
SENS^VOUT .3 .2
.SENS VI 1 0 V2 2 0 IX VCC
If a .SENS card is included in the SPICE data deck, the program will
compute the dc, small-signal sensitivities (derivatives) at each
specified output variable with respect to every circuit value
(including the dc parameters for BJT model and diode model). There
is no way of selecting specific sensitivities. In the first example,
the program will compute and print the derivative of the voltage
between node 3 and node 2 with respect to every circuit parameter.
-12d-
© ©•
© /
c* 7\
©K*l
MIKd. r*
®
VtKl. f;
1IK
6)
R2.
1-5K.
K Q5
/*
©*6*
o<r
-12e-
©
• »
<• .-
SPICE 1Q, (1 Mar 74)
The latest version of SPICE, SPICE 1Q, is now released. Versions
1M, IN, 10, and IP were all local versions, so 1Q is the replacement
version for SPICE IL. In contains the following modifications:
1. Overlay organization - The program structure has beenmodified slightly to readily accomodate an overlaystructure. The program requires a 60000 octal regionto execute on the CDC 6400 computer at the Universityof California, Berkeley.
2. Distortion analysis - A new analysis algorithm forcomputing the small-signal distortion performanceof a linear circuit has been implemented. For furtherdetails on the theory of distortion analysis, seeTrans. IEEE, Vol. CT-7, November 1973, pp. 709 - 717and pp. 742 - 746.
3. Revised .OUTPUT control card - To accomodate distortionanalysis; and to add some flexibility to the AC analysisoutput, the .OUTPUT format has been modified.
4. Assembly language matrix routines - The matrix decompositionand solution routines have been recoded in COMPASS
._•., •asseably^languag.c. ...For .CDC users, ..this results in"a savings of 10% - 40%. For non-CDC users, the FORTRAN
code has been included, as comments, in the assemblyroutines, and can be easily reinstated.
5. Addition of the .RUN card - The .RUN control card has beenadded to allow the printing of various executionstatistics (matrix structure, number of iterations,and timing data for each phase of a simulation).
6. FET convergence - The routines for JFET's and MOSFET'shave been modified to improve the convergence ofsimulations involving JFET's and MOSFET's.
7. Small-signal dc transfer curve errors - An error in thecomputation of the dc, small-signal input resistance,transfer function, and output resistance has beencorrected.
8. Gummel-Poon temperature dependence - An error that causedthe saturation currents in the Gummel-Poon transistormodel to be computed incorrectly (as a function oftemperature) has been corrected.
-12f-
9 Voltage source polarity error -An error that caused the'* £iarit?tf voltage sources to sometimes be reversed has
been corrected.
[ SPICE 1Q 1NP"T FORMAT CHANCES
1. Distortion analysis
- SPICE will compute the distortion characteristics ofthe circuit in a small-signal mode as a part of theac small-signal sinusoidal steady-state analysisif requested. The analysis is performed assumingthat signals of two frequencies are imposed at theinput; let the two frequencies be ^ and f2.
The program then computes the following distortionmeasures:
HD2 - The magnitude of the frequency component 2 fxassuming that f2 is not present.
HD3 - The magnitude of the frequency component 3 f1assuming that ±2 is not present.
...:&B£2 •— ..The.oftagnitude.of .the..frequency component i^ + f2
DIM2 - The magnitude of the frequency component fx - f2
DIM3 - The magnitude of the frequency component 2fx - f2
All of these distortion measures can be computed at eachfrequency point (value of fx) and printed or Plotted(either as REAL and IMAG, or as MAG, DB, and PHASE)just as any other output variable. In addition, atspecified frequencies, the contribution of every nonlineardevice to the total distortion can be printed.
\- Distortion analysis is specified on the .AC card:
•AC DEC 10 1 10KHZ DISTO RLOAD INTER REFPWR SKW2 SPW2
any legal freq optional - defaultsvariation format supplied if not specified
KHERE:
RLOAD - The name of the output load resistor intowhich all distortion power products areto be computed (must be specified).
-12g-
INTER - The interval at which the summary P^outof the contributions of all nonlinear devicesto the total distortion is to be printed.Zero implies no printout, 1 Implies every point,2 implies every other point, 3 implies everythird point, and so on. Defaults to zero ifnot specified.
REFPWR - The reference power level used in computingthe distortion products. If not specified,a value of 1 mW (that is, dBm) is used.
SKW2 - The ratio of f2 to fr If not specified,a value of 0.9 is used (i.e., f2 - 0.9 fx).
SPW2 - The amplitude of f2. A value of 1.0 is used ifnot specified.
EXAMPLE: .AC DEC 10 1.0 100K DISTO RL 2 1.0E-3 0.95 0.75
2. Output options (.OUTPUT card)
Some new options have-been added to the .OUTPUT card toaccomodate distortion analysis and improve output forAC analysis:
..AqiUPUT.Vxxxxxx.Nl N2 .PRINT (options) .PLOT^(options)Ixxxxxx Vyyyyy "0N0ISE either print or plot or both canRINOISE be deletedHD2
HD3
SIM2
DIM2
SIM3
The output variable Vxxxxxx is a voltage output (Nl is thepositive node, and N2 is the negative node), Ixxxxxx is acurrent output (Vyyyyyy is the voltage source the current isflowing in), 0N0ISE is the output noise computed in thenoise analysis, RINOISE is the reflected input noise computedin the noise analysis, and HD2, HD3, SIM2, D1M2, and DIM3are the distortion measures mentioned in distortion analysis.
The options available are:
DC dc analysis outputTR transient analysis outputMAG ac analysis output, magnitudeDB *c analysis output, magnitude (in dB)PHS ac analysis output, phaseRE ac analysis output, real partIM ac analysis output, imaginary part
-12h-
Some output examples:
To plot a transient response of node voltage 4
.OUTPUT V4 4 0 PLOT TR
To print and plot the dc transfer curve for node voltage 17and the bode plot for node voltage 17
.OUTPUT V17 17 0PRINT DC^lAG DB PHS PLOT MAG DB PHS DCTo plot the output noise and equivalent input noise in bothvolts and dB:
.OUTPUT ONOISE PLOT MAG DB
.OUTPUT RINOISE PLOT MAG DB
To plot the distortion measures HD2, HD3, DIM2, and DIM3:
.OUTPUT HD2 PLOT DB PHS
.OUTPUT HD3 PLOT DB PHS
.OUTPUT DIM2 PLOT DB PHS
.OUTPUT DIM3 PLOT DB PHS
3. .RUN card - If a .RUN card is included in the input deck,-*~the -program will print matrix statistics,
circuit statistics, and timing information.. . This data is not printed if the .RUN card is
absent.
-12i-
•. i
MUTUAL INDUCTORS
SPICE 1Q also contains provision for specifying a
coupling between inductors in the circuit. A mutual
inductance is specified by the following card:
uxxxxxx Lyyyyyy Lzzzzzz value
The name must begin with a U. Lyyyyyy and Lzzzzzz are the
two coupled inductors, and 'value1 is the value of mutual
inductance between the inductors. The coefficient of
coupling/ k, is defined by:
k « _M
Li L2
where M is the mutual inductance/ and l1 and L2 are the
values of inductance for the two coupled inductors.
This coeff.detent of ..coupling, must..always Jxe l*ss tnan
unity.in absolute value. A negative value of M inverts
the direction in which current flows. The following data
deck defines an ac analysis of the simple transformer cir
cuit shov/n below.
TEST OF MUTUAL INDUCTANCEII 0 1 AC 1KIN 1 0 IK
LI 1 0 1UH
L2 2 0 1UHU12 LI L2 0.99UH
RLOAD 2 0 IK•AC DEC 10 10 100KHZ.OUTPUT VI 1 0 PLOT MAG PHS.OUTPUT V2 2 0 PLOT MAG PHS• END
11
-12j-
LZ, ffft.L*AD
y I
TYPICAL BJT AND FET PARAMETERS
For bipolar transistors, forward and inverse current gains, outputconductance or Early voltage, and emitter saturation current are measuredat .typical active region operating point. Collector series resistance
1. measured at' atypical saturated region operating point. Base seriesresistance is calculated from mask dimensions and base sheet resistance.The three depletion layer capacitances are calculated at aero bias frommask dimensions and process specifications. Forward and inverse transittimes are calculated from these capacitances (under bias) and measuredvalues of forward and inverse current gain-bandwidth (fj). taken at a
typical operating point. These eleven parameters are adequate to characterize integrated circuit bipolar transistors in almost all analog anddigital applications. Representative values for a small IC transistor
* * • •
are given in Table I.
Once these parameters are known for one transistor made by a given
process, parameters for devices of differing mask geometry may be determined without further measurements. Current gains, Early voltage, and
transit times are to first order independent of mask geometry for npn
.IC transistors. Emitter saturation current, junction capacitances, and
series resistances are simple functions of mask dimensions and process
specifications. The most troublesome parameters in this scaling process
are the inverse current gain and inverse transit time; due to the trend
toward non-saturating and Schottky clamped circuits, the significance of
these parameters is decreasing. In such circuits, inverse parameters
have virtually no influence on circuit performance.
-12k-
This approach to modeling bipolar IC components usually willproduce circuit simulation results accurate to within .05 Vin DClevels and to within 102 in time and frequency domain characteristics.
Substantially more effort is needed to reduce errors by afactor of
two.
A similar approach works well for MOS transistor model parameter
determination. Asample device made by the chosen process is evaluated.Threshold voltage, gain factor (k or Beta), body effect coefficient,
and output conductance or Early voltage are measured. The five inter-electrode capacitances are calculated from mask dimensions and process
specifications. Source-body and drain-body capacitances are those ofnormal pn junctions. Gate area and oxide capacitance determine the
total capacitance from gate to source, body, and drain. This capacitance
.may be divided into two or three parts. For static MOS circuits,
dividing this capacitance into equal, constant gate-source and gate-
drain components is simple and adequate. For dynamic circuits (particularly
the ratioless type), gate capacitance should be divided into three
voltage-dependent parts. Representative parameters for a small p-
channel silicon-gate MOS transistor are shown in Table II.
Parameters for other MOS transistors, differing in mask geometry
from the sample device, are obtained by scaling. Gain factor and
capacitances are simple functions of geometry; the other parameters
are independent of geometry in first-order approximation.
-12£-
FORWARD BETA 10°• INVERSE BETA f -16 '
" v EMITTER SATURATION CURRENT 2 x 10 AEARLY VOLTAGE 50 V .
' " COLLECTOR SERIE£ RESISTANCE 50 ftV.' BASE SERIES RESISTANCE 50 ft
FORWARD TRANSIT TUB ' 0.3 nSINVERSE TRANSIT TIME . 10 nSEMITTER JUNCTION CAPACITANCE 0.5 pFCOLLECTOR JUNCTION CAPACITANCE • 0.5 pFSUBSTRATE JUNCTION CAPACITANCE . 1.0 pF
TABLE I
CHANNEL WIDTH TO LENGTH RATIO ' .1.0THRESHOLD VOLTAGE
GAIN FACTOR
BODY EFFECT
EARLY VOLTAGE
SOURCE-BODY CAPACITANCEDRAIN-BODY CAPACITANCE
GATE-SOURCE CAPACITANCE
GATE-DRAIN CAPACITANCE
GATE-BODY CAPACITANCE
2 V
2 uA/V*0.75 V1'*
50 V
0.05 pF0.05 pF0.01 pF0.01 pF
-0
TABLE II
-12m-
\\ w
REFERENCES
W. J. McCalla and W. G. Howard. Jr., y»*-***^£f*Nonlinear DC Analysis of Bipolar Transistor Circuits, IEEE^KSolid State Circuits, vol. SC-6, Feb. 1971, pp. 14-1*.
121 L Nagel and R. Rohrer, "Computer Analysis of Nonlinear Circuits,11 kcludlng^adiation (CANCER)." TIM J. Solid State Circuits, vol.
SC-6, Aug. 1971. pp. 166-182.
Ml v S Jenkins and S. P. Fan, 'TIME — A Nonlinear DC and Time131 ^in C^itTimuiation Program." ITT,?, J. Solid State Circuits,vol. SC-6, Aug. 1971, pp. 182-188.
[4) T. E. Idleman, F. S. Jenkins, W. J. McCalla. and D. 0. person,1 "SLIC - ASimulator for Linear Integrated Circuits IEEE^
Solid State Circuits, vol. SC-6, Aug. 1971, pp. 188-203..
l5] R. A. Rohrer. L. W. Nagel. R. Meyer, and L. Weber. "ComputationallyEfficient Electronic Circuit Noise Calculations," IEEE J. SolidState Circuits, vol. SC-6, Aug. 1971, pp. 204-213.
[6] H. Shichman and D. A. Hodges, '•Modeling and Simulation of In-lated-Gate Field-Effect Transistor Switching Circuits.'IEEE J. SolidState Circuits, vol. SC-3. Sept. 1968, pp. 285-289.
171 a D Berry. "An Optimal Ordering of Electronic Circuit Equations11 for alllVae Matrix Solution." tIpp. Tr»ns. Circuit Theory, vol.
CT-18, Jan. 1971, pp. 40-50.
[8] R. Meyer, L. Nagel. and S. I. Lui, "Computer Simulation of &Noise Performance of Electronic Circuits," to appear, IEEE J. SolidState Circuits, Dec. 1973.
[9]"" P. E.Gray, et al., Physical Electronics and Circuit Models ofTransistors, SEEC, Vol. II, Wiley, Chicago, 1964.
[10] J. J. Elbers and J. L. Moll, "Large Signal Behavior of JunctionTransistors," Proc. IRE, vol. 42, Dec. 1954, pp. 1761-1772.
[11) J. M. Early, "Effects of Space-Charge Layer Widening in JunctionTransistors," Proc. IRE, vol. 46, Nov. 1952, pp. 1141-1152.
[12) W. M. Webster, "On the Variation of Junction Transistor CurrentCain Amplification Factor with Emitter Current," Proc. IRE,vol. 42, June 1954, pp. 914-920.
'* t
[13) C. T. Kirk, Jr., "A Theory of Transistor Cutoff Frequency (O atHigh Current Densities," IRE Trans. Electron Devices, vol, Et>-9,Mar. 1962, pp. 164-174.
1141 R. J. Whittler and D. A. Tremere, "Current Cain and CutoffFrequency Falloff at High Currents," IEEE Trans. Electron Devices,vol. ED-16, Jan. 1969, pp. 39-57.
[15] C. T. Sah, R. N. Noyc'e, and W. Shockley, "Carrier Generation and1 J Recombination in p-n Junctions and p-n Junction Characteristics,
Proc. IRE, vol. 45, Sept. 1957, pp. 1228-1243.
[16) H. K. Gummel. "A Charge Control *eUtion for Bipolar Transistors."I J »ell System Tech. J., vol. 49, Jan. 1970. pp. 115-120.tl71 H K. Gummel and H. C. Poon, "An Integral Charge Control Model ofII Sipoiar^ansistors." lall System Tech. J.. vol. 49. May/June 1970.
pp. 827-852.
[18]
[19)
R I. Dowell. "Automated Biasing of Integrated Circuits." Ph.D.Thesis. University of California, Berkeley, March 1972.
I. B. Getreau, "Low-Voltage, Micropower Integrated Amplifiers,"Ph.D. Thesis, University of California, Berkeley, March 1972.
[20] W. J. McCalla and D. 0. Pederaon, ^«*f•of ^u^f*£* i97l.Circuit Analysis," IEEE Trans. Circuit Theory, vol. CT-18, June x97l,pp. 14-26.
[211 C. W. Gear, "The Automatic Integration of Stiff Ordinary Differentia11 Equations,1 Information Processing 68, A. J. H. Morrell, Ed.,
Amsterdam, the Netherlands, 1969, pp. 187-193.
!7?1 * K Bravton F. G. Gustavson, and G. D. Hachtal, "The Use of11 SariabSeKr Sarlabie-Step Backward Differentiation Methods forNonlinear Electrical Networks," New Mexico 1971 InternationalIEEE Conf. Systems. Networks, and Computers, Oaxtepec, Mexico,pp. 102-106.
[23] D. Frohman-Bentchskowsky and L. Vadasz, "S^^^S^^sS^Characterization of Digital MOS Integrated Circuits, IEEE J. SolidState Circuits, vol. Sfc-3, Sept. 1968, pp. 285-289.
[24] A. S. Grove, Physics and Technology of Semiconductor Devices, NewYork, Wiley, 1968.
TABLE 1
'- BJT MODEL PARAMETERS FOR SHUNT-SERIES FEEDBACK AMPLIFIER
\[ EBERS-MOLL GUMMEL-POON
$- 75 *mF i *,
100
1
*r ,/ ™ ^-14R 1.0X10-14 Xr 1«10I„ A.U X XU *Ss
*cOr
r ee r 100t. 1 ns C2
xR ° *k
0
0
0
F .ft t 3mA
2
68 0c o c4 o„jC° 1 nF I infiniteCjco 1PF *» 2♦e * "' 2e i
♦- X TF1 ns
c 050 TR °VA 50
-15-
CcsCjeoCjcoV 50
Ay_ infinite
1
0.5
1
0.5
B
Te
me
♦cm
c
0
0
lpF
TABLE 2
EXECUTION TIMES FOR SN7400 TTL INVERTER
(27 NODES, 8 BJT1 S, 101 TIMEPOINTS)
READIN °-A2 6ec
SETUP °*08 sec
DC ANALYSIS 0.52 sec(ITERATIONS) (22>
TRANSIENT 7#26,!?!L(ITERATIONS) • C340)
OUTPUT 0.92 sec
TOTAL 9-20 8ec
TIME PER NEWTON ITERATION:
TIME PER NEWTON INTERATION PER BJT:
21.4 msec
2.7 msec
•• \
\ I /
TABLE 3
EXECUTION TIMES FOR 741 OP AMP
(49 NODES, 22 BJTS, 101 TIMEPOINTS)
READIN
SETUP
DC ANALYSIS(ITERATIONS)
TRANSIENT
(ITERATIONS)
OUTPUT
TOTAL
TIME PER NEWTON ITERATION:
TIME PER NEWTON INTERATION PER BJT:
0.8 sec
0.5 sec
0.9 sec(12)
13.6 sec
•(203)
0.9 sec
16.7 sec
67 msec
3 msec
. 1r*
•* ^
•
CONTROL
/ PROGRAM
L
INIPUT DC; AND
ERROR TRANSIENT OUTPUT
CHECKING ANALYSIS.
1
•
SPARSE SIAALL
MATRIX SIGNAL
SETUP
1
ANALYSIS
Figure 1
-18-
*.. • /
B
VftC -
Figure 2
.10.
Co
Vce
Is to
800
Figure 3
Figure 4
I*-1* *
~lt10
*•* **» goo
Figure 5
« :
I -f
H
t•4 e
•AI
+ O
.> \
VI%
4
+ 'ft
7
Figure 6
2*ll •
oo
#
Figure 7
-24-
i : '.
oo
>
Figure 6
-25-
% %
Figure 9
«9A-
9iI
%
H
.. •»
1
in
rr
ff
Qto
I*o
t*
+ v a©
6 o
Figure 10
_M_
De
rji
+
vos
/
8*
/ iMM
• V«.s
-Vt.
Figure 11
0H
Figure 12
(A
\4
6 *•
Cm
/
o
o
I»Du
Qft©
+ V&o - w—
Vos ©I
+ VW -
Cos•W
C&&
6
Figure 13
-30-
- Vas
KH
z«s
0Qas
-e
* .
% I » I I I I i II v«$
-lo -5
fy t 0*1 i>*^
Figure 14
/
APPENDIX
UNIVERSITYOFCALIFORNIA
COLLEGE
OF
ENGINEERING
OEPAATNENT
OFELECTRICAL
ENGINEERING
AND
COMPUTER
SCIENCES
IM
NACtl
00
PEOERSON
29
APR
TJ
USERS
GUIOE
FOR
SPICE
I
SPICE
ISAGENERALPURPOSE
CIRCUIT
SIMULATION
PROGRAMm
WNLlMMNt
NONLINEAR
TRANSIENT.
AND
LINEAR
ACANALYSIS.
CIRCUITS
MAY"CONTAINJ""™"*
CAPACITORS.
INDUCTDRS.
INDEPENDENT
VOLTAGE
ANDCURRENT
SOURCES,
VOLTAGE
DEPFNOENT
CURRENT
SOURCES.
ANDTHE
FOUR
MOST
COMMON
SEMICONDUCTOR
DEVICES!
BJTS.
DIODES,JFETSANDHOSFETS.
SPICE
MASBUILT-IN
MOOELS
FOR
THE
SEMICONDUCTOR
DEVICES,
«*"™E
USER...f
SPECIFIES
ONLY
THE
PERTINENT
MODEL
PARAMETER
VALUES.
TWO"ODELS
AREAVAILABLE
FOR
THE
BJT.
THE
SIMPLER
NOOEL
ISBASEOON
THE
EBERS-MOLL
MODEL
AND
INCLUDES
CHARGE
STOOGE
EFFECTS.
OHMIC
RESISTANCES.
ANOACURRENTOEPENOENT
OUTPUT
CONDUCTANCE.
ANOOEL
BASEOON
THE
INTEGRAL
CHARGE
NOOEL
OFGUNNEL
ANDP30N
ISALSO
AVAILABLE
FOR
PROBLEMS
WHICH
REOUIREA
MORE
SOPHISTICATEDJ"
MODEL.
THE
DIODE
MOOEL
CAN
BEUSEO
FOR
EITHER
JUNCTION
DIODES
ORSHOTTRY
BARRIER
OIOOES.
THE
JFET
AND
MOSFET
MODELS
ARE
BOTH
BASEDON
THE
FET
MODEL
OFSHICHMAN
AND
HODGES.
...
.....
PROGRAM
IIMITATIONS
400
100
25
200
10
NODES,
INCLUDING
INTERNAL
OEVICE
NOOES.
EACH
NONKRO
OMMICJ"""""
INADEVICE
HILL
GENERATE
ANINTERNAL
NODE.
FOR"AMPLE,ACIRCUIT
JlTM
35USER
SPECIFIEO
NODES
ANO
10BJTS
MITH
NONZERO
BASE
AND
COLLECTOR
RESISTANCES
MILL
CONTAIN
55NOOES.
DEVICES
IBJTS,
OIOOES.
JFETS.
ANO
N3SFETSI.
INDEPENDENTVOLTAGEOR
CURRENT
SOURCES.
ONLY
3INDEPENDENT
SOURCES
CAN
BETIME
OEPENDENT
FORTRANSIENT
ANALYSIS.
TOTAL
ELEMENTS.
INCLUOING
DEVICES
ANOINDEPENDENT
SOURCES.
OUTPUT
VARIABLES.
ANOUTPUT
VARIABLE
ISEITHER
ANOOE
TCNODE
VOLTAGE
n«ACURRENTTHROUGH
ANINDEPENDENT
VOLTAGE
SOURCE.
OUTPUT
VARIABLES
S?Y
BEJSlNTEO
INTABULA^
FORM.
PLOTTED
ASLINE
PRINTER
PLOTS.
ORBOTH.
!5lYIOUTPUT
VARIABLESCAN
BEUSEO
INTHE
ACSMALL
SIGNAL
ANALYSIS.
20SETS
OFMODEL
PARAMETERS
FOR
DEVICES.
V
PAGE
2
TYPES
OF
ANALYSIS
.....
DC
ANALYSIS
THEOCANALYSISPORTIONOFSPICEDETERMINES
THEDCOPERATING
POINTOFTHE
\CIRCUITWITH
INDUCTORS
SHORTEOANDCAPACITORSOPENED.
AOCANALYSISIS
AUTOMATICALLY
PERFORMEO
PRIORTOATRANSIENT
ANALYSIS
TODETERMINE
THETRANSIENT
INITIAL
CONDITIONS.
ANOPRIORTOANAC
SMALL
SIGNALANALYSIS
TODETERMINE
THE
>LINF.ARIfCD,
SMALLSIGNAL
MODELS
FORNONLINEAR
OEVICES.
IFREQUESTED,
THEOC
SMALLSIGNALVALUEOFATRANSFER
FUNCTION(RATIOOFOUTPUTVARIABLETO
INPUT
SOURCEI.
INPUT
RESISTANCE.
ANDOUTPUTRESISTANCE
WILLALSOBECOMPUTEOASAPART
1OF
THE
SMALL
SIGNALOPERATING
POINT.
THE
DC
ANALYSIS
CAN
ALSO
BEUSED
TO
GENERATE
DCTRANSFERCURVES.
ASPECIFIED
INDEPENDENT
VOLTAGEORCURRENT
SOURCE
IS
STEPPEDOVER
AUSED
SPECIFIED
RANGE
ANO
THE
OC
OUTPUT
VARIABLES
ARE
STOREO
>FOREACH
SEQUENTIAL
SOURCEVALUE.
THEOC
ANALYSISOPTIONSARESPECIFIEDONTHE
_.DCCONTROLCARO(PAGE
15).
>.....
ac
SMALLSIGNALANALYSIS
,
THEAC
SNAIL
SIGNAL
PORTIONOFSPICECOMPUTESTHEACOUTPUTVARIABLESASA
)FUNCTIONOFFREQUENCY.
THEPROGRAN
FIRSTCOMPUTES
THE
DCOPERATING
POINT
OFTHE
CIRCUIT
ANODETERMINES
LINEARIZEO,
SHALL
SIGNAL
MOOELS
FOR
ALL
OFTHENONLINFAR
.OEVICES
INTHE
CIRCUIT.
THE
RESULTANT
LINEAR
CIRCUIT
ISTHEN
ANALYZEDOVER
AI
USERSPECIFIEORANGEOFFREQUENCIES.
THEOESIREDOUTPUTOFANAC
SMALL
SIGNAL
ANALYSISISUSUALLYATRANSFERFUNCTION(VOLTAGEGAIN.TRANSIMPEDANCE,
ETCI.
IF
THECIRCUITHASONLYONEAC
INPUT,
ITISCONVENIENTTOSETTHAT
INPUTTOUNITY
IANO
ZEROPHASE.
SO
THATOUTPUT
VARIABLES
HAVE
THE
SAME
VALUE
AS
THE
TRANSFER
FUNCTION
OFTHE
OUTPUT
VARIABLE
WITH
RESPECTTOTHE
INPUT.
...
)THEGENERATIONOFWHITE
NOISE
BYRESISTORSANOSEMICONDUCTOR
OEVICESCAN
ALSOBESIMULATEDWITHTHEAC
SMALL
SIGNAL
PORTION
OF
SPICE.
EQUIVALENT
NOISE
SOURCE
VALUES
AREDETERMINED
AUTOMATICALLY
FROMTHESMALL
SIGNAL
OPERATING
POINT
IOFTHECIRCUIT,AND
THECONTRIBUTIONOFEACHNOISESOURCE
ISADOEOATAGIVEN
SUMMINGPOINT.
THETOTALOUTPUTNOISELEVELANDTHEEQUIVALENTIN»UTNOISE
LEVEL
ARE
DETERMINEDATEACHFREOUENCV
POINT.
THE
OUTPUT
ANO
INPUT
NOISE
LEVELS
IARENORMALIZEDWITHRESPECT
TOTHE
SQUARE
ROOTOFTHENOISE
BANDWIDTHANDHAVE
THEUNITS
VOLTS/RT
HZORAMPS/AT
HZ.
THEOUTPUT
NOISE
ANOEQUIVALENT
INPUT
NOISECANBEPRINTEOORPLOTTEOINTHESAME
FASHIONASOTHER
OUTPUT
VARIABLES.
THEFREQUENCYRANGEANDTHENOISEANALYSIS
OPTIONSARESPECIFIEOONTHE
•ACCONTROL
CARO
fPAGE
151.
)——
TRANSIENT
ANALYSIS
ITHETRANSIENT
ANALYSISPORTIONOFSPICECOMPUTESTHETRANSIENTOUTPUT
VARIABLES
ASAFUNCTION
OFTIMEOVERAUSERSPECIFIED
TIME
INTERVAL.
THE
INITIALCONDITIONS
ARE
AUTOMATICALLY
DETERMINED
BYAOCANALYSIS.
ALL
SOURCES
WHICHARENOT
TIME
DEPENDENT
IFOR
EXAMPLE,
POWERSUPPLIESIARESETTOTHEIROC
VALUE.
FORLARGESIGNAL
SINUSOIDALSIMULATIONS,
AFOURIERANALYSISOFTHE
OUTPUTWAVEFORMCANBESPECIFIEOTOOBTAINTHEFREOUENCVDOMAINFOURIER
COEFFICIENTS.
THE
TRANSIENT
TIME
INTERVAL
ANOTHEFOURIER
ANALYSIS
OPTIONS
ARE
SPECIFIED
ON
THE
.TRAN
CONTROL
CARO
IPAGE
161.
V
PAGE
3
.....
ANALYSIS
AT
OIF'ERENT
TEMPERATURES
ALL
INPUTDATAFORSPICEISASSUMEDTOHAVEBEENMEASUREO
AT2TDEGC
ISOO
DFGRl.
THESIMULATIONALSOASSUMES
ANOMINALTENPERATURE
OF2TOEGC.
THECIRCUITCANBESIMULATEDATUPTOSDIFFERENT
TEMPERATURES
BYUSINGA.TEMP
CONTROL
CARO
IPAGE
151.
TEMPERATURE
APPEARS
EXPLICITLY
INTHEEXPONENTIALTERMSOFTHEBJTAND
OIODE
MODEL
EQUATIONS.
INADOITION*
SATURATION
CURRENTS
HAVE
ARUILT-IN
TEMPERATURE
DEPENDENCE.
THE
TEMPERATURE
DEPENDENCE
OFTHE
SATURATION
CURRENT
IN
THE
BJT
MOOELS
IS
DETERMINED
BY!
ISITEMPI•
10•
<TEHP*»3>
•EXP1-0•EG/
IR•TEMPI).
NHERER
ISB0LT2NANSCONSTANT.0
ISTHEELECTRONIC
CHARGE,
10IS*A
CONSTANT.
ANO
EG
ISTHE
ENERGY
GAPWHICH
ISAMODEL
PARAHETER.
THE
TEMPERATURE
DEPENDENCE
OF
THESATURATIONCURRENT
INTHEJUNCTION
OIODE
MODEL
ISDETERMINED,BVt
IS
ITENPI
•10•
ITEHP»*I3/NII
•EXPf-0•
EG/IR•
TENPII,
WHEREN
ISTHEEMISSION
COEFFICIENT.
WHICH
ISA
NOOEL
PARAMETER,
ANOTHEOTHER
SYMBOLSHAVE
THE
SAME
MEANING
ASABOVE.
FOR
SHOTTRV
BARRIER
OIOOES,
THE
TEMPERATURE
DEPENDENCEOFTHESATURATIONCURRENT
ISDETERMINED
BVt
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CONVERGENCE
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NHICM
ISTERMINATED
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THE
NODE
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ISLARGER.
ALTHOUGH
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USED
ISSPICEHAS
BEEN
FOUND
TOBE
VERY
RELIABLE,
INSOME
CASES
ITWILL
FAIL
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WHEN
THIS
HAPPENS,
THE
PROGRAM
WILL
OUT
THE
LAST
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VOLTAGES
ANOTERHINATE
THE
JOB.
THE
NOOE
VOLTAGES
THAT
ARE
PRINTED
ARE
NOT
NECESSARILY
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SOLUTION.
FAILURETOCONVERGE
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ISUSUALLY
OUETOANERRORIN
SPECIFYING
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ELEMENT
VALUES,
ORMODEL
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VALUES.
REGENERATIVE
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WITH
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PROBABLY
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FAILURE
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ANALYSIS
CANALSO
BEDUE
TOATIME
STEP
WHICH
ISTOO
LARGE.
SPICE
PRESENTLY
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NOT
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TIME
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CONTROL,
ANDSIGNIFICANT
ERROR
AND/OR
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CAN
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IFTHE
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V
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OS
•••••
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GENERAL
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RXXXXXX
Nl
N2
VALUE
CXXXXXX
Nl
N2
VALUE
LXXXXXX
Nl
N2
VALUE
RI3
12
IT
IR
CGOOD
13
010P
LLINKS
42
69
1U
PA
GE
9
NlANON2ARETHETWO
ELEMENTNOOES.
THEOROEROFTHE
NODESFORTHESE
ELEMENTStSUNIMPORTANT.
VALUE
ISTHE
RESISTANCElOHMSI.THECAPACITANCE
(FARADSN
ANOTHEINDUCTANCE
IHENRtES).
RESPECTIVELY....
THIS.VALUE
CANNOT
BE
NEGATIVE
OR
ZERO.
"•^•
•V-v
bLT
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ON
TR
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bC
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RE
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AY
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IGN
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20
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3.0NS
THE
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VMUST
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FIELD
FOLLOWING
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N*
AND
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ARETHE
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AND
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RESPECTIVELY.
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NO
AND
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VALUE
ISTHE
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...
INTHEACANALYSISTHETRANSCONDUCTANCE
CAN
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ILINEAR
PHASEIOPERATOR.
THEOELAY
fSECONDSI
ISAPPENOEO
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THECOMPLEX.
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OF
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l-J
♦6.28318
*FREO
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•
THEOELAY
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PAGE
6
•»•••
INDEPENDENT
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VXXXXXX
N»
N-
OC
OCVAL
AC
ACVAL
PHASE
IXXXXXX
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N-
DC
DCVAL
AC
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IZENER
13
15
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IS
2OC
0.001
AC
1UN
21
23
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0.33345.0
VNEAS
12
9
'VIS
THEPOSITIVE
NOOE
ANON-ISTHENEGATIVE*NODE."""NOTE"THATVOLTAGE
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NEED
NOT
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NEGATIVE
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OCVAL
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VALUE
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THE
SOURCE
IS
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ANALYSIS
AND,
IFNO
TIME
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ISATTACHED.
IN
THE
TRANSIENT
ANALYSIS._
IF
THE
DC
SOURCE
VALUE
IS
ZERO,
THE
LETTERS
OC
ANO
THE
DC
VALUE
CAN
BE
OMITTED.
>ACVAL
ISTHE
ACVALUE
ANDPHASE
ISTHE
ACPHASE.
THE
SOURCE
ISSETTOTHIS
VALUE
IS
THE
AC
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THE
ARBITRARY
PHASE
FACTOR
CAN
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OMITTED.
IF
THE
SOURCE
IS
NOT
AN
AC
SMALL
SIGNAL
INPUT.
THE
LETTERS
AC
AND
THE
AC
VALUES
ARE
..OMITTED..
__
......
ASOURCE
MAY
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FOR
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BY
APPENDING
ONE
OF
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FUNCTIONS!
PULSE,
EXPONENTIAL,
ANO
SINUSOIDAL.
IF
PARAMETERS
OTHER
THAN
SOURCE
VALUES
ARE
OMITTEO
OR
SET
TO
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THE
DEFAULT
VALUES
SHOWN
WILL
BE
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TSTEP
IS
THE
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INCREMENT
ITINE
STEPI.
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TSTOP
IS
THE
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tPAGE
151.
1.
PULSE
PULSE
V
EXAMPLE
VIN
30
PULSE
-
PARAMETERS
ANO.DEFAULT.VALUES
..
VI
INITIAL
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PULSED
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...
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TR
RISE
TIME
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TF
FALL
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PN
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VALUE
__
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TO
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30NS
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THESE
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0.1
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IONS
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PAGE
B
•*»»•
BIPOLAR
JUNCTIONTRANSISTORS
GENERAL
FORM
OXXXXXXNCNBNENNAME
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i
EXA«F1E
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2.0
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|NC
ISTHE
COLLECTOR
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BASE
NOOE.
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THEFITTER
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AREA
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ISEQUIVALENT
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AREA
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FACTOR
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..
_....—
.
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JUNCTION
OtOOES
j
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I
EXAMPLE
OBRIOGEB
10OIOOEI...
L.
-•
V|
N»IS
THE
POSITIVE
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N-IS
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NNANE
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MODEL
NAME
jIPAGE91,
ANO
AREA
ISTHE
AREA
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BJTS,
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]•••••
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JXXXXXX
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91,
AND
AREA
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IPAGE
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AREA
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AREA
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BJTS,
ABOVEI.
PAGE
9
•••••
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EXAMPLE!
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PAGE
31.
NAME
PARAMETER
RS
OHMICRESISTANCE
TT
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SATURATIONCURRENT
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PAGE 11
PARAMETER DEFAULT TYPICAL
SAT CURRENT/I0EAL B-E SAT CURRENT 100 100SAT CURRENT/IOEAL B-C SAT CURRENT 1 0.1BASE OM*!C RESISTANCE ... 0 100COLLECTOR OHMIC RESISTANCE 0 10EMITTER OHMIC RESISTANCE 0 1COLLECTOR-SUBSTRATE CAPACITANCE 0 2PFFORWARO TRANSIT TIME 0 0.1NSREVERSE TRANSIT TIME 0 IONSZERO BIAS B-E JUNCTION CAPACITANCE .0 2PFZERO BIAS B-C JUNCTION CAPACITANCE 0 IPFSATURATION CURRENT l.OE-14 l.OE-14FORWARO EARLY VOLTAGE INFINITE 50REVERSE EARLY VOLTAGE INFINITE 50NONIOEAL B-E SAT CURRENT/SAT CURRENT 0 1000FORWARO RNEE CURRENT . ._ . INFINITE 10MAB-E EMISSION COEFFICIENT 2*0 1.5NONIOEAL B-C SAT CURRENT/SAT CURRENT 0 1.0REVERSE RNEE CURRENT INFINITE 100NAB-C EMISSION COEFFICIENT 2*0 1*5B-E JUNCTION POTENTIAL 1.0 O.TB-E GRADING COEFFICIENT 0.9 0.33 ...B-C JUNCTION POTENTIAL 1-0 0.5B-C GRAOING COEFFICIENT 0.5 0.33ENERGY GAP l.H 1-" ™ J«
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--~«_JFET N00ELS..I00TH N ANO P CHANNEL! ... ._.
THE JFET NOOEL IS OERIVEO FRON THE FET NODEL OF SHICHMAN AND HODGES. THEOC CHARACTERISTICS ARE OEFINEO BY THE PARAMETERS VTO AND BETA. WHICH DETERMINETHE VARIATION OF ORAIN CURRENT WITH GATE VOLTAGE. LAMBDA. WHICH DETERMINES THEOUTPUT CONDUCTANCE. AND IS. THE SATURATION CURRENT OF THE TWO GATE mmmtkmttm ..JUNCTIONS. TWO OHMIC RESISTANCES. RO AND RS. ARE INCLUDEO. CHARGE STORAGE IS
" MODELEO BY NONLINEAR DEPLETION LAYER CAPACITANCES FOR BOTH GATE JUNCTIONS WHICHVARY AS THE -1/2 POWER OF JUNCTION VOLTAGE AND ARE OEFINEO BY THE PARANETERSCOS, CGO. ANO PB.
NAME PARAMETER
VTO THRESHOLD VOLTAGEBETA TRANSCONDUCTANCE PARAMETERLAMBDA CHANNEL LENGTH MODULATION PARAMETERRD DRAIN OHMIC RESISTANCERS SOURCE OHMIC RESISTANCECGS ZERO BIAS G-S JUNCTION CAPACITANCECGO ZERO BIAS G-0 JUNCTION CAPACITANCEPB GATE JUNCTION POTENTIALIS GATE JUNCTION SATURATION CURRENT
DEFAULT TYPICAL
-2.01.0E-4
0
0
0
0
0
1l.OE-14
-2.0
l.OE-31.0E-4
100
1005PF
" IPF0.6
l.OE-14
V
PAGE
12
NOSFET
NOOELS
IBOTHN
ANDPCHANNELS!
THE
NOSFET
MOOEL
ISALSO
DERIVED
FROM
THEFETNOOEL
OFSHICHMAN
AND
HODGES?
Ttt
DCCHiRic?iRIS?ICS
OFTHE
NOSFET
AREOEFINEO
BYTHE"j***™*.
yf«mm
ami)
ii.nni.WHICH
ARE
IDENTICALTO
THE
PARAMETERS
FOR
THE
JFET*
PHI_
VOLTAGE,
AND
IS,
THE
SATURATION
CURRENT
OFTHETWOfUBJTRATE
JUNCTIONS.
CHARGE
STORAGE
ISMOOELED
BYTHREE
CONSTANT
CAPACITORS,
CCS,
CGD,
ANO
CGB.
AND
inMiiNFAR
DEPLETIONLAYERCAPACITANCES
FOR
BOTH
SUBSTRATE
JUNCTIONSWHICH
VARY
ISTM?
-1/S
PO«R^F
JInJtiSn
VOLTAGE
AND
AREDETERMINED
BYTHE
PARAMETERS
CBO,
CBS,
ANO
PB.
NAME
PARAMETER
VTO
THRESHOLO
VOLTAGE
PHI
SURFACE
POTENTIAL
BETA
TRANSCONOUCTANCE
PARAMETER.
m".
GAMMA
BUIRTHRESHOLO
PARAMETER
LAMBDA
CHANNEL
LENGTH
MODULATION
PARAMETER
'RD
DRAINOHMICRESISTANCE
RS
SOURCE
OHMICRESISTANCE
CGS
GATE-SOURCECAPACITANCE
CGO
GATE-DRAINCAPACITANCE
;.
"""CGB
GATE-BULRCAPACITANCE
CBO
ZERO
BIAS
8-0
JUNCTION
CAPACITANCE
CBS
ZERO
BIAS
B-S
JUNCTION
CAPACITANCE
PB
BULKJUNCTIONPOTENTIAL
ISBULK
JUNCTION
SATURATION
CURRENT
DEFAULT
TYPICAL
2.0
0.9
l.OE-4
0 0 0 0 0 0..
b'
0 0 1l.OE-14
2.0
O.T
l.OE-6
1.0
0.1
100
100
O.OIPF
0.01PF
..O.OIPF
O.OIPF
O.OIPF
O.T
l.OE-14
V
PAGE
13
CONTROL
CAROS
*»••»
TITLE
CARD
'EXANPLE
"OP
AMP"
CIRCUIT
JOEJSTUOENT
EECS
241
THIS
CARO
MUST
BETHE
FIRSTCARO
INTHE
INPUT
OECR.
ITSCONTENTS
ARE
PRINTED
VERBATIM
ASTHEHEADINGFOREACHSECTIONOFOUTPUT.
•••••
.ENDCARO
GENERAL
FORM
.END
THIS
CARO
NUST
ALWAYS
BETHE
LAST
CARO
INTHE
INPUT
OECR.
NOTE
THAT
THE
PERIOD
ISANINTEGRAL
PART
OFTHE
NAME.
IFTHE
.END
CARD
ISOMITTEO.
THE
NEXT
JOBWILL
BEREADINASPART
OFTHE
JOB
NtSSINGTHE.ENDCARO.
ANO
NEITHER
JOB
WILL
BERUN
SUCCESSFULLY.
'
••*••
COMMENTCARO
"GENERAL
"FORM
"•'ANY"COMMENTS
""
EXANPLE
•RF'IR
GAINSHOULDBE100
THIS
CARO
ISPRINTEO
OUT
INTHEINPUTLISTINGBUT
ISOTHERWISE
IGNORED.
•«**•
NO
PRINTCARO
GENERAL
FORM
.NP
THIS
CARO
SUPPRESSES
THE
SUMMARYOFINPUTOATA
THAT
ISNORMALLY
PRINTEO
AFTER
REAOINC
THE
INPUT
OECR.
ITDOES
NOT
SUPPRESS"THELISTING
OFTHE
INPUT
OECROR
ANYERROR
MESSAGES
THAT
NAY
OCCUR.
••*•*
.TEMPCARO
GENERAL
FORN
.TENPTEl
TE2
EXANPLE
•TENP-99.0
29.0
129.0
THIS
CARO
SPECIFIES
THETEMPERATURES
ATWHICHTHE
CIRCUIT
ISTOBE
SINULATEO.
TEl.
TE2.
...
ARE
THE
DIFFERENT
TEMPERATURES,
INDEGREES
C.A
MAXIMUM
OFFIVE
TEMPERATURES
ARE
ALLOWED.
TEMPERATURES
LESS
THAN
-223.0
DEG
CARE
IGNORED.
\
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-/*
PAGE
14
•*••»
#qVPVT
CARO
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NODE
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NAME
MUST
BEGINWITH
ANI.
AND
VYYYYYV
irini6MMrOFC?S"7ND??E!;DlST
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SOURCE
THAT
THECURRENT
ISFLOWING
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ham
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In5EQUIVALENT
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ORFLOTTEOAS"J*"J"™
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THE
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0*.
vimnu^UT
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BYSPECIFYING
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THE
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APPLYONLY
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OPTION
THAT
THEY
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EXAMPLE
.OUTPUTV12
120
PLOT
MAPH
-20
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03
INTHIS
EXAMPLE,
THE
PROGRAMWILL
DETERMINE
LIMITS
FORTHE
"{6NITUDE
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BUTWUL
PLOT
THE
PHASE
BETWEEN-20
DEGREES
ANO
30DEGREES,
ANDWILL
PLOT
THE
TRANSIENT
RESPONSE
BETWEEN0VOLTS
AND5VOLTS.
PAGE
13
•••••
.DCCARO
GENERAL
FORM
.OCOPOUTPUT
INPUT
TCELNAME
VSTART
VSTOP
VINCR
EXANPLES
.DC
OP
•DC
TC
VIN
09
0.9
•OC
OP
VOUT
VIN
TC
VIN
09
0.9
FORTHE
SMALL
SIGNAL
TRANSFER
FUNCTION,
OUTPUT
tSTHE
OUTPUT
VARIABLE
AND
INPUT
ISTHE
INPUT
SOURCE.
THE
PROGRAM
WILL
COMPUTE
THE
DCSMALL
SIGNAL
VALUE
OFTHE
TRANSFER
FUNCTION
IOUTPUT/INPUT),
INPUT
IMPEDANCE,
AND
OUTPUT
IMPEDANCE.
IFTHE
TRANSFER
FUNCTION
VALUE
ISNOT
DESIREO.
OMIT
THE
OUTPUT
AND
INPUT
SPECIFICATIONS.
IFTHE
DCOPERATING
POINT
ISNOT
OESIRED.
OMIT
THE
LETTERS
OP.
HOWEVER.
AOCOPERATING
POINT
WILL
ALWAYS
BECOMPUTEO
PRIORTOANAC
SMALL
SIGNAL
ANALYSISORATRANSIENT
ANALYSIS.
FORTRANSFER
CURVES.
ELNAME
ISTHE
NAME
OFTHE
VARIABLE
SOURCE.
VSTART
ISTHE
STARTING
SOURCE
VALUE.
VSTOP
ISTHEFINAL
SOURCE
VALUE.
AND
VINCR
ISTHE
INCREMENT.
THE
TOTAL
NUNBEA
OFPOINTS
TO
BECOMPUTED
CANNOT
EXCEEO
101.
IFA
TRANSFER
CURVE
ISNOT
OESIRED.
ONIT
THE
LETTERSTCANO
THETRANSFER
CURVE
PARAMETERS.
••"•
"••
"*.»
CCA
RD**
"
GE
NE
RA
LF
OR
M
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•ACOECNOFSTARTFSTO*NOISEOUTPUTINPUTNUNS
•ACOCTNOFSTARTFSTOPNOISEOUTPUT
INPUT
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.ACOEC
10
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1100KHZNOISE
VOUT
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10
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10
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NOISE
VOUT
V21
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STANDS
FOR
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VARIATION,
ANO
NOIS
THE
NUMBER
OFPOINTS
PER
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OCT
STANOS
FOROCTAVE
VARIATION,
AND
NOIS
THE
NUNBEA
OFPOINTS
PER
.OCTAVE.
LIN
STANDS
FOR
LINEAR,
AND
HPIS
THE
NUMBER
OFPOINTS.
FSTART
tSTHE
STARTING
FREOUENCV,
AND
FSTOP
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FINAL
FREQUENCY.
THE
TOTAL
NUMBER
OFFREQUENCY
POINTSTOBECOMPUTEDCANNOTEXCEED101.
FORNOISE
ANALYSIS,
OUTPUT
ISTHE
NAME
OFAVOLTAGEOUTPUT
VARIABLE.
THIS
OUTPUT.
WHICH
MUST
BEAVOLTAGE.
WILL
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pOINT.
INPUT
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NANE
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INDEPENDENT
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THE
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NOISE
ISOIVIOEO
BYTHE
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fOUTPUT/INPUTI
TOOBTAIN
THE
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INPUT
NOISE
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NUNS
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ATEVERY
NUNS
FREOUENCV
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PRINTOUT
WILL
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FOR
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PRINTOUT,
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SHOULD
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LARGE
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IFTHE
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THE
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NOISE
AND
THE
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ANALYSIS
SPECIFICATIONS.
P'
\
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*'
PAGE
16
•••#•
.TRANCARO
GENERAL
FORN
.TRANTSTEPTSTOPTSTART
FOUR
OUTPUT
FREO
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.....
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INSlOOONSBOONS
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BEGINS
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»|
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hero,
tstarti,
the
circuit
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steady
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but
,,
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mitoiirt
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THECIRCUITIS
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1001.AND
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.|
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»FOR
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TOAVOID
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ITMAY
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