COMP541
Combinational Logic - I
Montek Singh
Mon, Jan 12, 2015
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Today Basics of digital logic (review)
Basic gatesCombinational logicVarious representations
Boolean algebraTruth tablesKarnaugh Maps (“K-Maps”)Circuit schematic diagramsHardware Description Languages (HDL)
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Binary Logic Binary variables
Can be 0 or 1 (True or False, low or high)Variables named with single letters in examples
Really use words when designing circuits
Logic Gates Perform logic functions:
inversion (NOT), AND, OR, NAND, NOR, etc. Single-input:
NOT gatebuffer (non-inverting)
Two-input: AND, OR, XOR, NAND, NOR, XNOR
Multiple-inputMost 2-input gates also have multi-input flavors
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Single-Input Logic Gates
NOT
Y = A
A Y0 11 0
A Y
BUF
Y = A
A Y0 01 1
A Y
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Two-Input Logic Gates
AND
Y = AB
A B Y0 0 00 1 01 0 01 1 1
AB
Y
OR
Y = A + B
A B Y0 0 00 1 11 0 11 1 1
AB
Y
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More Two-Input Logic Gates
XNOR
Y = A + B
A B Y0 00 11 01 1
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0 00 1 11 0 11 1 0
A B Y0 0 10 1 11 0 11 1 0
A B Y0 0 10 1 01 0 01 1 0
AB
Y AB
Y AB
Y
1001
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More Two-Input Logic Gates
XNOR
Y = A + B
A B Y0 00 11 01 1
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0 00 1 11 0 11 1 0
A B Y0 0 10 1 11 0 11 1 0
A B Y0 0 10 1 01 0 01 1 0
AB
Y AB
Y AB
Y
1001
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Multiple-Input Logic Gates
NOR3
Y = A+B+C
B C Y0 00 11 01 1
AB YC
A0000
0 00 11 01 1
1111
10000000
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Multiple-Input Logic Gates
NOR3
Y = A+B+C
B C Y0 00 11 01 1
AB YC
A0000
0 00 11 01 1
1111
10000000
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NAND is Universal Can express any Boolean Function
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Using NAND as Invert-OR
Also reverse inverter diagram for clarity
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DeMorgan’s Law:
NOR Also Universal Dual of NAND: also can express any Boolean
func
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Representation: Schematic “Schematic” is short for “schematic diagram”
Simply means a drawing showing gates (or more complex modules) and wire connections
More complex modules are usually shown as black boxes
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Representation: Boolean Algebra More on this next class
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ZY X F
Representation: Truth Table 2n rows: where n is # of variables
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Schematic Diagrams Can you design a Pentium or a graphics chip
that way?Well, yes, but diagrams are overly complex and hard
to enter These days people represent the same thing
with textYou can call it “code,” but it is not software!More precisely, it is a textual “description”
Hardware Description Languages Main ones are Verilog and VHDL
Others: Abel, SystemC, Handel Origins as testing languages
To generate sets of input values Levels of use from very detailed to more
abstract descriptions of hardware
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Design w/ HDL Two leading HDLs:
Verilogdeveloped in 1984 by Gateway Design Automationbecame an IEEE standard (1364) in 1995
VHDLDeveloped in 1981 by the Department of DefenseBecame an IEEE standard (1076) in 1987
Most (all?) commercial designs built using HDLs
We will use Verilog
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Uses of HDL Simulation
Defines input values applied to the circuitOutputs checked for correctnessMillions of dollars saved by debugging in simulation
instead of hardware Synthesis
Transforms HDL code into a circuit-level implementationHDL is transformed into a “netlist”“Netlist” = a list of gates and the wires connecting them
– Just a textual description instead of drawing
IMPORTANT:When describing circuits using an HDL, it is critical to
think of the hardware the code should produce.20
Verilog Module Code always organized in modules Represent a logic “box”
With inputs and outputs
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ab yc
VerilogModule
Examplemodule example(input a, b, c, output y); *** HDL DESCRIPTION HERE ***endmodule
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ab yc
VerilogModule
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Levels of VerilogSeveral different levels (or “views”)
Mainly two types: Structural or BehavioralStructural: Describe the physical structure of the
hardwareTypically, gates/modules and wires that connect them
Behavioral: Describes the algorithmic behavior of the hardwareE.g., Output X = Y + Z
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Example 1 Output is 1 when input < 011
Figure (b) is called a “Karnaugh Map” (or “K-Map”)graphical representation of truth table: n-dimensional
“cube”Figure (c) is a “sum-of-products” implementation
AND-OR, implemented as NAND-NAND
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Structural Verilog Explicit description of gates and connections
Textual form of schematicSpecifying netlist
netlist = gates/modules and their wire connections
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Example 1 in Structural Verilogmodule example_1(X,Y,Z,F); input X; input Y; input Z; output F;
//wire X_n, Y_n, Z_n, f1, f2;not
g0(X_n, X),g1(Y_n, Y),g2(Z_n, Z);
nandg3(f1, X_n, Y_n),g4(f2, X_n, Z_n),g5(F, f1, f2);
endmodule
Can also be: input X, Y, Z; output F;
Newer syntax: module example_1( input X, input Y, input Z, output F );
Slight Variation – Gates not named
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module example_1_c(X,Y,Z,F); input X; input Y; input Z; output F;
not(X_n, X);not(Y_n, Y);not(Z_n, Z);
nand(f1, X_n, Y_n);nand(f2, X_n, Z_n);nand(F, f1, f2);
endmodule
Observe:• each gate is declared using a separate
“not” or “nand” declaration• gate instances are not named
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Explanation Each of these gates is an instance
Like object vs class In first example, they had names
not g0(X_n, X), In second example, no name
not(X_n, X); Why can naming an instance be useful?
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Gates Standard set of gates available
and, or, notnand, norxor, xnorbuf
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Dataflow Description (Behavioral)
Basically a logical expression
No explicit gates
module example_1_b(X,Y,Z,F); input X; input Y; input Z; output F;
assign F = (~X & ~Y) | (~X & ~Z);
endmodule
Conditional Expressions Useful for:
describing multiplexerscombinational logic in an if-then-else style
module example_1_c(input [2:0] A,output F);
assign F = (A > 3’b011) ? 0 : 1;
endmodule
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Noticealternatespecification
Abstraction Using the digital abstraction we have been
thinking of the inputs and outputs asTrue or False1 or 0
What are they really?
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Logic Levels Define discrete voltages to represent 1 and 0 For example, we could define:
0 to be ground or 0 volts1 to be VDD or 5 volts
What about 4.99 volts? Is that a 0 or a 1? What about 3.2 volts?
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Logic Levels Define a range of voltages to represent 1 and
0 Define different ranges for outputs and inputs
to allow for noise in the system What is noise?
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What is Noise? Anything that degrades the signal
E.g., resistance, power supply noise, coupling to neighboring wires, etc.
Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts
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Driver ReceiverNoise
5 V 4.5 V
The Static Discipline Given logically valid inputs, every circuit
element must produce logically valid outputs
Discipline ourselves to use limited ranges of voltages to represent discrete values
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Logic Levels
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NMH = VOH – VIH
NML = VIL – VOL
DC Transfer Characteristics
VDD
V(A)
V(Y)
VOH VDD
VOL
VIL, VIH
0
A Y
VDD
V(A)
V(Y)
VOH
VDD
VOL
VIL VIH
Unity GainPoints
Slope = 1
0VDD / 2
Ideal Buffer: Real Buffer:
NMH = NML = VDD/2 NMH , NML < VDD/2
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(See textbook for characteristics of an inverter)
VDD Scaling Chips in the 1970s and 1980s were designed
using VDD = 5 V As technology improved, VDD dropped
Avoid frying tiny transistorsSave power
3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …
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Logic Family Examples
Logic Family VDD VIL VIH VOL VOH
TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4
CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84
LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4
LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7
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Next Class Boolean Algebra Synthesis of combinational logic
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