Start of CSCs installation
The installation of cathode strip chambers started in June 2003
Installation of the first chamber on an iron disk.
The chambers were installed layer by layer and then were cabled.
CSC’s Readout Electronics
CSC
CFEBCFEBCFEB CFEB
ALCT1 of 24
CFEB
1 of 2
LVDB
LVDB
AFEB
CFEB
ALCT
MPC
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
CCB
VME
CONTROLLER
Peripheral C
rates
(on iron disks)
DCS
TTC Crate
Track Finder Crate Readout Data
FED
Crates
(in US
C55)
in USC55
TMB-RAT
DMBCCB
MPC DDU DCC
1 of 5
1 of 5
Time diagram of CSC installation and commissioning
0
100
200
300
400
Time
Num
ber o
f cha
mbe
rs Installed
Cabled
Commissioned
With problems
MTCCPC commissioning on + side
CHAMBER CABLES EXTENSION CABLES
(1 )
PORTABLE RACK
(2 )( 3 )
(4 )
(VME & LV POWER}
HV GAS DAQ PC
1
2
34
5
6
AC POWER
Portable set-up for CSC commissioning
4 – AFEB analog noise & threshold
2 – Anode connectivity
5 – SCA noise
3 – Cathode connectivity
1. Slow Control V/I
6 – Comparator noise
7 – Comparator logic 8 – Chamber noise at nominal HV
List of CSC Tests
It takes usually 4-6 hours to test one chamber in perfect conditionsIt can take a number of days to find a problem, eliminate it and retest the chamber in question
Skew-clear cable revision problem
Skew clear cable data transfer at 280 MHz
0
20
40
60
80
100
120
0 5 10 15 20 25
Cable length in meters
Dat
a tr
ansf
er
with
out
erro
rs Rev A,B
Rev C,D
1. It was found that we have two type of skew clear cables: Production Revisions A and B - have delay 4.7 ns/meter Production Revisions C and D – have delay 5.2 ns/meter
2. They differ in terms of data transfer capability:
Chamber noise problem
360 Hz 590 Hz
• Each 15-20th installed chamber needs training either at 3.8 kV or with reverse HV at 3.3-3.4 kV.
• Training of chambers with reverse HV polarity helped in most cases.
•Two chambers had to be replaced because the training didn’t help
ME+2/2/17-039 ME+4/1/06-005
Noisy channels
Unexpected cross-talks
ME-3/2/08-145
ME+3/2/18-075
Test pulse was sent to the test strip of the plane #3
Test pulse was sent to the test strip of the plane #4
AFEB problems
1 ME+3/2/15-051 AFEB#21 Flaky behavior of ch #53 pl #5
2 ME-3/2/12-110 AFEB#7 Dead channel #17 in plane #2
3 ME+2/2/30-130 AFEB#12 Dead channel h#29 in plane #6
4 ME+3/1/11-017 AFEB#27 Dead channel #65 in plane #5
5 ME+2/2/26-070 AFEB#19 Dead channels #49-50 in plane #2
6 ME+3/1/03-026 AFEB#23 Dead channel #61 in plane #4
7 ME+2/1/06-018 AFEB#7 Dead channel #21 in plane #2
8 ME-4/1/15-021 AFEB#14 Channel 33 in plane 3 showed efficiency 55%
9 ME-4/1/12-035 AFEB#12 Channel #28 in plane 5 showed efficiency 60%
10 ME+3/1/12-028 AFEB#15 Dead channel #27 in plane #6
Test pulse was sent
to the test strip of plane #2
• 2 AFEB were replaced (one needs threshold < 0, second one had large crosstalk
• ME-1/2/16 – two wire groups in the plane #6 have a short
• ME-2/1/09 – one AFEB shows unstable behavior (2-9 channels cab be dead)
Slice test CSC
Three types of CSC electronics noise observed
RMS of SCA pedestals RMS of SCA pedestals AFEB threshold noise
Mostly seen in planes 3, 4, 5 Mostly seen in planes 1, 2, 6 So far seen in planes 1, 3, 5
Possible source of CFEB noise
Our LV power supplies can be a source of the CFEB noise. LV cable jackets connected to a crate with LV power supplies causes CFEB noise in some chambers.
There are 3 types of chambers:
• Good
•Acceptable
•Noisy
CFEB noise of ME+2/2/28
MTCC, DQM results for Global run 2599 CSC commissioning set-up, Sep 08
Our set-up sees less CFEB noise level
Summary of replacements
• 5 boards had mechanical damages:– LVDB – broken input connector– LVMB – broken switch– ALCT – broken input connector– CFEB – broken latch, input connectors
• 20 CFEBs were replaced:a. 14 CFEBs – dead channels, low response to the test pulse, no comparators, no data, … b. 6 CFEBs - by mistakes
• 5 LVMB – read wrong currents
• 5 ALCT: a. four boards had 1.8 V fuse burnt outb. one board couldn’t been readout
• 9 cables: a. one DMB-LVDB was damaged b. eight skew clear cables
• 4 CSCs: a. two chambers couldn’t hold HV > 2.7 kVb. two chambers had unacceptable level of noise
Summary table of known problems
Disc Installed Commissioned Problems Plane Cross-talk
AFEB
Cable probl
LVBD-LVMB
AFEB ch dead,
short
CFEB Noise
YE-1 36 36 1 1
YE-2 108 108 13 1 1 8 2 1
YE-3 18 18 1 1
YE+1 72 72
YE+2 108 108 15 1 4 9 1
YE+3 18 18 1 1
- Must be repaired
- Can be fix, but needs board replacement or taking a chamber down
- Can be ignored
Boards in Peripheral Crate (PC)
MPC
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
DMB
TMB
CCB
CONTROLLER
Data acquisition Motherboard (DMB)
VME Crate Controller
(VCC)
Trigger Motherboard (TMB) and RPC-ALCT Transition module (RAT)
Muon Port Card (MPC)
Clock & Control Board (CCB)
60 Peripheral Crates for CSC’s in Total.
Lists of new boards and tests
1. Crate Controller - 1
2. CCB - 1
3. MPC - 1
4. DMB - 9
5. TMB - 9
6. RAT - 9
7. PCRB -1
8. MPCB - 1
9. Back plane - 1
1. Timing of ALCT Rx and Tx
2. Timing of CFEB Rx
3. Wire scan
4. Strip comparator scan
5. TMB test
6. DMB test
7. TMB-MPC test
8. TMB-RAT self test
FAST site tests (calibration)
Peripheral crate commissioning report
1. There was not comparator data from CFEB #2 of ME+1/2/35 chamber.
2. The low voltage control cable on ME+1/2/36 chambers didn’t work.
3. The ALCT fuse on 1.8 V power line of ME-4/1/11 burnt out.
4. Two CFEB-DMB skew-clear cables were swept.
PC commissioning summary
• 62 PC have been assembled and tested in ISR before shipping to SX5 for final installation
• 38 PC have been installed filled up with electronics and cabled
• 24 PC passed through the first stage of the commissioning
• The first stage of installed PC commissioning on minus side has started (3 PC have been commissioned).
User Interface http://cmsdoc.cern.ch/CSC/TESTB/
Instructions
Traveller
Summary Table
AFEB Thresholds
Test-B Database
Our plans for 2006-2007
1. Commissioning of 36 ME-1/3 chambers which are going to be installed in November-December 2006.
2. Fix the problems on as many CSCs as possible before they go down the shaft.
3. Installed most of the Peripheral Crates, fill them up with electronics, and hook up skew clear cables.
4. Finish first stage of Peripheral Crate commissioning before disks are moved down the shaft.
5. Redesign set-up for PC commissioning (add FED crate and TTCVi crate.
6. Develop the software for CSC calibration using PC control and readout.
7. Develop a database for storage the results of the tests.8. Commissioning new set-up for PC and on-chamber
electronics test.
Plans on 2006-2007
1. PC commissioning and integration with CSCs.
2. PC and CSC integration with XDAQ.
3. PC and CSCs integration with cross-DAQ (DQM).
M&O of CSC system 2008-2009
1. Full calibration of CSC and CSC’s electronics.2. Using particles coming from interaction point
make calibration of:I. HV sectors (18 for small CSC and 30 for big ones)II. Time adjustment of ALCT delays for precision BXIII. Trigger time adjustment of CSC in PCsIV. ALCT-CLCT trigger time decision for the chambers in
PCs
3. M&O of the system:– Control and monitoring CSC performance– CSC repair– Failed board replacement– Participation in data taking runs – shifts on duty