CMOS Design
Introduction
Integrated circuits: many transistors on one chip.Very Large Scale Integration (VLSI): very many
Metal Oxide Semiconductor (MOS) transistorFast, cheap, low-power transistorsComplementary: mixture of n- and p-type leads to less
power How to build your own simple CMOS chip
CMOS transistorsBuilding logic gates from transistorsTransistor layout and fabrication
Silicon Lattice
Transistors are built on a silicon substrateSilicon is a Group IV materialForms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
Dopants
Silicon is a semiconductorPure silicon has no free carriers and conducts poorlyAdding dopants increases the conductivityGroup V: extra electron (n-type)Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
NMOS Transistor
Four terminals: gate, source, drain, bodyGate – oxide – body stack looks like a capacitor
Gate and body are conductorsSiO2 (oxide) is a very good insulatorCalled metal – oxide – semiconductor (MOS) capacitorEven though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
NMOS Operation
Body is commonly tied to ground (0 V)When the gate is at a low voltage:
P-type body is at low voltageSource-body and drain-body diodes are OFFNo current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
Body is commonly tied to ground (0 V)When the gate is at a low voltage:
P-type body is at low voltageSource-body and drain-body diodes are OFFNo current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
NMOS Operation
PMOS Transistor
Similar, but doping and voltages reversedBody tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFBubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
Power Supply Voltage
GND = 0 VIn 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF ON
ON OFF
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
CMOS Inverter
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
3-input NAND Gate
Y pulls low if ALL inputs are 1Y pulls high if ANY input is 0
A
B
Y
C
CMOS Transistor Theory
Outline
IntroductionMOS CapacitornMOS I-V CharacteristicspMOS I-V CharacteristicsGate and Diffusion Capacitance
Introduction
So far, we have treated transistors as ideal switchesAn ON transistor passes a finite amount of current
Depends on terminal voltagesDerive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitanceI = C (DV/Dt) -> Dt = (C/I) DVCapacitance and current determine speed
Also explore what a “degraded level” really means
MOS Capacitor
Gate and body form MOS capacitorOperating modes
AccumulationDepletionInversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion regioninversion region
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminalsBy convention, source is terminal at lower voltageHence Vds 0
nMOS body is grounded. First assume source is 0 .Three regions of operation
CutoffLinearSaturation
nMOS Cutoff
No channelIds = 0
+-
Vgs = 0
n+ n+
+-
Vgd
p-type body
b
g
s d
nMOS Linear
Channel formsCurrent flows from d to s
e- from s to d
Ids increases with Vds
Similar to linear resistor
+-
Vgs > Vt
n+ n+
+-
Vgd = Vgs
+-
Vgs > Vt
n+ n+
+-
Vgs > Vgd > Vt
Vds = 0
0 < Vds < Vgs-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
nMOS Saturation
Channel pinches offIds independent of Vds
We say current saturatesSimilar to current source
+-
Vgs > Vt
n+ n+
+-
Vgd < Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
I-V Characteristics
In Linear region, Ids depends onHow much charge is in the channel?How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversionGate – oxide – channel
Qchannel =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.9)
polysilicongate
Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversionGate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.9)
polysilicongate
Carrier velocity
Charge is carried by e-Carrier velocity v proportional to lateral E-field
between source and drainv = mE m called mobilityE = Vds/L
Time for carrier to cross channel:t = L / v
nMOS Linear I-V
Now we knowHow much charge Qchannel is in the channelHow much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
ox = W
CL
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drainWhen Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
nMOS I-V Summary
Shockley 1st order transistor models
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
pMOS I-V
All dopings and voltages are inverted for pMOSMobility mp is determined by holes
Typically 2-3x lower than that of electrons mn
120 cm2/V*s in AMI 0.6 mm processThus pMOS must be wider to provide same current
In this class, assume mn / mp = 2
Capacitance
Any two conductors separated by an insulator have capacitance
Gate to channel capacitor is very importantCreates channel charge necessary for operation
Source and drain have capacitance to bodyAcross reverse-biased diodesCalled diffusion capacitance because it is associated with
source/drain diffusion
Gate Capacitance
Approximate channel as connected to sourceCgs = eoxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.90)
polysilicongate
Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitanceCapacitance depends on area and perimeter
Use small diffusion nodesComparable to Cg
for contacted diff½ Cg for uncontactedVaries with process
CMOS Fabrication
Overview of CMOSCMOS Fabrication Process OverviewCMOS Fabrication ProcessProblems with Current CMOS FabricationFuture Changes in CMOS Fabrication
Outline
Complementary metal–oxide–semiconductor (CMOS) Has many different uses:
Integrated Circuits Data converters Integrated transceivers Image sensors Logic circuits
What is CMOS?
NAND Circuit
What is CMOS?
CMOS Fabrication Process Overview
1. Create a pattern.2. Oxidize small layer,
about 1µm thick.3. Place photoresist on
top of SiO2
4. Place mask(pattern) above photoresist and expose it to UV light.
CMOS Fabrication Process
CMOS Fabrication Process
1. Etch away SiO2 using HF acid or plasma.
2. Remove remaining photoresist with acids.
CMOS Fabrication Process
To create a n well: Diffusion
Heat wafer in Arsenic gas chamber until diffusion occurs. Ion Implantation
Arsenic or phosphorous are implanted in window.
n well
SiO2
CMOS Fabrication Process
CMOS Fabrication Process
A thin layer of oxide is deposited.
A thin layer of polysilicon is deposited using Chemical Vapor Deposition (CVD) .
p substraten well
CMOS Fabrication Process
Remove oxide layer using acid.
Dope open area using Ion implantation or diffusion.
p substraten well
n+n+ n+p+p+p+
CMOS Fabrication Process
p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
CMOS Fabrication Process
CMOS Fabrication Process
Problems with Current CMOS Fabrication
Optical lithography is limited by the light frequency.
Material limitationsYield limitationsSpace limitations
Future Changes in CMOS Fabrication
Material changes like using high-k materials.
Design changesSOI(Silicon On Insulator)Double Gate (Finfet)Twin-Tub Process
DC Characteristics of a CMOS Inveter
DC Characteristics of a CMOS Inverter
A complementary CMOS inverter consists of a p-type and an n-type device connected in series.
The DC transfer characteristics of the inverter are a function of the output voltage (Vout) with respect to the input voltage (Vin).
The MOS device first order Shockley equations describing the transistors in cut-off, linear and saturation modes can be used to generate the transfer characteristics of a CMOS inverter.
Plotting these equations for both the n- and p-type devices produces the traces below.
IV Curves for nMOS
PMOS IV Curves
The DC transfer characteristic curve is determined by plotting the common points of Vgs intersection after taking the absolute value of the p-device IV curves, reflecting them about the x-axis and superimposing them on the n-device IV curves.
We basically solve for Vin(n-type) = Vin(p-type) and Ids(n-type)=Ids(p-type)
The desired switching point must be designed to be 50 % of magnitude of the supply voltage i.e. VDD/2.
Analysis of the superimposed n-type and p-type IV curves results in five regions in which the inverter operates.
Region A occurs when 0 leqVin leq Vt(n-type).
The n-device is in cut-off (Idsn =0).p-device is in linear region,Idsn = 0 therefore -Idsp = 0Vdsp = Vout – VDD, but Vdsp =0 leading to an output of Vout = VDD.
Region B occurs when the condition Vtn leq Vin le VDD/2 is met.
Here p-device is in its non-saturated region Vds neq 0.n-device is in saturation
Saturation current Idsn is obtained by setting Vgs = Vin resulting in the equation:
CMOS Inverter DC Characteristics
CMOS Inverter Transfer Characteristics
In region B Idsp is governed by voltages Vgs and Vds described by:
22
: thatRecall
2
22
2
DDoutDDouttpDDinptnin
n
dspdsn
DDoutDDouttpDDinpdsp
VVVVVVVVV
II
VVVVVVVI
DDoutdsDDings VVVVVV and
Region C has that both n- and p-devices are in saturation.
Saturation currents for the two devices are:
tnintninn
dsn
DDtpintpDDinp
dsp
VVVVI
VVVVVVI
;2
AND
;2
2
2
Region D is defined by the inequality
p-device is in saturation while n-device is in its non-saturation region.
Equating the drain currents allows us to solve for Vout. (See supplemental notes for algebraic manipulations).
tpDDinDD VVV
V
2
tninout
outtninndsn
DDtpintpDDinp
dsp
VVV
VVVI
VVVVVVI
;2
AND
;2
2
2
CMOS Inverter Static Charateristics
In Region E the input condition satisfies:
The p-type device is in cut-off: Idsp=0
The n-type device is in linear modeVgsp = Vin –VDD and this is a more positive value compared
to Vtp.
Vout = 0
tpDDin VVV
nMOS & pMOS Operating points
nMOS & pMOS Operating points
A
C
B
D E
Vtp Vtn
VDD
0VDD/2 VDD+Vtp VDD
Both in satnMOS in satpMOS in sat
Out
put V
olta
ge
Vout =Vin-Vtp
Vout =Vin-Vtn
Circuits & Layout
Outline
CMOS Gate DesignPass TransistorsCMOS Latches & Flip-FlopsStandard Cell LayoutsStick Diagrams
CMOS Gate Design
Activity:Sketch a 4-input CMOS NOR gate
A
B
C
DY
Complementary CMOS
Complementary CMOS logic gatesnMOS pull-down networkpMOS pull-up networka.k.a. static CMOS
pMOSpull-upnetwork
outputinputs
nMOSpull-downnetwork
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
Series and Parallel
nMOS: 1 = ONpMOS: 0 = ONSeries: both must be ONParallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
Conduction Complement
Complementary CMOS gates always produce 0 or 1Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1Thus Y=1 when either input is 0Requires parallel pMOS
Rule of Conduction ComplementsPull-up network is complement of pull-downParallel -> series, series -> parallel
A
B
Y
Compound Gates
Compound gates can do any inverting functionEx:
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
Example: O3AI
A B
Y
C
D
DC
B
A
Y = ((A+B+C).D)’
Signal Strength
Strength of signalHow close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0nMOS pass strong 0
But degraded or weak 1pMOS pass strong 1
But degraded or weak 0Thus nMOS are best for pull-down network
Pass Transistors
g
s d
g
s d
Transistors can be used as switches
Pass Transistors
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
Transistors can be used as switches
Transmission Gates
Pass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
Tristates
EN A Y
0 0
0 1
1 0
1 1
A Y
EN
A Y
EN
EN
Tristate buffer produces Z when not enabled
Nonrestoring Tristate
Transmission gate acts as tristate bufferOnly two transistorsBut nonrestoring
Noise on A is passed on to Y
A Y
EN
EN
Tristate Inverter
Tristate inverter produces restored outputViolates conduction complement ruleBecause we want a Z output
A
YEN
EN
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
Tristate inverter produces restored outputViolates conduction complement ruleBecause we want a Z output
Tristate Inverter
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X
0
1
S
D0
D1Y
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1Y
Multiplexers
Gate-Level Mux Design
How many transistors are needed? 20
44
D1
D0S Y
4
2
2
2 Y2
D1
D0S
1 0 (too many transistors)Y SD SD
Transmission Gate Mux
Nonrestoring mux uses two transmission gatesOnly 4 transistors
S
S
D0
D1
YS
Inverting Mux
Inverting multiplexerUse compound AOI22Or pair of tristate invertersEssentially the same thing
Non inverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selectsTwo levels of 2:1 muxesOr four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
D Latch
When CLK = 1, latch is transparentD flows through to Q like a buffer
When CLK = 0, the latch is opaqueQ holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
D Latch
D Latch Design
Circuits and LayoutSlide 90
Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
D Flip-flop
When CLK rises, D is copied to QAt all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
Flo
p
CLK
D Q
D
CLK
Q
D Flip-flop Design
Built from master and slave D latches
QM
CLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
Race Condition
Back-to-back flops can malfunction from clock skewSecond flip-flop fires lateSees first flip-flop change and captures its resultCalled hold-time failure or race condition
CLK1
D Q1
Flo
p
Flo
p
CLK2
Q2
CLK1
CLK2
Q1
Q2
Non overlapping Clocks
Non overlapping clocks can prevent racesAs long as non overlap exceeds clock skew
We will use them in this class for safe designIndustry manages skew more carefully instead
1
11
1
2
22
2
2
1
QMQD
Stick Diagram & Scalable Stick Diagram & Scalable Design RulesDesign Rules
IC Layout Concept
Stick Diagram Design Rules Layout Verification
Basic Concept
Based on the view point of IC layout, the stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.
Legend:
contactmetal 2metal 1
polyndiffpdiff
VDD
in
VSS
out
■
Although the stick diagram is an abstract presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2-diomensional plane and reach the aim same as the physical layout does.
The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices, it still can reflect the real condition to layout of the silicon chip.
Basic Concept
Notations of the stick diagram
Intermediate representation between the transistor level and the mask (layout) level.
Gives topological information (identifies different layers and their relationship)
Assumes that wires have no width. It is possible
to translate stick diagram automatically to layout with correct design rules.
Stick Diagram
Stick Diagram
When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.
When polysilicon crosses N or P diffusion, an N or P transistor is formed. Polysilicon is drawn on top of diffusion.Diffusion must be drawn connecting the source and the
drain.Gate is automatically self-aligned during fabrication.
When a metal line needs to be connected to one of the other three conductors, a contact cut (via) is required.
Stick Diagram
Manhattan geometrical rule: When we use only vertical and horizontal lines In orthogonal to describe circuitry.
Boston geometrical rule: The stick diagram also allows curves to describe circuitry.
In order to describe N/PMOS more completely, to add n-well 、P+ select 、 well contact and substrate contact are optional for 4-terminal notation.
Stick Diagram
Conclusion
Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout.
Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location.
Stick diagram doesn’t include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.
CMOS Inverter Stick Diagrams
Basic layout
․ More area efficient layout
CMOS inverter described in other way.
VDD
in
VSS
out
CMOS Inverter Stick Diagrams
The transmission gate Circuit schematic Stick diagram
CMOS Transmission Gate
CMOS Stick DiagramsNAND/NOR
CMOS Stick Diagrams NAND
< Exercise 1 >
To draw the following circuitry by using a stick diagram
CMOS Stick Diagrams NOR
Lambda-based Design Rules
Lambda design rules are based on a reference metric λthat has units of um.
All widths, spacing and distances are written in the form Value = m λ
Where m is scaling multiplier.
<e.g.> λ= 1um w = 2 λ=2um
s = 3λ=3um
Lambda-based Design RulesLambda based design: half of technology since 1985. As technologychanges with smaller dimensions, a simple change in the value of can be used to produce a new mask set.
All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3
6
2
6
3
3
Active Contact and Surround Rule
Example of surrounded design rule
Potential Problem - Misalignment
Misalignment –induced defect
Potential Problem – Short between Source and Drain
Example of an extended (gate over hang)design rule
Design Rule (0)
Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment.
In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule。
The purpose of design rules
Interface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width
scalable design rules: lambda parameterabsolute dimensions (micron rules)
Design Rule (1)
Layout rules are used for preparing the masks for fabrication.Fabrication processes have inherent limitations in accuracy.Design rules specify geometry of masks to optimize yield and
reliability (trade-offs: area, yield, reliability).Three major rules:
Wire width: Minimum dimension associated with a given feature.
Wire separation: Allowable separation.Contact: overlap rules.
Two major approaches:“Micron” rules: stated at micron resolution. rules: simplified micron rules with limited scaling
attributes. may be viewed as the size of minimum feature.Design rules represents a tolerance which insures very high
probability of correct fabrication (not a hard boundary between correct and incorrect fabrication).
Design rules are determined by experience.
Design Rule (2)
Terminology & Definition
Min. Width : The min. width of the line (layer) <Example> Wpoly(min.) = 0.5um
Min. Space : The min. spacing between lines with same material
<Example> Spoly-poly(min.) = 0.5um
Terminology & Definition
<Min. Extension : The min. extension over different layers
<Example> Poly-gate extension over diffusion area = 0.55um
Min. Overlap : The overlap between different layers
<Example> Poly1 overlap Poly2 min. = 0.7um
Max. area of the specific region. <Example> Bonding Pad Area, max. =
100um x 100um
Terminology & Definition
Conventional Layer Definition
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
IntraIntra--Layer Design RulesLayer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
SCMOS Design Rules
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
SCMOS Design Rules
1
3 3
2
2
2
WellSubstrate
Select3
5
SCMOS Design Rules
MOSIS Layout Design Rules
3 basic design rules: Wire widthWire separationContact rule
Layout Verification
DRC – Design Rule CheckERC – Electrical Rule CheckLVS – Layout Versus SchematicLPE – Layout Parameter Extraction
Layout Verification
DRC(Design Rule Check): => To check the min. line width and spacing
based on the design rules.
ERC(Electrical Rule Check): => To check the short circuit between Power
and Ground, or check the floating node or devices.
LVS(Layout versus Schematic): => To verify the consistency between Schematic and
Layout. For example : to check the amount of transistor numbers, sizes of W/L.
LPE or PEX(Layout Parameter Extraction): => From the database of layout, to extract the devices
with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation。
Layout Verification
Simulations
Pre-Layout Simulation - before layout workPost-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.
Layout Verification
The complete design environment of Fill-Custom Design Design database – Cadence Design Framework IICircuit Editor – Text editor/Schematic editor (S-edit, Composer)Circuit Simulator – SPICE,TSPICE, HSPICELayout Editor – Cadence Virtuoso, Laker, L-editLayout Verification Diva, Dracula, Calibre, Hercules
Layout Verification
Concluding Remarks
Milestones technology in silicon eraTransistor Integrated Circuits CMOS
TechnologyKey weapons in SOC era
Design AutomationDesign Reuse
Breakthrough techniques in design automationSimulation (e.g., SPICE, Verilog-XL, etc.)Automatic Placement and Routing (APR)Logic Synthesis (e.g., Design Compiler)Formal VerificationTest Pattern Generation
It is EDA that pushes the IC design technology forward !